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This commit is contained in:
JanLJL
2025-03-05 10:40:18 +01:00
parent 799acd5c20
commit b7e5df0a08
2 changed files with 162 additions and 158 deletions
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266
tests/test_parser_x86intel.py
View File

@@ -43,7 +43,7 @@ class TestParserX86Intel(unittest.TestCase):
self.assertEqual(self._get_label(self.parser, "$$B1?10:")[0].name, "$$B1?10") self.assertEqual(self._get_label(self.parser, "$$B1?10:")[0].name, "$$B1?10")
self.assertEqual( self.assertEqual(
self._get_label(self.parser, "$LN9:\tcall\t__CheckForDebuggerJustMyCode")[0].name, self._get_label(self.parser, "$LN9:\tcall\t__CheckForDebuggerJustMyCode")[0].name,
"$LN9" "$LN9",
) )
self.assertEqual( self.assertEqual(
self._get_label(self.parser, "$LN9:\tcall\t__CheckForDebuggerJustMyCode")[1], self._get_label(self.parser, "$LN9:\tcall\t__CheckForDebuggerJustMyCode")[1],
@@ -57,28 +57,34 @@ class TestParserX86Intel(unittest.TestCase):
label_id=None, label_id=None,
line=None, line=None,
line_number=None, line_number=None,
) ),
) )
def test_directive_parser(self): def test_directive_parser(self):
self.assertEqual(self._get_directive(self.parser, "\t.allocstack 16")[0], self.assertEqual(
DirectiveOperand(name=".allocstack", self._get_directive(self.parser, "\t.allocstack 16")[0],
parameters=["16"])) DirectiveOperand(name=".allocstack", parameters=["16"]),
self.assertEqual(self._get_directive(self.parser, "INCLUDELIB MSVCRTD")[0], )
DirectiveOperand(name="INCLUDELIB", self.assertEqual(
parameters=["MSVCRTD"])) self._get_directive(self.parser, "INCLUDELIB MSVCRTD")[0],
self.assertEqual(self._get_directive(self.parser, "msvcjmc\tSEGMENT")[0], DirectiveOperand(name="INCLUDELIB", parameters=["MSVCRTD"]),
DirectiveOperand(name="SEGMENT", )
parameters=["msvcjmc"])) self.assertEqual(
self.assertEqual(self._get_directive(self.parser, "EXTRN\t_RTC_InitBase:PROC")[0], self._get_directive(self.parser, "msvcjmc\tSEGMENT")[0],
DirectiveOperand(name="EXTRN", DirectiveOperand(name="SEGMENT", parameters=["msvcjmc"]),
parameters=["_RTC_InitBase:PROC"])) )
self.assertEqual(self._get_directive(self.parser, "$pdata$kernel DD imagerel $LN9")[0], self.assertEqual(
DirectiveOperand(name="DD", self._get_directive(self.parser, "EXTRN\t_RTC_InitBase:PROC")[0],
parameters=["$pdata$kernel", "imagerel", "$LN9"])) DirectiveOperand(name="EXTRN", parameters=["_RTC_InitBase:PROC"]),
self.assertEqual(self._get_directive(self.parser, "repeat$ = 320")[0], )
DirectiveOperand(name="=", self.assertEqual(
parameters=["repeat$", "320"])) self._get_directive(self.parser, "$pdata$kernel DD imagerel $LN9")[0],
DirectiveOperand(name="DD", parameters=["$pdata$kernel", "imagerel", "$LN9"]),
)
self.assertEqual(
self._get_directive(self.parser, "repeat$ = 320")[0],
DirectiveOperand(name="=", parameters=["repeat$", "320"]),
)
def test_parse_instruction(self): def test_parse_instruction(self):
instr1 = "\tsub\trsp, 296\t\t\t\t; 00000128H" instr1 = "\tsub\trsp, 296\t\t\t\t; 00000128H"
@@ -110,93 +116,93 @@ class TestParserX86Intel(unittest.TestCase):
parsed_13 = self.parser.parse_instruction(instr13) parsed_13 = self.parser.parse_instruction(instr13)
self.assertEqual(parsed_1.mnemonic, "sub") self.assertEqual(parsed_1.mnemonic, "sub")
self.assertEqual(parsed_1.operands[0], self.assertEqual(parsed_1.operands[0], RegisterOperand(name="RSP"))
RegisterOperand(name="RSP")) self.assertEqual(parsed_1.operands[1], ImmediateOperand(value=296))
self.assertEqual(parsed_1.operands[1],
ImmediateOperand(value=296))
self.assertEqual(parsed_1.comment, "00000128H") self.assertEqual(parsed_1.comment, "00000128H")
self.assertEqual(parsed_2.mnemonic, "fst") self.assertEqual(parsed_2.mnemonic, "fst")
self.assertEqual(parsed_2.operands[0], self.assertEqual(parsed_2.operands[0], RegisterOperand(name="ST(3)"))
RegisterOperand(name="ST(3)"))
self.assertEqual(parsed_2.comment, "Good ol' x87.") self.assertEqual(parsed_2.comment, "Good ol' x87.")
self.assertEqual(parsed_3.mnemonic, "mulsd") self.assertEqual(parsed_3.mnemonic, "mulsd")
self.assertEqual(parsed_3.operands[0], self.assertEqual(parsed_3.operands[0], RegisterOperand(name="XMM0"))
RegisterOperand(name="XMM0")) self.assertEqual(
self.assertEqual(parsed_3.operands[1], parsed_3.operands[1],
MemoryOperand(base=RegisterOperand(name="RDX"), MemoryOperand(
index=RegisterOperand(name="RCX"), base=RegisterOperand(name="RDX"), index=RegisterOperand(name="RCX"), scale=8
scale=8)) ),
)
self.assertEqual(parsed_4.mnemonic, "mov") self.assertEqual(parsed_4.mnemonic, "mov")
self.assertEqual(parsed_4.operands[0], self.assertEqual(parsed_4.operands[0], RegisterOperand(name="EAX"))
RegisterOperand(name="EAX"))
self.assertEqual( self.assertEqual(
parsed_4.operands[1], parsed_4.operands[1],
MemoryOperand( MemoryOperand(
offset=ImmediateOperand(identifier="cur_elements$", value=104), offset=ImmediateOperand(identifier="cur_elements$", value=104),
base=RegisterOperand(name="RBP") base=RegisterOperand(name="RBP"),
) ),
) )
self.assertEqual(parsed_5.mnemonic, "mov") self.assertEqual(parsed_5.mnemonic, "mov")
self.assertEqual(parsed_5.operands[0], self.assertEqual(
MemoryOperand(offset=ImmediateOperand(value=24), parsed_5.operands[0],
base=RegisterOperand(name="RSP"))) MemoryOperand(offset=ImmediateOperand(value=24), base=RegisterOperand(name="RSP")),
self.assertEqual(parsed_5.operands[1], )
RegisterOperand(name="R8")) self.assertEqual(parsed_5.operands[1], RegisterOperand(name="R8"))
self.assertEqual(parsed_6.mnemonic, "jmp") self.assertEqual(parsed_6.mnemonic, "jmp")
self.assertEqual(parsed_6.operands[0], self.assertEqual(parsed_6.operands[0], LabelOperand(name="$LN2@kernel"))
LabelOperand(name="$LN2@kernel"))
self.assertEqual(parsed_7.mnemonic, "lea") self.assertEqual(parsed_7.mnemonic, "lea")
self.assertEqual(parsed_7.operands[0], self.assertEqual(parsed_7.operands[0], RegisterOperand(name="RCX"))
RegisterOperand(name="RCX")) self.assertEqual(
self.assertEqual(parsed_7.operands[1], parsed_7.operands[1],
MemoryOperand(offset=IdentifierOperand(name="__FAC6D534_triad@c"))) MemoryOperand(offset=IdentifierOperand(name="__FAC6D534_triad@c")),
)
self.assertEqual(parsed_8.mnemonic, "mov") self.assertEqual(parsed_8.mnemonic, "mov")
self.assertEqual(parsed_8.operands[0], self.assertEqual(
MemoryOperand( parsed_8.operands[0],
base=RegisterOperand(name="GS"), MemoryOperand(base=RegisterOperand(name="GS"), offset=ImmediateOperand(value=111)),
offset=ImmediateOperand(value=111))) )
self.assertEqual(parsed_8.operands[1], self.assertEqual(parsed_8.operands[1], RegisterOperand(name="AL"))
RegisterOperand(name="AL"))
self.assertEqual(parsed_9.mnemonic, "lea") self.assertEqual(parsed_9.mnemonic, "lea")
self.assertEqual(parsed_9.operands[0], self.assertEqual(parsed_9.operands[0], RegisterOperand(name="R8"))
RegisterOperand(name="R8")) self.assertEqual(
self.assertEqual(parsed_9.operands[1], parsed_9.operands[1],
MemoryOperand(base=None, MemoryOperand(base=None, index=RegisterOperand(name="R8"), scale=4),
index=RegisterOperand(name="R8"), )
scale=4))
self.assertEqual(parsed_10.mnemonic, "movsd") self.assertEqual(parsed_10.mnemonic, "movsd")
self.assertEqual(parsed_10.operands[0], self.assertEqual(parsed_10.operands[0], RegisterOperand(name="XMM1"))
RegisterOperand(name="XMM1")) self.assertEqual(
self.assertEqual(parsed_10.operands[1], parsed_10.operands[1],
MemoryOperand(offset=IdentifierOperand(name="boost@@XZ@4V456@A", MemoryOperand(
offset=ImmediateOperand(value=16)))) offset=IdentifierOperand(
name="boost@@XZ@4V456@A", offset=ImmediateOperand(value=16)
)
),
)
self.assertEqual(parsed_11.mnemonic, "lea") self.assertEqual(parsed_11.mnemonic, "lea")
self.assertEqual(parsed_11.operands[0], self.assertEqual(parsed_11.operands[0], RegisterOperand(name="RCX"))
RegisterOperand(name="RCX")) self.assertEqual(
self.assertEqual(parsed_11.operands[1], parsed_11.operands[1],
MemoryOperand(offset=IdentifierOperand(name="??_R0N@8", MemoryOperand(
offset=ImmediateOperand(value=8)))) offset=IdentifierOperand(name="??_R0N@8", offset=ImmediateOperand(value=8))
),
)
self.assertEqual(parsed_12.mnemonic, "vfmadd213sd") self.assertEqual(parsed_12.mnemonic, "vfmadd213sd")
self.assertEqual(parsed_12.operands[0], self.assertEqual(parsed_12.operands[0], RegisterOperand(name="XMM0"))
RegisterOperand(name="XMM0")) self.assertEqual(parsed_12.operands[1], RegisterOperand(name="XMM1"))
self.assertEqual(parsed_12.operands[1], self.assertEqual(
RegisterOperand(name="XMM1")) parsed_12.operands[2],
self.assertEqual(parsed_12.operands[2], MemoryOperand(offset=IdentifierOperand(name="__real@bfc5555555555555")),
MemoryOperand(offset=IdentifierOperand(name="__real@bfc5555555555555"))) )
self.assertEqual(parsed_13.mnemonic, "jmp") self.assertEqual(parsed_13.mnemonic, "jmp")
self.assertEqual(parsed_13.operands[0], self.assertEqual(parsed_13.operands[0], IdentifierOperand(name="$LN18@operator"))
IdentifierOperand(name="$LN18@operator"))
def test_parse_line(self): def test_parse_line(self):
line_comment = "; -- Begin main" line_comment = "; -- Begin main"
@@ -257,63 +263,85 @@ class TestParserX86Intel(unittest.TestCase):
operands=[ operands=[
MemoryOperand( MemoryOperand(
base=RegisterOperand("RBP"), base=RegisterOperand("RBP"),
offset=ImmediateOperand(value=4, identifier="r$1") offset=ImmediateOperand(value=4, identifier="r$1"),
), ),
ImmediateOperand(value=0) ImmediateOperand(value=0),
], ],
line="\tmov\tDWORD PTR r$1[rbp], 0", line="\tmov\tDWORD PTR r$1[rbp], 0",
line_number=73 line_number=73,
) ),
) )
# Check a few lines to make sure that we produced something reasonable. # Check a few lines to make sure that we produced something reasonable.
self.assertEqual(parsed[60], self.assertEqual(
InstructionForm(mnemonic="mov", parsed[60],
operands=[MemoryOperand(base=RegisterOperand("RSP"), InstructionForm(
offset=ImmediateOperand(value=8)), mnemonic="mov",
RegisterOperand(name="RCX")], operands=[
line="\tmov\tQWORD PTR [rsp+8], rcx", MemoryOperand(base=RegisterOperand("RSP"), offset=ImmediateOperand(value=8)),
line_number=64)) RegisterOperand(name="RCX"),
self.assertEqual(parsed[120], ],
InstructionForm(directive_id=DirectiveOperand(name="END"), line="\tmov\tQWORD PTR [rsp+8], rcx",
line="END", line_number=64,
line_number=124)) ),
)
self.assertEqual(
parsed[120],
InstructionForm(
directive_id=DirectiveOperand(name="END"), line="END", line_number=124
),
)
self.assertEqual(len(parsed), 121) self.assertEqual(len(parsed), 121)
def test_parse_file2(self): def test_parse_file2(self):
parsed = self.parser.parse_file(self.triad_iaca_code) parsed = self.parser.parse_file(self.triad_iaca_code)
self.assertEqual(parsed[0].line_number, 1) self.assertEqual(parsed[0].line_number, 1)
# Check a few lines to make sure that we produced something reasonable. # Check a few lines to make sure that we produced something reasonable.
self.assertEqual(parsed[68], self.assertEqual(
InstructionForm(directive_id=DirectiveOperand(name="=", parsed[68],
parameters=["s$", "88"]), InstructionForm(
line="s$ = 88", directive_id=DirectiveOperand(name="=", parameters=["s$", "88"]),
line_number=72)) line="s$ = 88",
self.assertEqual(parsed[135], line_number=72,
InstructionForm(directive_id=DirectiveOperand(name="END"), ),
line="END", )
line_number=139)) self.assertEqual(
parsed[135],
InstructionForm(
directive_id=DirectiveOperand(name="END"), line="END", line_number=139
),
)
self.assertEqual(len(parsed), 136) self.assertEqual(len(parsed), 136)
def test_parse_file3(self): def test_parse_file3(self):
parsed = self.parser.parse_file(self.gs_icc_code) parsed = self.parser.parse_file(self.gs_icc_code)
self.assertEqual(parsed[0].line_number, 1) self.assertEqual(parsed[0].line_number, 1)
# Check a few lines to make sure that we produced something reasonable. # Check a few lines to make sure that we produced something reasonable.
self.assertEqual(parsed[113], self.assertEqual(
InstructionForm(mnemonic="vmovsd", parsed[113],
operands=[RegisterOperand("XMM5"), InstructionForm(
MemoryOperand(base=RegisterOperand("R11"), mnemonic="vmovsd",
index=RegisterOperand("R10"), operands=[
scale=1, RegisterOperand("XMM5"),
offset=ImmediateOperand(value=16))], MemoryOperand(
comment_id="26.19", base=RegisterOperand("R11"),
line=" vmovsd xmm5, QWORD PTR [16+r11+r10]" index=RegisterOperand("R10"),
+ " #26.19", scale=1,
line_number=114)) offset=ImmediateOperand(value=16),
self.assertEqual(parsed[226], ),
InstructionForm(directive_id=DirectiveOperand(name=".long", ],
parameters=["681509"]), comment_id="26.19",
line=" .long 681509", line=" vmovsd xmm5, QWORD PTR [16+r11+r10]" + " #26.19",
line_number=227)) line_number=114,
),
)
self.assertEqual(
parsed[226],
InstructionForm(
directive_id=DirectiveOperand(name=".long", parameters=["681509"]),
line=" .long 681509",
line_number=227,
),
)
self.assertEqual(len(parsed), 227) self.assertEqual(len(parsed), 227)
def test_normalize_imd(self): def test_normalize_imd(self):
@@ -342,9 +370,7 @@ class TestParserX86Intel(unittest.TestCase):
################## ##################
def _get_comment(self, parser, comment): def _get_comment(self, parser, comment):
return " ".join( return " ".join(
parser.process_operand(parser.comment.parseString(comment, parseAll=True))[ parser.process_operand(parser.comment.parseString(comment, parseAll=True))["comment"]
"comment"
]
) )
def _get_label(self, parser, label): def _get_label(self, parser, label):

54
tests/test_semantics.py
View File

@@ -54,40 +54,31 @@ class TestSemanticTools(unittest.TestCase):
with open(cls._find_file("kernel_aarch64_deps.s")) as f: with open(cls._find_file("kernel_aarch64_deps.s")) as f:
cls.code_AArch64_deps = f.read() cls.code_AArch64_deps = f.read()
cls.kernel_x86 = reduce_to_section( cls.kernel_x86 = reduce_to_section(
cls.parser_x86_att.parse_file(cls.code_x86), cls.parser_x86_att.parse_file(cls.code_x86), cls.parser_x86_att
cls.parser_x86_att
) )
cls.kernel_x86_memdep = reduce_to_section( cls.kernel_x86_memdep = reduce_to_section(
cls.parser_x86_att.parse_file(cls.code_x86_memdep), cls.parser_x86_att.parse_file(cls.code_x86_memdep), cls.parser_x86_att
cls.parser_x86_att
) )
cls.kernel_x86_long_LCD = reduce_to_section( cls.kernel_x86_long_LCD = reduce_to_section(
cls.parser_x86_att.parse_file(cls.code_x86_long_LCD), cls.parser_x86_att.parse_file(cls.code_x86_long_LCD), cls.parser_x86_att
cls.parser_x86_att
) )
cls.kernel_x86_intel = reduce_to_section( cls.kernel_x86_intel = reduce_to_section(
cls.parser_x86_intel.parse_file(cls.code_x86_intel), cls.parser_x86_intel.parse_file(cls.code_x86_intel), cls.parser_x86_intel
cls.parser_x86_intel
) )
cls.kernel_x86_intel_memdep = reduce_to_section( cls.kernel_x86_intel_memdep = reduce_to_section(
cls.parser_x86_intel.parse_file(cls.code_x86_intel_memdep), cls.parser_x86_intel.parse_file(cls.code_x86_intel_memdep), cls.parser_x86_intel
cls.parser_x86_intel
) )
cls.kernel_AArch64 = reduce_to_section( cls.kernel_AArch64 = reduce_to_section(
cls.parser_AArch64.parse_file(cls.code_AArch64), cls.parser_AArch64.parse_file(cls.code_AArch64), cls.parser_AArch64
cls.parser_AArch64
) )
cls.kernel_aarch64_memdep = reduce_to_section( cls.kernel_aarch64_memdep = reduce_to_section(
cls.parser_AArch64.parse_file(cls.code_aarch64_memdep), cls.parser_AArch64.parse_file(cls.code_aarch64_memdep), cls.parser_AArch64
cls.parser_AArch64
) )
cls.kernel_aarch64_SVE = reduce_to_section( cls.kernel_aarch64_SVE = reduce_to_section(
cls.parser_AArch64.parse_file(cls.code_AArch64_SVE), cls.parser_AArch64.parse_file(cls.code_AArch64_SVE), cls.parser_AArch64
cls.parser_AArch64
) )
cls.kernel_aarch64_deps = reduce_to_section( cls.kernel_aarch64_deps = reduce_to_section(
cls.parser_AArch64.parse_file(cls.code_AArch64_deps), cls.parser_AArch64.parse_file(cls.code_AArch64_deps), cls.parser_AArch64
cls.parser_AArch64
) )
# set up machine models # set up machine models
@@ -438,10 +429,7 @@ class TestSemanticTools(unittest.TestCase):
# 5_______>9 # 5_______>9
# #
dg = KernelDG( dg = KernelDG(
self.kernel_x86, self.kernel_x86, self.parser_x86_att, self.machine_model_csx, self.semantics_csx
self.parser_x86_att,
self.machine_model_csx,
self.semantics_csx
) )
self.assertTrue(nx.algorithms.dag.is_directed_acyclic_graph(dg.dg)) self.assertTrue(nx.algorithms.dag.is_directed_acyclic_graph(dg.dg))
self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=3))), 1) self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=3))), 1)
@@ -472,7 +460,7 @@ class TestSemanticTools(unittest.TestCase):
self.kernel_x86_intel, self.kernel_x86_intel,
self.parser_x86_intel, self.parser_x86_intel,
self.machine_model_csx, self.machine_model_csx,
self.semantics_csx_intel self.semantics_csx_intel,
) )
self.assertTrue(nx.algorithms.dag.is_directed_acyclic_graph(dg.dg)) self.assertTrue(nx.algorithms.dag.is_directed_acyclic_graph(dg.dg))
self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=3))), 1) self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=3))), 1)
@@ -589,10 +577,7 @@ class TestSemanticTools(unittest.TestCase):
def test_cyclic_dag(self): def test_cyclic_dag(self):
dg = KernelDG( dg = KernelDG(
self.kernel_x86, self.kernel_x86, self.parser_x86_att, self.machine_model_csx, self.semantics_csx
self.parser_x86_att,
self.machine_model_csx,
self.semantics_csx
) )
dg.dg.add_edge(100, 101, latency=1.0) dg.dg.add_edge(100, 101, latency=1.0)
dg.dg.add_edge(101, 102, latency=2.0) dg.dg.add_edge(101, 102, latency=2.0)
@@ -659,10 +644,7 @@ class TestSemanticTools(unittest.TestCase):
lcd_id = "8" lcd_id = "8"
lcd_id2 = "5" lcd_id2 = "5"
dg = KernelDG( dg = KernelDG(
self.kernel_x86, self.kernel_x86, self.parser_x86_att, self.machine_model_csx, self.semantics_csx
self.parser_x86_att,
self.machine_model_csx,
self.semantics_csx
) )
lc_deps = dg.get_loopcarried_dependencies() lc_deps = dg.get_loopcarried_dependencies()
# self.assertEqual(len(lc_deps), 2) # self.assertEqual(len(lc_deps), 2)
@@ -695,7 +677,7 @@ class TestSemanticTools(unittest.TestCase):
self.kernel_x86_intel, self.kernel_x86_intel,
self.parser_x86_intel, self.parser_x86_intel,
self.machine_model_csx, self.machine_model_csx,
self.semantics_csx_intel self.semantics_csx_intel,
) )
lc_deps = dg.get_loopcarried_dependencies() lc_deps = dg.get_loopcarried_dependencies()
# self.assertEqual(len(lc_deps), 2) # self.assertEqual(len(lc_deps), 2)
@@ -804,14 +786,10 @@ class TestSemanticTools(unittest.TestCase):
self.semantics_csx_intel.normalize_instruction_form(instr_form_w_c) self.semantics_csx_intel.normalize_instruction_form(instr_form_w_c)
self.semantics_csx_intel.assign_src_dst(instr_form_w_c) self.semantics_csx_intel.assign_src_dst(instr_form_w_c)
instr_form_rw_ymm_1 = self.parser_x86_intel.parse_line( instr_form_rw_ymm_1 = self.parser_x86_intel.parse_line("vinsertf128 ymm1, ymm0, xmm1, 1")
"vinsertf128 ymm1, ymm0, xmm1, 1"
)
self.semantics_csx_intel.normalize_instruction_form(instr_form_rw_ymm_1) self.semantics_csx_intel.normalize_instruction_form(instr_form_rw_ymm_1)
self.semantics_csx_intel.assign_src_dst(instr_form_rw_ymm_1) self.semantics_csx_intel.assign_src_dst(instr_form_rw_ymm_1)
instr_form_rw_ymm_2 = self.parser_x86_intel.parse_line( instr_form_rw_ymm_2 = self.parser_x86_intel.parse_line("vinsertf128 ymm1, ymm1, xmm0, 1")
"vinsertf128 ymm1, ymm1, xmm0, 1"
)
self.semantics_csx_intel.normalize_instruction_form(instr_form_rw_ymm_2) self.semantics_csx_intel.normalize_instruction_form(instr_form_rw_ymm_2)
self.semantics_csx_intel.assign_src_dst(instr_form_rw_ymm_2) self.semantics_csx_intel.assign_src_dst(instr_form_rw_ymm_2)
instr_form_r_ymm = self.parser_x86_intel.parse_line("vmovapd ymm0, ymm1") instr_form_r_ymm = self.parser_x86_intel.parse_line("vmovapd ymm0, ymm1")