From bbb004a2aa3dc9dfbac947eff95aba4024170ef0 Mon Sep 17 00:00:00 2001 From: JanLJL Date: Wed, 18 Dec 2019 16:56:20 +0100 Subject: [PATCH] added default load TP and relocation in identifier --- osaca/data/bdw.yml | 1 + osaca/data/csx.yml | 5 +++++ osaca/data/hsw.yml | 1 + osaca/data/ivb.yml | 1 + osaca/data/skx.yml | 1 + osaca/data/snb.yml | 1 + osaca/data/tx2.yml | 1 + osaca/data/zen1.yml | 1 + osaca/frontend.py | 2 +- osaca/parser/parser_x86att.py | 2 ++ osaca/semantics/arch_semantics.py | 5 ++++- osaca/semantics/hw_model.py | 7 ++++++- 12 files changed, 25 insertions(+), 3 deletions(-) diff --git a/osaca/data/bdw.yml b/osaca/data/bdw.yml index ac0fc32..6bce1e7 100644 --- a/osaca/data/bdw.yml +++ b/osaca/data/bdw.yml @@ -16,6 +16,7 @@ load_throughput: - {base: gpr, index: gpr, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} - {base: gpr, index: gpr, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} - {base: gpr, index: gpr, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +load_throughput_default: [[1, '23'], [1, ['2D', '3D']]] ports: ['0', 0DV, '1', '2', 2D, '3', 3D, '4', '5', '6', '7'] port_model_scheme: | ┌------------------------------------------------------------------------┐ diff --git a/osaca/data/csx.yml b/osaca/data/csx.yml index 21ea669..9f20b51 100644 --- a/osaca/data/csx.yml +++ b/osaca/data/csx.yml @@ -12,10 +12,15 @@ load_throughput: - {base: gpr, index: ~, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} - {base: gpr, index: ~, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} - {base: gpr, index: ~, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: ~, offset: id, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: ~, offset: id, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} - {base: gpr, index: gpr, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} - {base: gpr, index: gpr, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} - {base: gpr, index: gpr, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} - {base: gpr, index: gpr, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: gpr, offset: id, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: gpr, offset: id, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +load_throughput_default: [[1, '23'], [1, ['2D', '3D']]] ports: ['0', 0DV, '1', '2', 2D, '3', 3D, '4', '5', '6', '7'] port_model_scheme: | ┌------------------------------------------------------------------------┐ diff --git a/osaca/data/hsw.yml b/osaca/data/hsw.yml index d396ecf..8735b91 100644 --- a/osaca/data/hsw.yml +++ b/osaca/data/hsw.yml @@ -16,6 +16,7 @@ load_throughput: - {base: gpr, index: ~, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} - {base: gpr, index: ~, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]} - {base: gpr, index: ~, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +load_throughput_default: [[1, '23'], [1, ['2D', '3D']]] ports: ['0', 0DV, '1', '2', '2D', '3', '3D', '4', '5', '6', '7'] port_model_scheme: | ┌------------------------------------------------------------------------┐ diff --git a/osaca/data/ivb.yml b/osaca/data/ivb.yml index 0e030de..a3b2513 100644 --- a/osaca/data/ivb.yml +++ b/osaca/data/ivb.yml @@ -16,6 +16,7 @@ load_throughput: - {base: gpr, index: ~, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} - {base: gpr, index: ~, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]} - {base: gpr, index: ~, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +load_throughput_default: [[1, '23'], [1, ['2D', '3D']]] ports: ['0', '0DV', '1', '2', '2D', '3', '3D', '4', '5'] port_model_scheme: | ┌-----------------------------------------------------┐ diff --git a/osaca/data/skx.yml b/osaca/data/skx.yml index faf38a2..b4f3a7b 100644 --- a/osaca/data/skx.yml +++ b/osaca/data/skx.yml @@ -16,6 +16,7 @@ load_throughput: - {base: gpr, index: gpr, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} - {base: gpr, index: gpr, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} - {base: gpr, index: gpr, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +load_throughput_default: [[1, '23'], [1, ['2D', '3D']]] ports: ['0', 0DV, '1', '2', 2D, '3', 3D, '4', '5', '6', '7'] port_model_scheme: | ┌------------------------------------------------------------------------┐ diff --git a/osaca/data/snb.yml b/osaca/data/snb.yml index 3b36118..69b25bb 100644 --- a/osaca/data/snb.yml +++ b/osaca/data/snb.yml @@ -16,6 +16,7 @@ load_throughput: - {base: gpr, index: ~, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} - {base: gpr, index: ~, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]} - {base: gpr, index: ~, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +load_throughput_default: [[1, '23'], [1, ['2D', '3D']]] ports: ['0', '0DV', '1', '2', '2D', '3', '3D', '4', '5'] port_model_scheme: | ┌-----------------------------------------------------┐ diff --git a/osaca/data/tx2.yml b/osaca/data/tx2.yml index 6a264d7..1eae10c 100644 --- a/osaca/data/tx2.yml +++ b/osaca/data/tx2.yml @@ -40,6 +40,7 @@ load_throughput: - {base: x, index: x, offset: imd, scale: 8, pre-indexed: false, post-indexed: false, port_pressure: [[1, '34']]} - {base: x, index: x, offset: imd, scale: 8, pre-indexed: true, post-indexed: true, port_pressure: [[1, '34']]} - {base: x, index: x, offset: imd, scale: 8, pre-indexed: true, post-indexed: false, port_pressure: [[1, '34']]} +load_throughput_default: [[1, '34']] ports: ['0', 0DV, '1', 1DV, '2', '3', '4', '5'] port_model_scheme: | ┌-----------------------------------------------------------┐ diff --git a/osaca/data/zen1.yml b/osaca/data/zen1.yml index 390f5bb..ab64df6 100644 --- a/osaca/data/zen1.yml +++ b/osaca/data/zen1.yml @@ -13,6 +13,7 @@ load_throughput: - {base: gpr, index: gpr, offset: ~, scale: 8, port_pressure: [[1, '89'], [1, ['8D','9D']]]} - {base: gpr, index: gpr, offset: imd, scale: 1, port_pressure: [[1, '89'], [1, ['8D','9D']]]} - {base: gpr, index: gpr, offset: imd, scale: 8, port_pressure: [[1, '89'], [1, ['8D','9D']]]} +load_throughput_default: [[1, '89'], [1, ['8D', '9D']]] hidden_loads: false ports: ['0', '1', '2', '3', 3DV, '4', '5', '6', '7', '8', '9', 8D, 9D, ST] port_model_scheme: | diff --git a/osaca/frontend.py b/osaca/frontend.py index 48c02a5..75cfca1 100755 --- a/osaca/frontend.py +++ b/osaca/frontend.py @@ -197,7 +197,7 @@ class Frontend(object): sums[dep] = sum( [instr_form['latency_lcd'] for instr_form in dep_dict[dep]['dependencies']] ) - lcd_sum = max(sums.values()) + lcd_sum = max(sums.values()) if len(sums) > 0 else 0.0 lcd_lines = [] longest_lcd = [line_no for line_no in sums if sums[line_no] == lcd_sum][0] lcd_lines = [d['line_number'] for d in dep_dict[longest_lcd]['dependencies']] diff --git a/osaca/parser/parser_x86att.py b/osaca/parser/parser_x86att.py index d7489ea..4cc2fb5 100755 --- a/osaca/parser/parser_x86att.py +++ b/osaca/parser/parser_x86att.py @@ -21,12 +21,14 @@ class ParserX86ATT(BaseParser): pp.ZeroOrMore(pp.Word(pp.printables)) ).setResultsName(self.COMMENT_ID) # Define x86 assembly identifier + relocation = pp.Combine(pp.Literal('@') + pp.Word(pp.alphas)) id_offset = pp.Word(pp.nums) + pp.Suppress(pp.Literal('+')) first = pp.Word(pp.alphas + '_.', exact=1) rest = pp.Word(pp.alphanums + '$_.') identifier = pp.Group( pp.Optional(id_offset).setResultsName('offset') + pp.Combine(first + pp.Optional(rest)).setResultsName('name') + + pp.Optional(relocation).setResultsName('relocation') ).setResultsName('identifier') # Label self.label = pp.Group( diff --git a/osaca/semantics/arch_semantics.py b/osaca/semantics/arch_semantics.py index ba7c19e..eb6802b 100755 --- a/osaca/semantics/arch_semantics.py +++ b/osaca/semantics/arch_semantics.py @@ -249,7 +249,10 @@ class ArchSemantics(ISASemantics): def convert_mem_to_reg(self, memory, reg_type, reg_id='0'): if self._isa == 'x86': - register = {'register': {'name': reg_type + reg_id}} + if reg_type == 'gpr': + register = {'register': {'name': 'r' + str(int(reg_id) + 9)}} + else: + register = {'register': {'name': reg_type + reg_id}} elif self._isa == 'aarch64': register = {'register': {'prefix': reg_type, 'name': reg_id}} return register diff --git a/osaca/semantics/hw_model.py b/osaca/semantics/hw_model.py index 8d1d8aa..6941eb4 100755 --- a/osaca/semantics/hw_model.py +++ b/osaca/semantics/hw_model.py @@ -155,7 +155,7 @@ class MachineModel(object): ld_tp = [m for m in self._data['load_throughput'] if self._match_mem_entries(memory, m)] if len(ld_tp) > 0: return ld_tp[0]['port_pressure'] - return None + return self._data['load_throughput_default'] def _match_mem_entries(self, mem, i_mem): if self._data['isa'].lower() == 'aarch64': @@ -490,6 +490,11 @@ class MachineModel(object): or (i_mem['offset'] is None and mem['offset']['value'] == '0') ) ) + or ( + mem['offset'] is not None + and 'identifier' in mem['offset'] + and i_mem['offset'] == 'id' + ) ) # check index and (