From 3435641451e58bc0770227c13324f8f64e2056d5 Mon Sep 17 00:00:00 2001 From: JanLJL Date: Mon, 4 Mar 2024 20:45:48 +0100 Subject: [PATCH 1/7] initial support Neoverse V2 --- README.rst | 86 +- osaca/data/v2.yml | 4613 +++++++++++++++++++++++++++++++++++ osaca/osaca.py | 4 +- osaca/semantics/hw_model.py | 1 + 4 files changed, 4662 insertions(+), 42 deletions(-) create mode 100644 osaca/data/v2.yml diff --git a/README.rst b/README.rst index 1efc795..06408b6 100644 --- a/README.rst +++ b/README.rst @@ -101,7 +101,7 @@ The usage of OSACA can be listed as: --arch ARCH needs to be replaced with the target architecture abbreviation. Possible options are ``SNB``, ``IVB``, ``HSW``, ``BDW``, ``SKX``, ``CSX``, ``ICL`` (Client), ``ICX`` (Server) for the latest Intel micro architectures starting from Intel Sandy Bridge and ``ZEN1``, ``ZEN2``, and ``ZEN3`` for AMD Zen architectures. - Furthermore, ``TX2`` for Marvell`s ARM-based ThunderX2 , ``N1`` for ARM's Neoverse, ``A72`` for ARM Cortex-A72, ``TSV110`` for the HiSilicon TaiShan v110, ``A64FX`` for Fujitsu's HPC ARM architecture, and ``M1`` for the Apple M1-Firestorm performance core are available. + Furthermore, ``TX2`` for Marvell`s ARM-based ThunderX2 , ``N1`` for ARM's Neoverse, ``A72`` for ARM Cortex-A72, ``TSV110`` for the HiSilicon TaiShan v110, ``A64FX`` for Fujitsu's HPC ARM architecture, ``M1`` for the Apple M1-Firestorm performance core, and ``V2`` for the Neoverse V2 (used in NVIDIA's Grace CPU) are available. If no micro-architecture is given, OSACA assumes a default architecture for x86/AArch64. --fixed Run the throughput analysis with fixed port utilization for all suitable ports per instruction. @@ -142,49 +142,53 @@ Supported microarchitectures ----------------------------- **x86 CPUs** -+---------+----------------+------------+ -|Designer | Model/microarch| OSACA flag | -+=========+================+============+ -| | | Sandy Bridge | ``SNB`` | -| | +----------------+------------+ -| | | Ivy Bridge | ``IVB`` | -| | +----------------+------------+ -| | | Haswell | ``HSW`` | -| | Intel +----------------+------------+ -| | | Broadwell | ``BDW`` | -| +----------------+------------+ -| | Skylake-X | ``SKX`` | -| +----------------+------------+ -| | Cascadelake-X | ``CSX`` | -| +----------------+------------+ -| | Icelake client | ``ICL`` | -| +----------------+------------+ -| | Icelake server | ``ICX`` | -+---------+----------------+------------+ -| | | Naples / Zen 1 | ``ZEN1`` | -| +----------------+------------+ -| | AMD | Rome / Zen 2 | ``ZEN2`` | -| +----------------+------------+ -| | | Milan / Zen 3 | ``ZEN3`` | -+---------+----------------+------------+ ++----------+----------------+------------+ +| Designer | Model/microarch| OSACA flag | ++==========+================+============+ +| | | Sandy Bridge | ``SNB`` | +| | +----------------+------------+ +| | | Ivy Bridge | ``IVB`` | +| | +----------------+------------+ +| | | Haswell | ``HSW`` | +| | Intel +----------------+------------+ +| | | Broadwell | ``BDW`` | +| +----------------+------------+ +| | Skylake-X | ``SKX`` | +| +----------------+------------+ +| | Cascadelake-X | ``CSX`` | +| +----------------+------------+ +| | Icelake client | ``ICL`` | +| +----------------+------------+ +| | Icelake server | ``ICX`` | ++----------+----------------+------------+ +| | | Naples / Zen 1 | ``ZEN1`` | +| +----------------+------------+ +| | AMD | Rome / Zen 2 | ``ZEN2`` | +| +----------------+------------+ +| | | Milan / Zen 3 | ``ZEN3`` | ++----------+----------------+------------+ **ARM AArch64 CPUs** -+---------+----------------+------------+ -|Designer | Model/microarch| OSACA flag | -+=========+================+============+ -| | | Cortex-A72 | ``A72`` | -| +----------------+------------+ -| | ARM | Neoverse N1 | ``N1`` | -+---------+----------------+------------+ -| Marvell | ThunderX2 | ``TX2`` | -+---------+----------------+------------+ -| Fujitsu | FX700/A64FX | ``A64FX`` | -+---------+----------------+------------+ -|HiSilicon| TaiShan v110 | ``TSV110``| -+---------+----------------+------------+ -| Apple | M1-Firestorm | ``M1`` | -+---------+----------------+------------+ ++-----------+-------------------+-------------+ +| Designer | Model/microarch | OSACA flag | ++===========+===================+=============+ +| | | Cortex-A72 | ``A72`` | +| +-------------------+-------------+ +| | ARM | Neoverse N1 | ``N1`` | +| +-------------------+-------------+ +| | | Neoverse V2 | ``V2`` | ++-----------+-------------------+-------------+ +| Marvell | ThunderX2 | ``TX2`` | ++-----------+-------------------+-------------+ +| Fujitsu | FX700/A64FX | ``A64FX`` | ++-----------+-------------------+-------------+ +| HiSilicon | TaiShan v110 | ``TSV110`` | ++-----------+-------------------+-------------+ +| Apple | M1-Firestorm | ``M1`` | ++-----------+-------------------+-------------+ +| NVIDIA | Neoverse V2/Grace | ``V2`` | ++-----------+-------------------+-------------+ ______________________ diff --git a/osaca/data/v2.yml b/osaca/data/v2.yml new file mode 100644 index 0000000..f7e8352 --- /dev/null +++ b/osaca/data/v2.yml @@ -0,0 +1,4613 @@ +osaca_version: 0.5.3 +micro_architecture: Arm Neoverse V2 +arch_code: v2 +isa: AArch64 +ROB_size: ~ +retired_uOps_per_cycle: ~ +scheduler_size: ~ +hidden_loads: false +load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 7.0, s: 6.0, d: 6.0, q: 6.0, v: 6.0, z: 6.0} +p_index_latency: 1 +load_throughput: +- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, ['12', '13', '14']]]} +- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '2367'], [1, ['12', '13', '14']]]} +- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '2367'], [1, ['12', '13', '14']]]} +load_throughput_default: [[1, ['12', '13', '14']]] +store_throughput: +- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, ['12', '13']], [1, ['15', '16']]]} +- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '2367'], [1, ['12', '13']], [1, ['15', '16']]]} +- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '2367'], [1, ['12', '13']], [1, ['15', '16']]]} +store_throughput_default: [[1, ['12', '13']], [1, ['15', '16']]] +ports: ['0', '1', '2', '3', '4', '5', '6','6DV', '7', '7DV', '8', '8DV', '9', '10', '10DV', '11', '12', '13', '14', '15', '16'] +port_model_scheme: | + +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + | BR = Branch | ISC = Int Single-Cycle | IMC = Int Multi-Cycle | FP = Floating-Point/SIMD,128bit | + +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + 0 |BR0 1 |BR1 2 |ISC0 3 |ISC1 4 |ISC2 5 |ISC3 6 |IMC0 7 |IMC1 8 |FP0 9 |FP1 10 |FP2 11 |FP3 12 |LDST 13 |LDST 14 |LD 15 |ST 16 |ST + \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ + +----+ +----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ +----+ +-------+ +----+ +-------+ +-------+ +----+ +-------+ +-----+ +-----+ +-----+ +-----+ +-----+ + | BR | | BR | | ALU | | ALU | | ALU | | ALU | | ALU | | DV | | ALU | | DV | |SIMD/FP| |FPDV| |SIMD/FP| |SIMD/FP| |FPDV| |SIMD/FP| | LD | | LD | | LD | | ST | | ST | + +----+ +----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ +----+ | ALU | +----+ | ALU | | ALU | +----+ | ALU | +-----+ +-----+ +-----+ +-----+ +-----+ + silly silly +------+ +------+ +-------+ +-------+ +-------+ +-------+ +-----+ +-----+ + | MUL | | MUL | +-------+ +-------+ +-------+ +-------+ | AGU | | AGU | + +------+ +------+ |SIMD/FP| |SIMD/FP| |SIMD/FP| |SIMD/FP| +-----+ +-----+ + +------+ +------+ | MISC | | MISC | | MISC | | MISC | + | CRC | | CRC | +-------+ +-------+ +-------+ +-------+ + +------+ +------+ +-------+ +-------+ +-------+ +-------+ + +------+ +------+ | SIMD | | SIMD | | SIMD | | SIMD | + | SHIFT| | SHIFT| |INT MUL| | SHIFT| |INT MUL| | SHIFT| + +------+ +------+ +-------+ +-------+ +-------+ +-------+ + +-------+ +-------+ +-------+ + | FPconv| | ST | | FPconv| + +-------+ +-------+ +-------+ + +-------+ +-------+ + | FPsqrt| | FPsqrt| + +-------+ +-------+ + +-------+ + | ST | + +-------+ +instruction_forms: +- name: adc + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: adcs + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.333333 + latency: 1.0 # 1*p{23}67 + port_pressure: [[1, '267']] +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.1666 + latency: 1.0 # 1*p245367 + port_pressure: [[1, '234567']] +- name: add + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: add + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.1666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: add + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: adds + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.333333 + latency: 1.0 # 1*p{23}67 + port_pressure: [[1, '267']] +- name: adds + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + throughput: 0.333333 + latency: 1.0 # 1*p{23}67 + port_pressure: [[1, '267']] +- name: adr + operands: + - class: register + prefix: '*' + - class: identifier + throughput: 0.25 + latency: ~ # 1*p67 + port_pressure: [[1, '2367']] +- name: and + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.16666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: and + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: and + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.16666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: and + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: ands + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.3333333 + latency: 1.0 # 1*p{23}67 + port_pressure: [[1, '267']] +- name: ands + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + throughput: 0.3333333 + latency: 1.0 # 1*p{23}67 + port_pressure: [[1, '267']] +- name: asr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: asr + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: [asr, asrv] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.16666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: asr + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: [b, bl, bcc, bcs, bgt, bhi, b.lo, b.ne, b.any, b.none, bal, b.al, b.lt, b.eq, b.hs, b.gt, b.hi, bne, beq] + operands: + - class: identifier + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '01']] +- name: bfc + operands: + - class: register + prefix: '*' + - class: immediate + imd: int + - class: immediate + imd: int + throughput: 0.5 + latency: 2.0 # 1*p67 + port_pressure: [[1, ['67']]] +- name: [bfi, bfm] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + - class: immediate + imd: int + throughput: 0.5 + latency: 2.0 # 1*p67 + port_pressure: [[1, ['67']]] +- name: bic + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.16666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: bics + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.33333333 + latency: 1.0 # 1*p{23}67 + port_pressure: [[1, '267']] +- name: bic + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.1666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: bics + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.33333333 + latency: 1.0 # 1*p{23}67 + port_pressure: [[1, '267']] +- name: [cls, clz] + operands: + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: [cls, clz] + operands: + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: cmp + operands: + - class: register + prefix: '*' + - class: immediate + imd: int + throughput: 0.33333333 + latency: 1.0 # 1*p{23}67 + port_pressure: [[1, '267']] +- name: cmp + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.3333333 + latency: 1.0 # 1*p{23}67 + port_pressure: [[1, '267']] +- name: [eon, eor] + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.1666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: eor + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: [eon, eor] + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.16666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: eor + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.16666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p12,13,14 + port_pressure: [[1, ['12', '13', '14']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p12,13,14 + port_pressure: [[1, ['12', '13', '14']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['8', '9', '10']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 4.0 # 1*p12,13 + port_pressure: [[1, ['12', '13']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 4.0 # 1*p12,13 + port_pressure: [[1, ['12', '13']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 4.0 # 1*p2367+1*p12,13 + port_pressure: [[1, '2367'], [1, ['12', '13']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 4.0 # 1*p2367+1*p12,13 + port_pressure: [[1, '2367'], [1, ['12', '13']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 4.0 # 1*p2367+1*p12,13 + port_pressure: [[1, '2367'], [1, ['12', '13']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 4.0 # 1*p2367+1*p12,13 + port_pressure: [[1, '2367'], [1, ['12', '13']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p12,13,14 + port_pressure: [[1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p12,13,14 + port_pressure: [[1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 6.0 # 1*p467 + port_pressure: [[1, '467']] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 6.0 # 1*p12,13,14 + port_pressure: [[1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 6.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 6.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 6.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 6.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.6666666 + latency: 6.0 # 2*p12,13,14 + port_pressure: [[2, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.6666666 + latency: 6.0 # 2*p12,13,14 + port_pressure: [[2, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.6666666 + latency: 6.0 # 1*p2367+2*p12,13,14 + port_pressure: [[1, '2367'], [2, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.6666666 + latency: 6.0 # 1*p2367+2*p12,13,14 + port_pressure: [[1, '2367'], [2, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.6666666 + latency: 6.0 # 1*p2367+2*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.6666666 + latency: 6.0 # 1*p2367+2*p12,13,14 + port_pressure: [[1, '2367'], [2, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 6.0 # 1*p12,13,14 + port_pressure: [[1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 6.0 # 1*p12,13,14 + port_pressure: [[1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 6.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 6.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 6.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 6.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p12,13,14 + port_pressure: [[1, ['12', '13', '14']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p12,13,14 + port_pressure: [[1, ['12', '13', '14']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: [ldr, ldur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 4.0 # 1*p12,13 + port_pressure: [[1, ['12', '13']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 4.0 # 1*p12,13 + port_pressure: [[1, ['12', '13']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 4.0 # 1*p2367+1*p12,13 + port_pressure: [[1, '2367'], [1, ['12', '13']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 4.0 # 1*p2367+1*p12,13 + port_pressure: [[1, '2367'], [1, ['12', '13']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 4.0 # 1*p2367+1*p12,13 + port_pressure: [[1, '2367'], [1, ['12', '13']]] +- name: ldp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 4.0 # 1*p2367+1*p12,13 + port_pressure: [[1, '2367'], [1, ['12', '13']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p12,13,14 + port_pressure: [[1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p12,13,14 + port_pressure: [[1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 4.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 4.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 6.0 # 1*p12,13,14 + port_pressure: [[1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 6.0 # 1*p12,13,14 + port_pressure: [[1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 6.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 6.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 6.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 6.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.6666666 + latency: 6.0 # 2*p12,13,14 + port_pressure: [[2, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.6666666 + latency: 6.0 # 1*p2367+2*p12,13,14 + port_pressure: [[1, '2367'], [2, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.6666666 + latency: 6.0 # 1*p2367+2*p12,13,14 + port_pressure: [[1, '2367'], [2, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.6666666 + latency: 6.0 # 1*p2367+2*p12,13,14 + port_pressure: [[1, '2367'], [2, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: q + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.6666666 + latency: 6.0 # 1*p2367+2*p12,13,14 + port_pressure: [[1, '2367'], [2, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 6.0 # 1*p12,13,14 + port_pressure: [[1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.3333333 + latency: 6.0 # 1*p12,13,14 + port_pressure: [[1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 6.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.3333333 + latency: 6.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 6.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: ldp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.3333333 + latency: 6.0 # 1*p2367+1*p12,13,14 + port_pressure: [[1, '2367'], [1, ['12', '13', '14']]] +- name: [lsl, lslv, lsr, lsrv] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.16666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: [lsl, lslv, lsr, lsrv] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: [madd, msub] # NOTE: if the dependency is via the addend (fourth operand), the latency is only 1cy !!! + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 1.0 + latency: 2.0 # 1*,6 NOTE: if the dependency is via the addend (fourth operand), the latency is only 1cy !!! + port_pressure: [[1, '6']] +- name: mneg + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.5 + latency: 2.0 # 1*p67 + port_pressure: [[1, '67']] +- name: [mov, movk, movn, movz] + operands: + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.16666666 + latency: 0 # 1*p89,10,11,12,13 + port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] +- name: [mov, movk, movn, movz] + operands: + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.16666666 + latency: 0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: [mov, movk, movn, movz] + operands: + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.16666666 + latency: 0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: [mov, movk, movn, movz] + operands: + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.16666666 + latency: 0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: mul + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.5 + latency: 2.0 # 1*p67 + port_pressure: [[1, '67']] +- name: mul + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.5 + latency: 2.0 # 1*p67 + port_pressure: [[1, '67']] +- name: mvn + operands: + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: [neg, ngc] + operands: + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.1666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: [neg, ngc] + operands: + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.1666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: [negs, ngcs] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.33333333 + latency: 1.0 # 1*p{23}67 + port_pressure: [[1, '267']] +- name: nop + operands: [] + throughput: 0.0 + latency: 0 # 0*p + port_pressure: [] +- name: [orn, orr] + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.1666666 + latency: 1.0 # 1*234567 + port_pressure: [[1, '234567']] +- name: [orn, orr] + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: [orn, orr] + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.1666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: [orn, orr] + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: [rbit, rev, rev16, rev32] + operands: + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.1666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: [rbit, rev, rev16, rev32] + operands: + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.1666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: ret + operands: [] + throughput: 0.0 + latency: ~ + port_pressure: [] +- name: ret + operands: + - class: immediate + imd: int + throughput: 0.0 + latency: ~ + port_pressure: [] +- name: ret + operands: + - class: identifier + throughput: 0.0 + latency: ~ + port_pressure: [] +- name: ror + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: [ror, rorv] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.1666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: [sbc, sbcs] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.33333333 + latency: 1.0 # 1*p{23}67 + port_pressure: [[1, '267']] +- name: [sbfiz, sbfx] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + - class: immediate + imd: int + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: sbfm + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + - class: immediate + imd: int + throughput: 0.1666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: [scvtf, ucvtf] + operands: + - class: register + prefix: s + - class: register + prefix: w + throughput: 1.0 + latency: 3.0 # 1*p6 + port_pressure: [[1, '6']] +- name: [scvtf, ucvtf] + operands: + - class: register + prefix: d + - class: register + prefix: x + throughput: 1.0 + latency: 3.0 # 1*p6 + port_pressure: [[1, '6']] +- name: [scvtf, ucvtf] + operands: + - class: register + prefix: d + - class: register + prefix: x + - class: immediate + imd: int + throughput: 1.0 + latency: 3.0 # 1*p6 + port_pressure: [[1, '6']] +- name: [scvtf, ucvtf] + operands: + - class: register + prefix: s + - class: register + prefix: w + - class: immediate + imd: int + throughput: 1.0 + latency: 3.0 # 1*p6 + port_pressure: [[1, '6']] +- name: sdiv + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 5.0 + latency: 5.0 # 2*p67DV + port_pressure: [[1, '67'], [10, ['6DV', '7DV']]] +- name: sdiv + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 5.0 +- name: [smaddl, smsubl, umaddl, umsubl] + operands: + - class: register + prefix: x + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: x + throughput: 1.0 + latency: 2.0 # 1*p6 + port_pressure: [[1, '6']] +- name: [smnegl, umnegl] + operands: + - class: register + prefix: x + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.5 + latency: 2.0 # 1*p67 + port_pressure: [[1, '67']] +- name: [smulh, umulh] + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.5 + latency: 3.0 # 1*p67 + port_pressure: [[1, '67']] +- name: [smull, umull] + operands: + - class: register + prefix: x + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.5 + latency: 2.0 # 1*p67 + port_pressure: [[1, '67']] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*12,13+1*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+1*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1+2367+1*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1+2367+1*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1+2367+1*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1+2367+1*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+1*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+1*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+1*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+1*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+1*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 1.0 + latency: 0.0 # 1*p12,13+2*p15,16 + port_pressure: [[1, ['12','13'], [2, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 1.0 + latency: 0.0 # 1*p12,13+2*p15,16 + port_pressure: [[1, ['12','13'], [2, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 1.0 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 1.0 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 1.0 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 1.0 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+2*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+2*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: ~ + scale: ~ + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+2*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+2*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: [str, stur] + operands: + - class: register + prefix: "*" + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+2*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+2*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+2*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+2*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+2*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+2*p15,16 + port_pressure: [[1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 1.0 + latency: 0.0 # 1*p12,13+2*p15,16 + port_pressure: [[1, ['12','13'], [2, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 1.0 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: q + - class: register + prefix: q + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+2*p15,16 + port_pressure: [[1, ['12','13'], [2, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: false + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p12,13+2*p15,16 + port_pressure: [[1, ['12','13'], [2, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: true + pre-indexed: false + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: identifier + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] +- name: stp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + post-indexed: false + pre-indexed: true + throughput: 0.5 + latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 + port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] +- name: sub + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: sub + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: sub + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.1666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: sub + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.1666666 + latency: 1.0 # 1*p234567 + port_pressure: [[1, '234567']] +- name: subs + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: immediate + imd: int + throughput: 0.33333333 + latency: 1.0 # 1*p{23}67 + port_pressure: [[1, '267']] +- name: subs + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.33333333 + latency: 1.0 # 1*p{23}67 + port_pressure: [[1, '267']] +- name: subs + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.33333333 + latency: 1.0 # 1*p{23}67 + port_pressure: [[1, '267']] +- name: subs + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.33333333 + latency: 1.0 # 1*p{23}67 + port_pressure: [[1, '267']] +- name: sxtb + operands: + - class: register + prefix: x + - class: register + prefix: w + throughput: 0.5 + latency: 1.0 # 1*p67 + port_pressure: [[1, '67']] +- name: [ubfiz, ubfm, ubfx] + operands: + - class: register + prefix: "*" + - class: register + prefix: "*" + - class: immediate + imd: int + - class: immediate + imd: int + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: udiv + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 5.0 + latency: 5.0 # 2*p67DV + port_pressure: [[1, '67'], [10, ['6DV', '7DV']]] +- name: [uxtb, uxth] + operands: + - class: register + prefix: w + - class: register + prefix: w + throughput: 0.25 + latency: 1.0 # 1*p2367 + port_pressure: [[1, '2367']] +- name: fabs + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.25 + latency: 1.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: fabs + operands: + - class: register + prefix: '*' + shape: '*' + width: '*' + - class: immediate + imd: int + throughput: 0.25 + latency: 2.0 # 1*p8,9,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: fadd + operands: + - class: register + prefix: '*' + shape: '*' + width: '*' + - class: register + prefix: '*' + shape: '*' + width: '*' + - class: register + prefix: '*' + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p8,9,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: [fcmp, fcmpe] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 1.0 + latency: 1.0 # 1*p3 + port_pressure: [[1, '3']] +- name: [fccmp, fccmpe] # LT assumed from fcmp + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: immediate + imd: int + - class: condition + ccode: "*" + throughput: 1.0 + latency: 1.0 # 1*p8 + port_pressure: [[1, '8']] +- name: fcvt + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.5 + latency: 3.0 # 1*p810 + port_pressure: [[1, ['8', '10']]] +- name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] + operands: + - class: register + prefix: h + - class: register + prefix: h + throughput: 0.5 + latency: 3.0 # 1*p89 + port_pressure: [[1, '89']] +- name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] + operands: + - class: register + prefix: s + - class: register + prefix: s + throughput: 0.5 + latency: 3.0 # 1*p89 + port_pressure: [[1, '89']] +- name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] + operands: + - class: register + prefix: d + - class: register + prefix: d + throughput: 0.5 + latency: 3.0 # 1*p89 + port_pressure: [[1, '89']] +- name: [fcvtzs, fcvtzu] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: immediate + imd: int + throughput: 0.5 + latency: 3.0 # 1*p89 + port_pressure: [[1, '89']] +- name: fdiv + operands: + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + throughput: 5.0 + latency: 12.0 # 1*p67 + port_pressure: [[1, ['8', '10']], [5, ['8DV', '10DV']]] +- name: fdiv + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + throughput: 5.0 + latency: 12.0 # 1*p + port_pressure: [[1, ['8', '10']], [5, ['8DV', '10DV']]] +- name: fdiv + operands: + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + throughput: 1.0 + latency: 7.0 # 1*p8,10 + port_pressure: [[1, ['8', '10']], [6, ['8DV', '10DV']]] +- name: fdiv + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + throughput: 1.0 + latency: 7.0 # 1*p8,10 + port_pressure: [[1, ['8', '10']], [3, ['8DV', '10DV']]] +- name: [fmadd, fnmadd] + operands: + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + - class: register + prefix: s + throughput: 0.5 + latency: 4.0 # 1*p8,10 + port_pressure: [[1, ['8', '10']]] +- name: [fmadd, fnmadd] + operands: + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + - class: register + prefix: d + throughput: 0.25 + latency: 4.0 # 1*p8,9,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: [fmax, fmaxnm, fmin, fminnm] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.25 + latency: 2.0 # 1*p8,9,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: fmov + operands: + - class: register + prefix: '*' + - class: immediate + imd: '*' + latency: 2.0 # 1*p8,9,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: fmov + operands: + - class: register + prefix: x + - class: register + prefix: d + latency: 2.0 # 1*p6 + port_pressure: [[1, '6']] + throughput: 1.0 +- name: fmov + operands: + - class: register + prefix: w + - class: register + prefix: s + latency: 1.5 # 1*p6 + port_pressure: [[1, '6']] + throughput: 1.0 +- name: fmov + operands: + - class: register + prefix: d + - class: register + prefix: x + latency: 2.0 # 1*p6 + port_pressure: [[1, '6']] + throughput: 1.0 +- name: fmov + operands: + - class: register + prefix: s + - class: register + prefix: w + latency: 1.5 # 1*p6 + port_pressure: [[1, '6']] + throughput: 1.0 +- name: fmov + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] + throughput: 0.25 +- name: [fmsub, fnmsub] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + latency: 4.0 # 1*p89,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] + throughput: 0.25 +- name: [fmul, fnmul] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.25 + latency: 3.0 # 1*p89,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: fneg + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: [frinta, frinti, frintm, frintn, frintp, frintx, frintz] + operands: + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 0.5 + latency: 3.0 # 1*p8,10 + port_pressure: [[1, ['8', '10']]] +- name: fsqrt + operands: + - class: register + prefix: s + - class: register + prefix: s + throughput: 0.75 + latency: 7.0 # 1*p8,10 + port_pressure: [[1, ['8', '10']], [3, ['8DV', '10DV']]] +- name: fsqrt + operands: + - class: register + prefix: d + - class: register + prefix: d + throughput: 2 + latency: 7.0 # 1*p8,10 + port_pressure: [[1, ['8', '10']], [5, ['8DV', '10DV']]] +- name: fsub + operands: + - class: register + prefix: '*' + shape: '*' + width: '*' + - class: register + prefix: '*' + shape: '*' + width: '*' + - class: register + prefix: '*' + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: abs + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: add + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: addp + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: and + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: bic + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: bic + operands: + - class: register + prefix: v + shape: s + width: '*' + - class: immediate + imd: int + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [bif, bit, bsl] + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.5 + latency: 2.0 # 1*p8,10 + port_pressure: [[1, ['8','10']]] +- name: [cls, clz] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [cmeq, cmge, cmgt, cmhi, cmhs, cmle, cmlt, cmtst] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [cmeq, cmge, cmgt, cmhi, cmhs, cmle, cmlt, cmtst] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: immediate + imd: int + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: cnt + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: eor + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: dup + operands: + - class: register + prefix: d + - class: register + prefix: v + shape: d + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: dup + operands: + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: dup + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: x + throughput: 1.0 + latency: 3.0 # 1*p7 + port_pressure: [[1, '7']] +- name: ext + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + - class: immediate + imd: int + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: fabd + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: fabs + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [facge, facgt] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: faddp + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 3.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: fcadd + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: immediate + imd: int + throughput: 0.25 + latency: 3.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [fcmeq, fcmge, fcmgt, fcmle, fcmlt] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: immediate + imd: int + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [fcmeq, fcmge, fcmgt, fcmle, fcmlt] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: fcmla + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: immediate + imd: int + throughput: 0.5 + latency: 5.0 # 1*p8,10 + port_pressure: [[1, ['8','10']]] +- name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] + operands: + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + throughput: 1.0 + latency: 4.0 # 1*p8 + port_pressure: [[1, '8']] +- name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] + operands: + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + throughput: 0.5 + latency: 3.0 # 1*p89 + port_pressure: [[1, '89']] +- name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] + operands: + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + - class: immediate + imd: int + throughput: 0.5 + latency: 3.0 # 1*p89 + port_pressure: [[1, '89']] +- name: [fmax, fmaxnm, fmaxnmp, fmaxp] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [fmin, fminnm, fminnmp, fminp] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [fmla, fmls] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 4.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [fmul, fmulx] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 3.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: fneg + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: frecpe + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.5 + latency: 3.0 # 1*p8,10 + port_pressure: [[1, ['8','10']]] +- name: frecps + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 4.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [frinta, frinti, frintm, frintn, frintp, frintx, frintz] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 3.0 # 1*p8,10 + port_pressure: [[1, ['8','10']]] +- name: fsqrt + operands: + - class: register + prefix: v + shape: d + width: '*' + - class: register + prefix: v + shape: d + width: '*' + throughput: 7.0 + latency: 7.0 # 1*p810+14*p8DV10DV + port_pressure: [[1, ['8','10']], [14, ['8DV', '10DV']]] +- name: fsqrt + operands: + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + throughput: 3.5 + latency: 7.0 # 1*p810+7*p8DV10DV + port_pressure: [[1, ['8','10']], [7, ['8DV', '10DV']]] +- name: frsqrte + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 1.0 + latency: 4.0 # 1*p810+2*p8DV10DV + port_pressure: [[1, ['8','10']], [2, ['8DV', '10DV']]] +- name: frsqrts + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 4.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [mla, mls] + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 4.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: mov + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 0.0 + port_pressure: [[1, ['8','9','10','11']]] +- name: mul + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.5 + latency: 4.0 # 1*p8,10 + port_pressure: [[1, ['8','10']]] +- name: mvn + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: neg + operands: + - class: register + prefix: v + shape: '*' + width: '*' + - class: register + prefix: v + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: not + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [orn, orr] + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: pmul + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.5 + latency: 2.0 # 1*p10,11 + port_pressure: [[1, ['10','11']]] +- name: rbit + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [rev16, rev32, rev64] + operands: + - class: register + prefix: v + shape: b + width: '*' + - class: register + prefix: v + shape: b + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: rev64 + operands: + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: saba + operands: + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + - class: register + prefix: v + shape: s + width: '*' + throughput: 0.5 + latency: 4.0 # 1*p9,11 + port_pressure: [[1, ['9','11']]] +- name: fadda + operands: + - class: register + prefix: s + - class: register + prefix: p + - class: register + prefix: s + - class: register + prefix: z + shape: s + width: '*' + throughput: 5.0 + latency: 7.0 # 5*p9 + port_pressure: [[5, '9']] +- name: fadda + operands: + - class: register + prefix: d + - class: register + prefix: p + - class: register + prefix: d + - class: register + prefix: z + shape: d + width: '*' + throughput: 0.5 + latency: 4.0 # 2*p8,9,10,11 + port_pressure: [[2, ['8','9','10','11']]] +- name: faddv + operands: + - class: register + prefix: s + - class: register + prefix: p + - class: register + prefix: z + shape: s + width: '*' + throughput: 0.75 + latency: 9.0 # 3*p89,10,11 + port_pressure: [[3, ['8','9','10','11']]] +- name: faddv + operands: + - class: register + prefix: d + - class: register + prefix: p + - class: register + prefix: z + shape: d + width: '*' + throughput: 0.5 + latency: 6.0 # 1*p89,10,11 + port_pressure: [[2, ['8','9','10','11']]] +- name: fcmla + operands: + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: p + predication: '*' + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: z + shape: d + width: '*' + - class: immediate + imd: int + throughput: 0.25 + latency: 5.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: fcadd + operands: + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: p + predication: '*' + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: z + shape: d + width: '*' + - class: immediate + imd: int + throughput: 0.25 + latency: 3.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [fmad, fmla, mla] + operands: + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: z + shape: d + width: '*' + throughput: 0.25 + latency: 4.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [fmad, fmla, mla, fmsb, fmls, mls] + operands: + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: p + predication: m + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: z + shape: d + width: '*' + throughput: 0.25 + latency: 4.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [fmad, fmla, fmsb, fmls] + operands: + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: p + predication: m + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: z + shape: d + width: '*' + - class: immediate + imd: 'double' + throughput: 0.5 + latency: 4.0 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: fmov + operands: + - class: register + prefix: z + shape: '*' + - class: immediate + imd: double + throughput: 0.25 + latency: 2 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [fmsb, fmls] + operands: + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: p + predication: m + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: z + shape: d + width: '*' + throughput: 0.25 + latency: 4 # 1*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: fmul + operands: + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: z + shape: d + width: '*' + throughput: 0.5 + latency: 3 # 1*p89,10,11 + port_pressure: [[2, ['8','9','10','11']]] +- name: fneg + operands: + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: p + - class: register + prefix: z + shape: d + width: '*' + throughput: 0.5 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[2, ['8','9','10','11']]] +- name: fsub + operands: + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: p + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: z + shape: d + width: '*' + throughput: 0.5 + latency: 2.0 # 1*p89,10,11 + port_pressure: [[2, ['8','9','10','11']]] +- name: [ld1d, ld1sw, ld1sh, ld1sb] + operands: + - class: register + prefix: z + shape: d + - class: register + prefix: p + predication: '*' + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 6.0 # 1*p12,13,14 + port_pressure: [[3, ['12', '13', '14']]] +- name: [ld1d, ld1sw, ld1sh, ld1sb] + operands: + - class: register + prefix: z + shape: d + - class: register + prefix: p + predication: '*' + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 6.0 # 1*p12,13,14 + port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] +- name: [ld1d, ld1sw, ld1sh, ld1sb] + operands: + - class: register + prefix: z + shape: d + - class: register + prefix: p + predication: '*' + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 6.0 # 1*p12,13,14 + port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] +- name: [ld1d, ld1w, ld1h, ld1b] # gather + operands: + - class: register + prefix: z + shape: d + - class: register + prefix: p + predication: '*' + - class: memory + base: x + offset: '*' + index: z + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 9.0 # 1*p12,13,14 + port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] +- name: [ld1d, ld1w, ld1h, ld1b] # gather + operands: + - class: register + prefix: z + shape: d + - class: register + prefix: p + predication: '*' + - class: memory + base: x + offset: '*' + index: z + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 9.0 # 1*p12,13,14 + port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] +- name: [ld1d, ld1w, ld1h, ld1b] # gather + operands: + - class: register + prefix: z + shape: d + - class: register + prefix: p + predication: '*' + - class: memory + base: x + offset: '*' + index: z + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 9.0 # 1*p12,13,14 + port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] +- name: [ld2d, ld2w, ld2h, ld2b] + operands: + - class: register + prefix: 'z' + shape: 'd' + - class: register + prefix: 'z' + shape: 'd' + - class: register + prefix: p + predication: '*' + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 9.0 # 1*p12,13,14 + port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] +- name: [ld2d, ld2w, ld2h, ld2b] + operands: + - class: register + prefix: 'z' + shape: 'd' + - class: register + prefix: 'z' + shape: 'd' + - class: register + prefix: p + predication: '*' + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.0 + latency: 9.0 # 1*p12,13,14 + port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] +- name: [ld2d, ld2w, ld2h, ld2b] + operands: + - class: register + prefix: 'z' + shape: 'd' + - class: register + prefix: 'z' + shape: 'd' + - class: register + prefix: p + predication: '*' + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.0 + latency: 9.0 # 1*p12,13,14 + port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] +- name: [ld3d, ld3w, ld3h, ld3b] + operands: + - class: register + prefix: 'z' + shape: 'd' + - class: register + prefix: 'z' + shape: 'd' + - class: register + prefix: p + predication: '*' + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.3333333 + latency: 10.0 # 1*p12,13,14 + port_pressure: [[1, ['8','9','10','11']], [4, ['12', '13', '14']]] +- name: [ld3d, ld3w, ld3h, ld3b] + operands: + - class: register + prefix: 'z' + shape: 'd' + - class: register + prefix: 'z' + shape: 'd' + - class: register + prefix: p + predication: '*' + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 1.3333333 + latency: 10.0 # 1*p12,13,14 + port_pressure: [[1, ['8','9','10','11']], [4, ['12', '13', '14']]] +- name: [ld3d, ld3w, ld3h, ld3b] + operands: + - class: register + prefix: 'z' + shape: 'd' + - class: register + prefix: 'z' + shape: 'd' + - class: register + prefix: p + predication: '*' + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 1.3333333 + latency: 10.0 # 1*p12,13,14 + port_pressure: [[1, ['8','9','10','11']], [4, ['12', '13', '14']]] +- name: [mov, movprfx] + operands: + - class: register + prefix: z + shape: '*' + - class: register + prefix: z + shape: '*' + throughput: 0.5 + latency: 2.0 # 2*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: [mov, sel, movprfx] + operands: + - class: register + prefix: z + shape: '*' + - class: register + prefix: p + predication: '*' + - class: register + prefix: z + shape: '*' + throughput: 0.5 + latency: 2.0 # 2*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: prfm + operands: + - class: prfop + type: '*' + target: '*' + policy: '*' + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.33333333 + latency: 5 + port_pressure: [[1, '2367'], [1, ['12','13','14']]] +- name: prfd + operands: + - class: prfop + type: '*' + target: '*' + policy: '*' + - class: register + prefix: p + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.333333333 + latency: 5 + port_pressure: [[1, '2367'], [1, ['12','13','14']]] +- name: prfd + operands: + - class: immediate + imd: int + - class: register + prefix: p + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.333333333 + latency: 5 + port_pressure: [[1, '2367'], [1, ['12','13','14']]] +- name: [ptrue, pfalse] + operands: + - class: register + prefix: p + throughput: 0.5 + latency: 2 + port_pressure: [[1, '67']] +- name: [ptrue, pfalse] + operands: + - class: register + prefix: p + shape: '*' + - class: identifier + throughput: 0.5 + latency: 2 + port_pressure: [[1, '67']] +- name: [st1d, std1w, st1h, st1b] + operands: + - class: register + prefix: z + shape: d + - class: register + prefix: p + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 1.0 + latency: 0 # 2*p89+2*p12,13 + port_pressure: [[2, '89'], [1, ['12','13']]] +- name: [st2d, st2w, st2b, st2h] + operands: + - class: register + prefix: 'z' + shape: 'd' + - class: register + prefix: 'z' + shape: 'd' + - class: register + prefix: p + predication: '*' + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 2.0 + latency: 0 # 2*p89+2*p12,13 + port_pressure: [[2, '89'], [1, ['12','13']]] +- name: [st3d, st3w, st3b, st3h] + operands: + - class: register + prefix: 'z' + shape: 'd' + - class: register + prefix: 'z' + shape: 'd' + - class: register + prefix: p + predication: '*' + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 2.0 + latency: 0 # 2*p89+2*p12,13 + port_pressure: [[4, '89'], [1, ['12','13']]] +- name: tbl + operands: + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: z + shape: d + width: '*' + throughput: 0.5 + latency: 2.0 # 1*p89 + port_pressure: [[1, '89']] +- name: [whilege, whilegt, whilehi, whilehs, whilele, whilelo, whilels, whilelt, whilerw, whilewr] + operands: + - class: register + prefix: p + shape: d + - class: register + prefix: '*' + - class: register + prefix: '*' + throughput: 1.0 + latency: 3.0 # 1*p67 + port_pressure: [[1, '67']] +- name: [zip1, zip2] + operands: + - class: register + prefix: z + shape: '*' + - class: register + prefix: z + shape: '*' + - class: register + prefix: z + shape: '*' + throughput: 0.25 + latency: 2.0 # 2*p89,10,11 + port_pressure: [[1, ['8','9','10','11']]] +- name: scvtf + operands: + - class: register + prefix: z + shape: s + - class: register + prefix: p + - class: register + prefix: z + shape: s + throughput: 1.0 + latency: 4.0 + port_pressure: [[2, ['8','10']]] +- name: scvtf + operands: + - class: register + prefix: z + shape: h + - class: register + prefix: p + - class: register + prefix: z + shape: h + throughput: 2.0 + latency: 6.0 + port_pressure: [[4, ['8','10']]] +- name: scvtf + operands: + - class: register + prefix: z + shape: d + - class: register + prefix: p + - class: register + prefix: z + shape: d + throughput: 0.5 + latency: 3.0 + port_pressure: [[1, ['8','10']]] diff --git a/osaca/osaca.py b/osaca/osaca.py index 60f7b58..59e342e 100755 --- a/osaca/osaca.py +++ b/osaca/osaca.py @@ -39,6 +39,7 @@ SUPPORTED_ARCHS = [ "TSV110", "A72", "M1", + "V2", ] DEFAULT_ARCHS = { "aarch64": "A64FX", @@ -102,7 +103,8 @@ def create_parser(parser=None): "--arch", type=str, help="Define architecture (SNB, IVB, HSW, BDW, SKX, CSX, ICL, ICX, ZEN1, ZEN2, ZEN3, TX2, N1, " - "A64FX, TSV110, A72, M1). If no architecture is given, OSACA assumes a default uarch for x86/AArch64.", + "A64FX, TSV110, A72, M1, V2). If no architecture is given, OSACA assumes a default uarch for " + "x86/AArch64.", ) parser.add_argument( "--fixed", diff --git a/osaca/semantics/hw_model.py b/osaca/semantics/hw_model.py index 19b0230..cc19579 100755 --- a/osaca/semantics/hw_model.py +++ b/osaca/semantics/hw_model.py @@ -282,6 +282,7 @@ class MachineModel(object): "tx2": "aarch64", "n1": "aarch64", "m1": "aarch64", + "v2": "aarch64", "zen1": "x86", "zen+": "x86", "zen2": "x86", From 764b22cebe96ddb3d6bbfba8fa81afbcd38b11f7 Mon Sep 17 00:00:00 2001 From: JanLJL Date: Wed, 6 Mar 2024 00:52:06 +0100 Subject: [PATCH 2/7] initial support for SPR --- README.rst | 30 +- osaca/data/generate_mov_entries.py | 471 ++- osaca/data/spr.yml | 5464 ++++++++++++++++++++++++++++ osaca/osaca.py | 5 +- osaca/semantics/hw_model.py | 1 + 5 files changed, 5952 insertions(+), 19 deletions(-) create mode 100644 osaca/data/spr.yml diff --git a/README.rst b/README.rst index 06408b6..bb67b57 100644 --- a/README.rst +++ b/README.rst @@ -100,7 +100,7 @@ The usage of OSACA can be listed as: shows the program’s version number. --arch ARCH needs to be replaced with the target architecture abbreviation. - Possible options are ``SNB``, ``IVB``, ``HSW``, ``BDW``, ``SKX``, ``CSX``, ``ICL`` (Client), ``ICX`` (Server) for the latest Intel micro architectures starting from Intel Sandy Bridge and ``ZEN1``, ``ZEN2``, and ``ZEN3`` for AMD Zen architectures. + Possible options are ``SNB``, ``IVB``, ``HSW``, ``BDW``, ``SKX``, ``CSX``, ``ICL`` (Client), ``ICX`` (Server), ``SPR`` for the latest Intel micro architectures starting from Intel Sandy Bridge and ``ZEN1``, ``ZEN2``, and ``ZEN3`` for AMD Zen architectures. Furthermore, ``TX2`` for Marvell`s ARM-based ThunderX2 , ``N1`` for ARM's Neoverse, ``A72`` for ARM Cortex-A72, ``TSV110`` for the HiSilicon TaiShan v110, ``A64FX`` for Fujitsu's HPC ARM architecture, ``M1`` for the Apple M1-Firestorm performance core, and ``V2`` for the Neoverse V2 (used in NVIDIA's Grace CPU) are available. If no micro-architecture is given, OSACA assumes a default architecture for x86/AArch64. --fixed @@ -150,21 +150,23 @@ Supported microarchitectures | | | Ivy Bridge | ``IVB`` | | | +----------------+------------+ | | | Haswell | ``HSW`` | -| | Intel +----------------+------------+ +| | +----------------+------------+ | | | Broadwell | ``BDW`` | -| +----------------+------------+ -| | Skylake-X | ``SKX`` | -| +----------------+------------+ -| | Cascadelake-X | ``CSX`` | -| +----------------+------------+ -| | Icelake client | ``ICL`` | -| +----------------+------------+ -| | Icelake server | ``ICX`` | +| | +----------------+------------+ +| | | Skylake-X | ``SKX`` | +| | Intel +----------------+------------+ +| | | Cascadelake-X | ``CSX`` | +| | +----------------+------------+ +| | | Icelake client | ``ICL`` | +| | +----------------+------------+ +| | | Icelake server | ``ICX`` | +| | +----------------+------------+ +| | | Sapphire Rapids| ``SPR`` | +----------+----------------+------------+ | | | Naples / Zen 1 | ``ZEN1`` | -| +----------------+------------+ +| | +----------------+------------+ | | AMD | Rome / Zen 2 | ``ZEN2`` | -| +----------------+------------+ +| | +----------------+------------+ | | | Milan / Zen 3 | ``ZEN3`` | +----------+----------------+------------+ @@ -174,9 +176,9 @@ Supported microarchitectures | Designer | Model/microarch | OSACA flag | +===========+===================+=============+ | | | Cortex-A72 | ``A72`` | -| +-------------------+-------------+ +| | +-------------------+-------------+ | | ARM | Neoverse N1 | ``N1`` | -| +-------------------+-------------+ +| | +-------------------+-------------+ | | | Neoverse V2 | ``V2`` | +-----------+-------------------+-------------+ | Marvell | ThunderX2 | ``TX2`` | diff --git a/osaca/data/generate_mov_entries.py b/osaca/data/generate_mov_entries.py index cdaaf9d..7ffb9cf 100755 --- a/osaca/data/generate_mov_entries.py +++ b/osaca/data/generate_mov_entries.py @@ -9,7 +9,7 @@ class MOVEntryBuilder: port_occupancy = defaultdict(Fraction) for uops, ports in port_pressure: for p in ports: - port_occupancy[p] += Fraction(uops, len(ports)) + port_occupancy[p] += Fraction(int(uops*100), len(ports)*100) return float(max(list(port_occupancy.values()) + [0])) @staticmethod @@ -71,7 +71,7 @@ class MOVEntryBuilder: ports = ports.split(",") if len(ports) == 1: ports = ports[0] - port_pressure.append([int(cycles), ports]) + port_pressure.append([float(cycles), ports]) return port_pressure def process_item(self, instruction_form, resources): @@ -115,6 +115,43 @@ class MOVEntryBuilderIntelNoPort7AGU(MOVEntryBuilder): ) +class MOVEntryBuilderIntelPort11(MOVEntryBuilder): + # for SPR + def build_description(self, instruction_name, operand_types, port_pressure=[], latency=0): + load, store, vec = self.classify(operand_types) + + if load: + if 'zmm' in operand_types: + port_pressure += [[1.5, ["2","3", "10"]]] + else: + port_pressure += [[1, ["2","3","10"]]] + latency += 5 + comment = "with load" + return MOVEntryBuilder.build_description( + self, instruction_name, operand_types, port_pressure, latency, comment + ) + if store: + if 'zmm' in operand_types: + port_pressure += [[2, "78"], [2, "49"]] + else: + port_pressure += [[1, "78"], [1, "49"]] + operands = ["mem" if o == "mem" else o for o in operand_types] + latency += 0 + return MOVEntryBuilder.build_description( + self, + instruction_name, + operands, + port_pressure, + latency, + "with store", + ) + + # Register only: + return MOVEntryBuilder.build_description( + self, instruction_name, operand_types, port_pressure, latency + ) + + class MOVEntryBuilderIntelPort9(MOVEntryBuilder): # for ICX def build_description(self, instruction_name, operand_types, port_pressure=[], latency=0): @@ -946,6 +983,433 @@ icx_mov_instructions = [ # TODO with masking! ] +p11 = MOVEntryBuilderIntelPort11() + +spr_mov_instructions = [ + # https://www.felixcloutier.com/x86/mov + ("mov gpr gpr", ("1*p0,1,5,6,10", 1)), + ("mov gpr mem", ("", 0)), + ("mov mem gpr", ("", 0)), + ("mov imd gpr", ("1*p0,1,5,6,10", 1)), + ("mov imd mem", ("", 0)), + ("movabs imd gpr", ("1*p0,1,5,6,10", 1)), # AT&T version + # https://www.felixcloutier.com/x86/movapd + ("movapd xmm xmm", ("1*p0,1,5,6,10", 1)), + ("movapd xmm mem", ("", 0)), + ("movapd mem xmm", ("", 0)), + ("vmovapd xmm xmm", ("1*p0,1,5,6,10", 1)), + ("vmovapd xmm mem", ("", 0)), + ("vmovapd mem xmm", ("", 0)), + ("vmovapd ymm ymm", ("1*p0,1,5,6,10", 1)), + ("vmovapd ymm mem", ("", 0)), + ("vmovapd mem ymm", ("", 0)), + ("vmovapd zmm zmm", ("1*p0,1,5,6,10", 1)), + ("vmovapd zmm mem", ("", 0)), + ("vmovapd mem zmm", ("", 0)), + # https://www.felixcloutier.com/x86/movaps + ("movaps xmm xmm", ("1*p0,1,5,6,10", 1)), + ("movaps xmm mem", ("", 0)), + ("movaps mem xmm", ("", 0)), + ("vmovaps xmm xmm", ("1*p0,1,5,6,10", 1)), + ("vmovaps xmm mem", ("", 0)), + ("vmovaps mem xmm", ("", 0)), + ("vmovaps ymm ymm", ("1*p0,1,5,6,10", 1)), + ("vmovaps ymm mem", ("", 0)), + ("vmovaps mem ymm", ("", 0)), + ("vmovaps zmm zmm", ("1*p0,1,5,6,10", 1)), + ("vmovaps zmm mem", ("", 0)), + ("vmovaps mem zmm", ("", 0)), + ## https://www.felixcloutier.com/x86/movd:movq + #("movd gpr mm", ("1*p5", 1)), + #("movd mem mm", ("", 0)), + #("movq gpr mm", ("1*p5", 1)), + #("movq mem mm", ("", 0)), + #("movd mm gpr", ("1*p0", 1)), + #("movd mm mem", ("", 0)), + #("movq mm gpr", ("1*p0", 1)), + #("movq mm mem", ("", 0)), + #("movd gpr xmm", ("1*p5", 1)), + #("movd mem xmm", ("", 0)), + #("movq gpr xmm", ("1*p5", 1)), + #("movq mem xmm", ("", 0)), + #("movd xmm gpr", ("1*p0", 1)), + #("movd xmm mem", ("", 0)), + #("movq xmm gpr", ("1*p0", 1)), + #("movq xmm mem", ("", 0)), + #("vmovd gpr xmm", ("1*p5", 1)), + #("vmovd mem xmm", ("", 0)), + #("vmovq gpr xmm", ("1*p5", 1)), + #("vmovq mem xmm", ("", 0)), + #("vmovd xmm gpr", ("1*p0", 1)), + #("vmovd xmm mem", ("", 0)), + #("vmovq xmm gpr", ("1*p0", 1)), + #("vmovq xmm mem", ("", 0)), + ## https://www.felixcloutier.com/x86/movddup + #("movddup xmm xmm", ("1*p5", 1)), + #("movddup mem xmm", ("", 0)), + #("vmovddup xmm xmm", ("1*p5", 1)), + #("vmovddup mem xmm", ("", 0)), + #("vmovddup ymm ymm", ("1*p5", 1)), + #("vmovddup mem ymm", ("", 0)), + #("vmovddup zmm zmm", ("1*p5", 1)), + #("vmovddup mem zmm", ("", 0)), + # https://www.felixcloutier.com/x86/movdq2q + #("movdq2q xmm mm", ("1*p015+1*p5", 1)), + # https://www.felixcloutier.com/x86/movdqa:vmovdqa32:vmovdqa64 + ("movdqa xmm xmm", ("1*p0,1,5,6,10", 1)), + ("movdqa mem xmm", ("", 0)), + ("movdqa xmm mem", ("", 0)), + ("vmovdqa xmm xmm", ("1*p0,1,5,6,10", 1)), + ("vmovdqa mem xmm", ("", 0)), + ("vmovdqa xmm mem", ("", 0)), + ("vmovdqa ymm ymm", ("1*p0,1,5,6,10", 1)), + ("vmovdqa mem ymm", ("", 0)), + ("vmovdqa ymm mem", ("", 0)), + ("vmovdqa32 xmm xmm", ("1*p0,1,5,6,10", 1)), + ("vmovdqa32 mem xmm", ("", 0)), + ("vmovdqa32 xmm mem", ("", 0)), + ("vmovdqa32 ymm ymm", ("1*p0,1,5,6,10", 1)), + ("vmovdqa32 mem ymm", ("", 0)), + ("vmovdqa32 ymm mem", ("", 0)), + ("vmovdqa32 zmm zmm", ("1*p0,1,5,6,10", 1)), + ("vmovdqa32 mem zmm", ("", 0)), + ("vmovdqa32 zmm mem", ("", 0)), + ("vmovdqa64 xmm xmm", ("1*p0,1,5,6,10", 1)), + ("vmovdqa64 mem xmm", ("", 0)), + ("vmovdqa64 xmm mem", ("", 0)), + ("vmovdqa64 ymm ymm", ("1*p0,1,5,6,10", 1)), + ("vmovdqa64 mem ymm", ("", 0)), + ("vmovdqa64 ymm mem", ("", 0)), + ("vmovdqa64 zmm zmm", ("1*p0,1,5,6,10", 1)), + ("vmovdqa64 mem zmm", ("", 0)), + ("vmovdqa64 zmm mem", ("", 0)), + # https://www.felixcloutier.com/x86/movdqu:vmovdqu8:vmovdqu16:vmovdqu32:vmovdqu64 + ("movdqu xmm xmm", ("1*p0,1,5,6,10", 1)), + ("movdqu mem xmm", ("", 0)), + ("movdqu xmm mem", ("", 0)), + ("vmovdqu xmm xmm", ("1*p0,1,5,6,10", 1)), + ("vmovdqu mem xmm", ("", 0)), + ("vmovdqu xmm mem", ("", 0)), + ("vmovdqu ymm ymm", ("1*p0,1,5,6,10", 1)), + ("vmovdqu mem ymm", ("", 0)), + ("vmovdqu ymm mem", ("", 0)), + ("vmovdqu8 xmm xmm", ("1*p0,1,5,6,10", 1)), + ("vmovdqu8 mem xmm", ("", 0)), + ("vmovdqu8 xmm mem", ("", 0)), + ("vmovdqu8 ymm ymm", ("1*p0,1,5,6,10", 1)), + ("vmovdqu8 mem ymm", ("", 0)), + ("vmovdqu8 ymm mem", ("", 0)), + ("vmovdqu8 zmm zmm", ("1*p0,1,5,6,10", 1)), + ("vmovdqu8 mem zmm", ("", 0)), + ("vmovdqu8 zmm mem", ("", 0)), + ("vmovdqu16 xmm xmm", ("1*p0,1,5,6,10", 1)), + ("vmovdqu16 mem xmm", ("", 0)), + ("vmovdqu16 xmm mem", ("", 0)), + ("vmovdqu16 ymm ymm", ("1*p0,1,5,6,10", 1)), + ("vmovdqu16 mem ymm", ("", 0)), + ("vmovdqu16 ymm mem", ("", 0)), + ("vmovdqu16 zmm zmm", ("1*p0,1,5,6,10", 1)), + ("vmovdqu16 mem zmm", ("", 0)), + ("vmovdqu16 zmm mem", ("", 0)), + ("vmovdqu32 xmm xmm", ("1*p0,1,5,6,10", 1)), + ("vmovdqu32 mem xmm", ("", 0)), + ("vmovdqu32 xmm mem", ("", 0)), + ("vmovdqu32 ymm ymm", ("1*p0,1,5,6,10", 1)), + ("vmovdqu32 mem ymm", ("", 0)), + ("vmovdqu32 ymm mem", ("", 0)), + ("vmovdqu32 zmm zmm", ("1*p0,1,5,6,10", 1)), + ("vmovdqu32 mem zmm", ("", 0)), + ("vmovdqu32 zmm mem", ("", 0)), + ("vmovdqu64 xmm xmm", ("1*p0,1,5,6,10", 1)), + ("vmovdqu64 mem xmm", ("", 0)), + ("vmovdqu64 xmm mem", ("", 0)), + ("vmovdqu64 ymm ymm", ("1*p0,1,5,6,10", 1)), + ("vmovdqu64 mem ymm", ("", 0)), + ("vmovdqu64 ymm mem", ("", 0)), + ("vmovdqu64 zmm zmm", ("1*p0,1,5,6,10", 1)), + ("vmovdqu64 mem zmm", ("", 0)), + ("vmovdqu64 zmm mem", ("", 0)), + ## https://www.felixcloutier.com/x86/movhlps + #("movhlps xmm xmm", ("1*p5", 1)), + #("vmovhlps xmm xmm xmm", ("1*p5", 1)), + ## https://www.felixcloutier.com/x86/movhpd + #("movhpd mem xmm", ("1*p5", 1)), + #("vmovhpd mem xmm xmm", ("1*p5", 1)), + #("movhpd xmm mem", ("", 0)), + #("vmovhpd mem xmm", ("", 0)), + ## https://www.felixcloutier.com/x86/movhps + #("movhps mem xmm", ("1*p5", 1)), + #("vmovhps mem xmm xmm", ("1*p5", 1)), + #("movhps xmm mem", ("", 0)), + #("vmovhps mem xmm", ("", 0)), + ## https://www.felixcloutier.com/x86/movlhps + #("movlhps xmm xmm", ("1*p5", 1)), + #("vmovlhps xmm xmm xmm", ("1*p5", 1)), + ## https://www.felixcloutier.com/x86/movlpd + #("movlpd mem xmm", ("1*p5", 1)), + #("vmovlpd mem xmm xmm", ("1*p5", 1)), + #("movlpd xmm mem", ("", 0)), + #("vmovlpd mem xmm", ("1*p5", 1)), + ## https://www.felixcloutier.com/x86/movlps + #("movlps mem xmm", ("1*p5", 1)), + #("vmovlps mem xmm xmm", ("1*p5", 1)), + #("movlps xmm mem", ("", 0)), + #("vmovlps mem xmm", ("1*p5", 1)), + ## https://www.felixcloutier.com/x86/movmskpd + #("movmskpd xmm gpr", ("1*p0", 1)), + #("vmovmskpd xmm gpr", ("1*p0", 1)), + #("vmovmskpd ymm gpr", ("1*p0", 1)), + ## https://www.felixcloutier.com/x86/movmskps + #("movmskps xmm gpr", ("1*p0", 1)), + #("vmovmskps xmm gpr", ("1*p0", 1)), + #("vmovmskps ymm gpr", ("1*p0", 1)), + # https://www.felixcloutier.com/x86/movntdq + ("movntdq xmm mem", ("", 0)), # TODO NT-store: what latency to use? + ("vmovntdq xmm mem", ("", 0)), # TODO NT-store: what latency to use? + ("vmovntdq ymm mem", ("", 0)), # TODO NT-store: what latency to use? + ("vmovntdq zmm mem", ("", 0)), # TODO NT-store: what latency to use? + # https://www.felixcloutier.com/x86/movntdqa + ("movntdqa mem xmm", ("", 0)), # TODO NT-store: what latency to use? + ("vmovntdqa mem xmm", ("", 0)), # TODO NT-store: what latency to use? + ("vmovntdqa mem ymm", ("", 0)), # TODO NT-store: what latency to use? + ("vmovntdqa mem zmm", ("", 0)), # TODO NT-store: what latency to use? + # https://www.felixcloutier.com/x86/movnti + ("movnti gpr mem", ("", 0)), # TODO NT-store: what latency to use? + # https://www.felixcloutier.com/x86/movntpd + ("movntpd xmm mem", ("", 0)), # TODO NT-store: what latency to use? + ("vmovntpd xmm mem", ("", 0)), # TODO NT-store: what latency to use? + ("vmovntpd ymm mem", ("", 0)), # TODO NT-store: what latency to use? + ("vmovntpd zmm mem", ("", 0)), # TODO NT-store: what latency to use? + # https://www.felixcloutier.com/x86/movntps + ("movntps xmm mem", ("", 0)), # TODO NT-store: what latency to use? + ("vmovntps xmm mem", ("", 0)), # TODO NT-store: what latency to use? + ("vmovntps ymm mem", ("", 0)), # TODO NT-store: what latency to use? + ("vmovntps zmm mem", ("", 0)), # TODO NT-store: what latency to use? + # https://www.felixcloutier.com/x86/movntq + ("movntq mm mem", ("", 0)), # TODO NT-store: what latency to use? + # https://www.felixcloutier.com/x86/movq + ("movq mm mm", ("", 0)), + ("movq mem mm", ("", 0)), + ("movq mm mem", ("", 0)), + ("movq xmm xmm", ("1*p0,1,5,6,10", 1)), + ("movq mem xmm", ("", 0)), + ("movq xmm mem", ("", 0)), + ("vmovq xmm xmm", ("1*p0,1,5,6,10", 1)), + ("vmovq mem xmm", ("", 0)), + ("vmovq xmm mem", ("", 0)), + # https://www.felixcloutier.com/x86/movs:movsb:movsw:movsd:movsq + # TODO combined load-store is currently not supported + # ('movs mem mem', ()), + # https://www.felixcloutier.com/x86/movsd + ("movsd xmm xmm", ("1*p0,1,5,6,10", 1)), + ("movsd mem xmm", ("", 0)), + ("movsd xmm mem", ("", 0)), + ("vmovsd xmm xmm xmm", ("1*p0,1,5,6,10", 1)), + ("vmovsd mem xmm", ("", 0)), + ("vmovsd xmm mem", ("", 0)), + ## https://www.felixcloutier.com/x86/movshdup + #("movshdup xmm xmm", ("1*p15", 1)), + #("movshdup mem xmm", ("", 0)), + #("vmovshdup xmm xmm", ("1*p15", 1)), + #("vmovshdup mem xmm", ("", 0)), + #("vmovshdup ymm ymm", ("1*p15", 1)), + #("vmovshdup mem ymm", ("", 0)), + #("vmovshdup zmm zmm", ("1*p5", 1)), + #("vmovshdup mem zmm", ("", 0)), + ## https://www.felixcloutier.com/x86/movsldup + #("movsldup xmm xmm", ("1*p15", 1)), + #("movsldup mem xmm", ("", 0)), + #("vmovsldup xmm xmm", ("1*p15", 1)), + #("vmovsldup mem xmm", ("", 0)), + #("vmovsldup ymm ymm", ("1*p15", 1)), + #("vmovsldup mem ymm", ("", 0)), + #("vmovsldup zmm zmm", ("1*p5", 1)), + #("vmovsldup mem zmm", ("", 0)), + # https://www.felixcloutier.com/x86/movss + ("movss xmm xmm", ("1*p0,1,5,6,10", 1)), + ("movss mem xmm", ("", 0)), + ("vmovss xmm xmm xmm", ("1*p0,1,5,6,10", 1)), + ("vmovss mem xmm", ("", 0)), + ("vmovss xmm xmm", ("1*p0,1,5,6,10", 1)), + ("vmovss xmm mem", ("", 0)), + ("movss mem xmm", ("", 0)), + # https://www.felixcloutier.com/x86/movsx:movsxd + ("movsx gpr gpr", ("1*p0,1,5,6,10", 1)), + ("movsx mem gpr", ("", 0)), + ("movsxd gpr gpr", ("", 0)), + ("movsxd mem gpr", ("", 0)), + ("movsb gpr gpr", ("1*p0,1,5,6,10", 1)), # AT&T version + ("movsb mem gpr", ("", 0)), # AT&T version + ("movsw gpr gpr", ("1*p0,1,5,6,10", 1)), # AT&T version + ("movsw mem gpr", ("", 0)), # AT&T version + ("movsl gpr gpr", ("1*p0,1,5,6,10", 1)), # AT&T version + ("movsl mem gpr", ("", 0)), # AT&T version + ("movsq gpr gpr", ("1*p0,1,5,6,10", 1)), # AT&T version + ("movsq mem gpr", ("", 0)), # AT&T version + # https://www.felixcloutier.com/x86/movupd + ("movupd xmm xmm", ("1*p0,1,5,6,10", 1)), + ("movupd mem xmm", ("", 0)), + ("movupd xmm mem", ("", 0)), + ("vmovupd xmm xmm", ("1*p0,1,5,6,10", 1)), + ("vmovupd mem xmm", ("", 0)), + ("vmovupd xmm mem", ("", 0)), + ("vmovupd ymm ymm", ("1*p0,1,5,6,10", 1)), + ("vmovupd mem ymm", ("", 0)), + ("vmovupd ymm mem", ("", 0)), + ("vmovupd zmm zmm", ("1*p0,1,5,6,10", 1)), + ("vmovupd mem zmm", ("", 0)), + ("vmovupd zmm mem", ("", 0)), + # https://www.felixcloutier.com/x86/movups + ("movups xmm xmm", ("1*p0,1,5,6,10", 1)), + ("movups mem xmm", ("", 0)), + ("movups xmm mem", ("", 0)), + ("vmovups xmm xmm", ("1*p0,1,5,6,10", 1)), + ("vmovups mem xmm", ("", 0)), + ("vmovups xmm mem", ("", 0)), + ("vmovups ymm ymm", ("1*p0,1,5,6,10", 1)), + ("vmovups mem ymm", ("", 0)), + ("vmovups ymm mem", ("", 0)), + ("vmovups zmm zmm", ("1*p0,1,5,6,10", 1)), + ("vmovups mem zmm", ("", 0)), + ("vmovups zmm mem", ("", 0)), + ## https://www.felixcloutier.com/x86/movzx + #("movzx gpr gpr", ("1*p0,1,5,6,10", 1)), + #("movzx mem gpr", ("", 0)), + #("movzb gpr gpr", ("1*p0,1,5,6,10", 1)), # AT&T version + #("movzb mem gpr", ("", 0)), # AT&T version + #("movzw gpr gpr", ("1*p0,1,5,6,106", 1)), # AT&T version + #("movzw mem gpr", ("", 0)), # AT&T version + #("movzl gpr gpr", ("1*p0156", 1)), # AT&T version + #("movzl mem gpr", ("", 0)), # AT&T version + #("movzq gpr gpr", ("1*p0156", 1)), # AT&T version + #("movzq mem gpr", ("", 0)), # AT&T version + ## https://www.felixcloutier.com/x86/cmovcc + #("cmova gpr gpr", ("2*p06", 1)), + #("cmova mem gpr", ("", 0)), + #("cmovae gpr gpr", ("1*p06", 1)), + #("cmovae mem gpr", ("", 0)), + #("cmovb gpr gpr", ("2*p06", 1)), + #("cmovb mem gpr", ("", 0)), + #("cmovbe gpr gpr", ("2*p06", 1)), + #("cmovbe mem gpr", ("", 0)), + #("cmovc gpr gpr", ("1*p06", 1)), + #("cmovc mem gpr", ("", 0)), + #("cmove gpr gpr", ("1*p06", 1)), + #("cmove mem gpr", ("", 0)), + #("cmovg gpr gpr", ("1*p06", 1)), + #("cmovg mem gpr", ("", 0)), + #("cmovge gpr gpr", ("1*p06", 1)), + #("cmovge mem gpr", ("", 0)), + #("cmovl gpr gpr", ("1*p06", 1)), + #("cmovl mem gpr", ("", 0)), + #("cmovle gpr gpr", ("1*p06", 1)), + #("cmovle mem gpr", ("", 0)), + #("cmovna gpr gpr", ("2*p06", 1)), + #("cmovna mem gpr", ("", 0)), + #("cmovnae gpr gpr", ("1*p06", 1)), + #("cmovnae mem gpr", ("", 0)), + #("cmovnb gpr gpr", ("1*p06", 1)), + #("cmovnb mem gpr", ("", 0)), + #("cmovnbe gpr gpr", ("2*p06", 1)), + #("cmovnbe mem gpr", ("", 0)), + #("cmovnc gpr gpr", ("1*p06", 1)), + #("cmovnc mem gpr", ("", 0)), + #("cmovne gpr gpr", ("1*p06", 1)), + #("cmovne mem gpr", ("", 0)), + #("cmovng gpr gpr", ("1*p06", 1)), + #("cmovng mem gpr", ("", 0)), + #("cmovnge gpr gpr", ("1*p06", 1)), + #("cmovnge mem gpr", ("", 0)), + #("cmovnl gpr gpr", ("1*p06", 1)), + #("cmovnl mem gpr", ("", 0)), + #("cmovno gpr gpr", ("1*p06", 1)), + #("cmovno mem gpr", ("", 0)), + #("cmovnp gpr gpr", ("1*p06", 1)), + #("cmovnp mem gpr", ("", 0)), + #("cmovns gpr gpr", ("1*p06", 1)), + #("cmovns mem gpr", ("", 0)), + #("cmovnz gpr gpr", ("1*p06", 1)), + #("cmovnz mem gpr", ("", 0)), + #("cmovo gpr gpr", ("1*p06", 1)), + #("cmovo mem gpr", ("", 0)), + #("cmovp gpr gpr", ("1*p06", 1)), + #("cmovp mem gpr", ("", 0)), + #("cmovpe gpr gpr", ("1*p06", 1)), + #("cmovpe mem gpr", ("", 0)), + #("cmovpo gpr gpr", ("1*p06", 1)), + #("cmovpo mem gpr", ("", 0)), + #("cmovs gpr gpr", ("1*p06", 1)), + #("cmovs mem gpr", ("", 0)), + #("cmovz gpr gpr", ("1*p06", 1)), + #("cmovz mem gpr", ("", 0)), + ## https://www.felixcloutier.com/x86/pmovmskb + #("pmovmskb mm gpr", ("1*p0", 1)), + #("pmovmskb xmm gpr", ("1*p0", 1)), + #("vpmovmskb xmm gpr", ("1*p0", 1)), + ## https://www.felixcloutier.com/x86/pmovsx + #("pmovsxbw xmm xmm", ("1*p15", 1)), + #("pmovsxbw mem xmm", ("1*p15", 1)), + #("pmovsxbd xmm xmm", ("1*p15", 1)), + #("pmovsxbd mem xmm", ("1*p15", 1)), + #("pmovsxbq xmm xmm", ("1*p15", 1)), + #("pmovsxbq mem xmm", ("1*p15", 1)), + #("vpmovsxbw xmm xmm", ("1*p15", 1)), + #("vpmovsxbw mem xmm", ("1*p15", 1)), + #("vpmovsxbd xmm xmm", ("1*p15", 1)), + #("vpmovsxbd mem xmm", ("1*p15", 1)), + #("vpmovsxbq xmm xmm", ("1*p15", 1)), + #("vpmovsxbq mem xmm", ("1*p15", 1)), + #("vpmovsxbw xmm ymm", ("1*p5", 1)), + #("vpmovsxbw mem ymm", ("1*p5", 1)), + #("vpmovsxbd xmm ymm", ("1*p5", 1)), + #("vpmovsxbd mem ymm", ("1*p5", 1)), + #("vpmovsxbq xmm ymm", ("1*p5", 1)), + #("vpmovsxbq mem ymm", ("1*p5", 1)), + #("vpmovsxbw ymm zmm", ("1*p5", 3)), + #("vpmovsxbw mem zmm", ("1*p5", 1)), + ## https://www.felixcloutier.com/x86/pmovzx + #("pmovzxbw xmm xmm", ("1*p15", 1)), + #("pmovzxbw mem xmm", ("1*p15", 1)), + #("vpmovzxbw xmm xmm", ("1*p15", 1)), + #("vpmovzxbw mem xmm", ("1*p15", 1)), + #("vpmovzxbw xmm ymm", ("1*p5", 1)), + #("vpmovzxbw mem ymm", ("1*p5", 1)), + #("vpmovzxbw ymm zmm", ("1*p5", 1)), + #("vpmovzxbw mem zmm", ("1*p5", 1)), + ################################################################## + ## https://www.felixcloutier.com/x86/movbe + #("movbe gpr mem", ("1*p15", 6)), + #("movbe mem gpr", ("1*p15", 6)), + ################################################ + # https://www.felixcloutier.com/x86/movapd + # TODO with masking! + # https://www.felixcloutier.com/x86/movaps + # TODO with masking! + # https://www.felixcloutier.com/x86/movddup + # TODO with masking! + # https://www.felixcloutier.com/x86/movdqa:vmovdqa32:vmovdqa64 + # TODO with masking! + # https://www.felixcloutier.com/x86/movdqu:vmovdqu8:vmovdqu16:vmovdqu32:vmovdqu64 + # TODO with masking! + # https://www.felixcloutier.com/x86/movq2dq + #("movq2dq mm xmm", ("1*p0+1*p015", 1)), + # https://www.felixcloutier.com/x86/movsd + # TODO with masking! + # https://www.felixcloutier.com/x86/movshdup + # TODO with masking! + # https://www.felixcloutier.com/x86/movsldup + # TODO with masking! + # https://www.felixcloutier.com/x86/movss + # TODO with masking! + # https://www.felixcloutier.com/x86/movupd + # TODO with masking! + # https://www.felixcloutier.com/x86/movups + # TODO with masking! + # https://www.felixcloutier.com/x86/pmovsx + # TODO with masking! +] + + class MOVEntryBuilderIntelWithPort7AGU(MOVEntryBuilder): # for HSW, BDW, SKX and CSX @@ -1612,6 +2076,7 @@ def get_description(arch, rhs_comment=None): "skx": "\n".join([p7.process_item(*item) for item in skx_mov_instructions]), "csx": "\n".join([p7.process_item(*item) for item in csx_mov_instructions]), "icx": "\n".join([p9.process_item(*item) for item in icx_mov_instructions]), + "spr": "\n".join([p11.process_item(*item) for item in spr_mov_instructions]), "zen3": "\n".join([z3.process_item(*item) for item in zen3_mov_instructions]), } @@ -1634,7 +2099,7 @@ if __name__ == "__main__": import sys if len(sys.argv) != 2: - print("Usage: {} (snb|ivb|hsw|bdw|skx|csx|icx|zen3)".format(sys.argv[0])) + print("Usage: {} (snb|ivb|hsw|bdw|skx|csx|icx|spr|zen3)".format(sys.argv[0])) sys.exit(0) try: diff --git a/osaca/data/spr.yml b/osaca/data/spr.yml new file mode 100644 index 0000000..9b8ff68 --- /dev/null +++ b/osaca/data/spr.yml @@ -0,0 +1,5464 @@ +osaca_version: 0.5.3 +micro_architecture: Sapphire Rapids +arch_code: SPR +isa: x86 +ROB_size: ~ +retired_uOps_per_cycle: ~ +scheduler_size: ~ +hidden_loads: false +load_latency: {gpr: 5.0, mm: 5.0, xmm: 5.0, ymm: 5.0, zmm: 5.0} +load_throughput: +- {dst: zmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '23']]} +- {dst: ymm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['2', '3', '11']]]} +- {dst: xmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['2', '3', '11']]]} +- {dst: gpr, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['2', '3', '11']]]} +load_throughput_default: [[1, ['2', '3', '11']]] +store_throughput: +- {src: zmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '78'], [1, '4'], [1, '9']]} +- {src: ymm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '78'], [1, '49']]} +- {src: xmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '78'], [1, '49']]} +- {src: gpr, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '78'], [1, '49']]} +store_throughput_default: [[1, '78'], [1, '49']] +ports: ['0', 0DV, '1', 1DV, '2', '3', '4', '5', '6', '7', '8', '9', '10', '11'] +port_model_scheme: | + +--------------------------------------------------------------------------------------------------------+ + | scheduler | + +--------------------------------------------------------------------------------------------------------+ + 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | + \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ + +-------+ +-------+ +-----+ +-----+ +-----+ +-------+ +-------+ +------+ +------+ +-----+ +-----+ +-----+ + | ALU | | ALU | | LD | | LD | | ST | | ALU | | ALU | |ST AGU| |ST AGU| | ST | | ALU | | LD | + +-------+ +-------+ +-----+ +-----+ +-----+ +-------+ +-------+ +------+ +------+ +-----+ +-----+ +-----+ + +-------+ +-------+ +-----+ +-----+ +-------+ +-------+ +-----+ +-----+ + | BRANCH| | LEA | | AGU | | AGU | | LEA | | SHIFT | | LEA | | AGU | + +-------+ +-------+ +-----+ +-----+ +-------+ +-------+ +-----+ +-----+ + +-------+ +-------+ +-------+ +-------+ + | LEA | |INT MUL| | MUL Hi| | BRANCH| + +-------+ +-------+ +-------+ +-------+ + +-------+ +-------+ +-------+ +-------+ + | SHIFT | |INT DIV| |AVX ALU| | LEA | + +-------+ +-------+ +-------+ +-------+ + +-------+ +-------+ +-------+ + |AVX ALU| |AVX*ALU| | AVX | + +-------+ +-------+ | SHUF | + +-------+ +-------+ +-------+ + |AVX DIV| |AVX*FMA| +-------+ + +-------+ +-------+ |AVX FMA| + +-------+ +-------+ +-------+ + |AVX FMA| | AVX* | + +-------+ | SHUF | + +--------+ +-------+ + |AVX SHFT| +-------+ + +--------+ | AVX* | + | SHFT | + +-------+ * = no AVX-512 +instruction_forms: +########################################## +# assume all jmp instruction 0 +- name: [jo, jno, js, jns, jp, jpe, jnp, jpo] + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: [jc, jb, jae, jnb, jna, jbe, ja, jnbe] + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: [je, jz, jne, jnz, jl, jnge] + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: [jge, jnl, jle, jng, jg, jnle] + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: jmp + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +########################################## +# assume all cmp's equal for now +# TODO add cmp instructions +- name: [cmp, cmpeqpd, cmpltpd, cmplepd, cmpunordpd, cmpneqpd, cmpnltpd, cmpnlepd, cmpordpd, cmpltps, cmpleps, cmpunordps, cmpneqps, cmpnltps, cmpnleps, cmpordps] + operands: + - class: register + name: '*' + - class: register + name: '*' + latency: 1.0 + port_pressure: [[1, ['0','1','5','6','10']]] + throughput: 0.20 + uops: 1 +- name: [cmp, cmpeqpd, cmpltpd, cmplepd, cmpunordpd, cmpneqpd, cmpnltpd, cmpnlepd, cmpordpd, cmpltps, cmpleps, cmpunordps, cmpneqps, cmpnltps, cmpnleps, cmpordps] + operands: + - class: immediate + imd: int + - class: register + name: '*' + latency: 1.0 + port_pressure: [[1, ['0','1','5','6','10']]] + throughput: 0.20 + uops: 1 +########################################## +- name: push + operands: + - class: immediate + imd: int + latency: 0 + port_pressure: [[1, '78'], [1, '49']] + throughput: 0.5 + uops: 2 +- name: push + operands: + - class: register + name: gpr + latency: 12 + port_pressure: [[1, '78'], [1, '49']] + throughput: 0.5 + uops: 2 +- name: push + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + latency: 0 + port_pressure: [[1, '78'], [1, '49']] + throughput: 0.5 + uops: 2 +- name: pop + operands: + - class: immediate + imd: int + latency: 5 + port_pressure: [[1, ['2', '3', '10']]] + throughput: 0.3333333333333333 + uops: 2 +- name: pop + operands: + - class: register + name: gpr + latency: 5 + port_pressure: [[1, ['2', '3', '10']]] + throughput: 0.3333333333333333 + uops: 2 +- name: pop + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + latency: 5 + port_pressure: [[1, ['2', '3', '10']]] + throughput: 0.3333333333333333 + uops: 2 +########################################## +- name: mov # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: mov # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: mov # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: mov # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: immediate # ./generate_mov_entries.py spr + imd: int # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: mov # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: immediate # ./generate_mov_entries.py spr + imd: int # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: movabs # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: immediate # ./generate_mov_entries.py spr + imd: int # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: movapd # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: movapd # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: movapd # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovapd # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovapd # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovapd # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovapd # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovapd # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovapd # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovapd # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovapd # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr + throughput: 1.0 # ./generate_mov_entries.py spr + uops: 4 # ./generate_mov_entries.py spr +- name: vmovapd # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1.5, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 1.5 # ./generate_mov_entries.py spr +- name: movaps # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: movaps # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: movaps # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovaps # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovaps # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovaps # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovaps # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovaps # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovaps # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovaps # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovaps # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr + throughput: 1.0 # ./generate_mov_entries.py spr + uops: 4 # ./generate_mov_entries.py spr +- name: vmovaps # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1.5, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 1.5 # ./generate_mov_entries.py spr +- name: movdqa # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: movdqa # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: movdqa # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqa # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqa # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovdqa # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqa # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqa # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovdqa # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqa32 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqa32 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovdqa32 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqa32 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqa32 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovdqa32 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqa32 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqa32 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1.5, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 1.5 # ./generate_mov_entries.py spr +- name: vmovdqa32 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr + throughput: 1.0 # ./generate_mov_entries.py spr + uops: 4 # ./generate_mov_entries.py spr +- name: vmovdqa64 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqa64 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovdqa64 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqa64 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqa64 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovdqa64 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqa64 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqa64 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1.5, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 1.5 # ./generate_mov_entries.py spr +- name: vmovdqa64 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr + throughput: 1.0 # ./generate_mov_entries.py spr + uops: 4 # ./generate_mov_entries.py spr +- name: movdqu # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: movdqu # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: movdqu # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqu # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqu # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovdqu # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqu # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqu # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovdqu # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqu8 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqu8 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovdqu8 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqu8 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqu8 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovdqu8 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqu8 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqu8 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1.5, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 1.5 # ./generate_mov_entries.py spr +- name: vmovdqu8 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr + throughput: 1.0 # ./generate_mov_entries.py spr + uops: 4 # ./generate_mov_entries.py spr +- name: vmovdqu16 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqu16 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovdqu16 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqu16 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqu16 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovdqu16 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqu16 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqu16 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1.5, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 1.5 # ./generate_mov_entries.py spr +- name: vmovdqu16 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr + throughput: 1.0 # ./generate_mov_entries.py spr + uops: 4 # ./generate_mov_entries.py spr +- name: vmovdqu32 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqu32 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovdqu32 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqu32 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqu32 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovdqu32 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqu32 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqu32 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1.5, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 1.5 # ./generate_mov_entries.py spr +- name: vmovdqu32 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr + throughput: 1.0 # ./generate_mov_entries.py spr + uops: 4 # ./generate_mov_entries.py spr +- name: vmovdqu64 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqu64 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovdqu64 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqu64 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqu64 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovdqu64 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovdqu64 # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovdqu64 # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1.5, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 1.5 # ./generate_mov_entries.py spr +- name: vmovdqu64 # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr + throughput: 1.0 # ./generate_mov_entries.py spr + uops: 4 # ./generate_mov_entries.py spr +- name: movntdq # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovntdq # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovntdq # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovntdq # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr + throughput: 1.0 # ./generate_mov_entries.py spr + uops: 4 # ./generate_mov_entries.py spr +- name: movntdqa # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovntdqa # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovntdqa # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovntdqa # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1.5, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 1.5 # ./generate_mov_entries.py spr +- name: movnti # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: movntpd # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovntpd # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovntpd # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovntpd # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr + throughput: 1.0 # ./generate_mov_entries.py spr + uops: 4 # ./generate_mov_entries.py spr +- name: movntps # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovntps # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovntps # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovntps # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr + throughput: 1.0 # ./generate_mov_entries.py spr + uops: 4 # ./generate_mov_entries.py spr +- name: movntq # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: mm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: movq # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: mm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: mm # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [] # ./generate_mov_entries.py spr + throughput: 0.0 # ./generate_mov_entries.py spr + uops: 0 # ./generate_mov_entries.py spr +- name: movq # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: mm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: movq # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: mm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: movq # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: movq # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: movq # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovq # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovq # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovq # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: movsd # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: movsd # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: movsd # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovsd # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovsd # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovsd # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: movss # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: movss # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovss # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovss # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovss # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovss # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: movss # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: movsx # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: movsx # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: movsxd # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [] # ./generate_mov_entries.py spr + throughput: 0.0 # ./generate_mov_entries.py spr + uops: 0 # ./generate_mov_entries.py spr +- name: movsxd # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: movsb # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: movsb # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: movsw # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: movsw # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: movsl # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: movsl # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: movsq # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: movsq # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: gpr # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: movupd # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: movupd # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: movupd # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovupd # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovupd # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovupd # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovupd # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovupd # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovupd # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovupd # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovupd # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1.5, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 1.5 # ./generate_mov_entries.py spr +- name: vmovupd # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr + throughput: 1.0 # ./generate_mov_entries.py spr + uops: 4 # ./generate_mov_entries.py spr +- name: movups # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: movups # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: movups # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovups # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovups # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovups # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: xmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovups # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovups # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.3333333333333333 # ./generate_mov_entries.py spr + uops: 1 # ./generate_mov_entries.py spr +- name: vmovups # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: ymm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 2 # ./generate_mov_entries.py spr +- name: vmovups # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 1 # ./generate_mov_entries.py spr + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr + throughput: 0.2 # ./generate_mov_entries.py spr + uops: 1.0 # ./generate_mov_entries.py spr +- name: vmovups # with load # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + latency: 5 # ./generate_mov_entries.py spr + port_pressure: [[1.5, ['2', '3', '10']]] # ./generate_mov_entries.py spr + throughput: 0.5 # ./generate_mov_entries.py spr + uops: 1.5 # ./generate_mov_entries.py spr +- name: vmovups # with store # ./generate_mov_entries.py spr + operands: # ./generate_mov_entries.py spr + - class: register # ./generate_mov_entries.py spr + name: zmm # ./generate_mov_entries.py spr + - class: memory # ./generate_mov_entries.py spr + base: "*" # ./generate_mov_entries.py spr + offset: "*" # ./generate_mov_entries.py spr + index: "*" # ./generate_mov_entries.py spr + scale: "*" # ./generate_mov_entries.py spr + latency: 0 # ./generate_mov_entries.py spr + port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr + throughput: 1.0 # ./generate_mov_entries.py spr + uops: 4 # ./generate_mov_entries.py spr +########################################## +- name: adc # ibench + operands: # ibench + - class: register # ibench + name: gpr # ibench + - class: register # ibench + name: gpr # ibench + latency: 1 # ibench + port_pressure: [[1, '06']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: add # ibench + operands: # ibench + - class: register # ibench + name: gpr # ibench + - class: register # ibench + name: gpr # ibench + latency: 1 # ibench + port_pressure: [[1, ['0','1','5','6','10']]] # ibench + throughput: 0.20 # ibench + uops: 1 # ibench +- name: add # ibench + operands: # ibench + - class: immediate # ibench + imd: int # ibench + - class: register # ibench + name: gpr # ibench + latency: 1 # ibench + port_pressure: [[1, ['0','1','5','6','10']]] # ibench + throughput: 0.20 # ibench + uops: 1 # ibench +- name: addpd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 2 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: addsd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 2 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: mulsd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: mulpd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: mulss # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: mulps # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: addps # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 2 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: addss # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 2 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: rcpss # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 4 # ibench + port_pressure: [[1, '0']] # ibench + throughput: 1.0 # ibench + uops: 1 # ibench +- name: rcpps # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 4 # ibench + port_pressure: [[1, '0']] # ibench + throughput: 1.0 # ibench + uops: 1 # ibench +- name: vrcpps # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 4 # ibench + port_pressure: [[1, '0']] # ibench + throughput: 1.0 # ibench + uops: 1 # ibench +- name: vrcpps # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + latency: 4 # ibench + port_pressure: [[1, '0']] # ibench + throughput: 1.0 # ibench + uops: 1 # ibench +- name: vrcpss # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 4 # ibench + port_pressure: [[1, '0']] # ibench + throughput: 1.0 # ibench + uops: 1 # ibench +- name: sqrtsd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 13 # ibench + port_pressure: [[6, ['0DV']], [1, '0']] # ibench + throughput: 6.0 # ibench + uops: 7 # ibench +- name: sqrtss # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 12 # ibench + port_pressure: [[3, ['0DV']], [1, '0']] # ibench + throughput: 3.0 # ibench + uops: 4 # ibench +- name: vsqrtsd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 13 # ibench + port_pressure: [[6, ['0DV']], [1, '0']] # ibench + throughput: 6.0 # ibench + uops: 7 # ibench +- name: vsqrtss # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 12 # ibench + port_pressure: [[3, ['0DV']], [1, '0']] # ibench + throughput: 3.0 # ibench + uops: 4 # ibench +- name: sub # ibench + operands: # ibench + - class: immediate # ibench + imd: int # ibench + - class: register # ibench + name: gpr # ibench + latency: 1 # ibench + port_pressure: [[1, ['0','1','5','6','10']]] # ibench + throughput: 0.20 # ibench + uops: 1 # ibench +- name: sub # ibench + operands: # ibench + - class: register # ibench + name: gpr # ibench + - class: register # ibench + name: gpr # ibench + latency: 1 # ibench + port_pressure: [[1, ['0','1','5','6','10']]] # ibench + throughput: 0.20 # ibench + uops: 1 # ibench +- name: vaddpd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 2 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vaddpd # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + latency: 2 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vaddpd # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + latency: 3 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vaddpd # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + mask: True # ibench + latency: 3 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vaddpd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 3 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vaddpd # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + mask: True # ibench + latency: 3 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vaddps # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + mask: True # ibench + latency: 3 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vaddps # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + mask: True # ibench + latency: 3 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vaddps # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 3 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vaddps # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 3 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vaddps # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + latency: 3 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vaddps # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + latency: 3 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vaddsd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 2 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vaddsd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 3 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vaddss # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 3 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vaddss # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 2 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vdivpd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 14 # ibench + port_pressure: [[1, '0'], [4, ['0DV']]] # ibench + throughput: 4.0 # ibench + uops: 4 # ibench +- name: vdivpd # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + latency: 14 # asmbench + port_pressure: [[1, '0'], [8, ['0DV']]] # asmbench + throughput: 8.0 # asmbench + uops: 8 # asmbench +- name: vdivpd # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + latency: 23 # ibench + port_pressure: [[1, '0'], [16, ['0DV']]] # ibench + throughput: 16.0 # ibench + uops: 16 # ibench +- name: vdivpd # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + mask: True # ibench + latency: 23 # ibench + port_pressure: [[1, '0'], [16, ['0DV']]] # ibench + throughput: 16.0 # ibench + uops: 16 # ibench +- name: vdivpd # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + mask: True # ibench + latency: 14 # ibench + port_pressure: [[1, '0'], [8, ['0DV']]] # ibench + throughput: 8.0 # ibench + uops: 8 # ibench +- name: vdivpd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 13 # ibench + port_pressure: [[1, '0'], [4, ['0DV']]] # ibench + throughput: 4.0 # ibench + uops: 4 # ibench +- name: vdivps # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + latency: 18 # ibench + port_pressure: [[1, '0'], [10, ['0DV']]] # ibench + throughput: 10.0 # ibench + uops: 10 # ibench +- name: vdivps # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + mask: True # ibench + latency: 18 # ibench + port_pressure: [[1, '0'], [10, ['0DV']]] # ibench + throughput: 10.0 # ibench + uops: 10 # ibench +- name: vdivps # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + mask: True # ibench + latency: 11 # ibench + port_pressure: [[1, '0'], [5, ['0DV']]] # ibench + throughput: 5.0 # ibench + uops: 5 # ibench +- name: vdivps # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + latency: 11 # ibench + port_pressure: [[1, '0'], [5, ['0DV']]] # ibench + throughput: 5.0 # ibench + uops: 5 # ibench +- name: vdivps # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 11 # ibench + port_pressure: [[1, '0'], [3, ['0DV']]] # ibench + throughput: 3.0 # ibench + uops: 3 # ibench +- name: vdivps # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 11 # ibench + port_pressure: [[1, '0'], [3, ['0DV']]] # ibench + throughput: 3.0 # ibench + uops: 3 # ibench +- name: vdivss # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 11 # ibench + port_pressure: [[1, '0'], [3, ['0DV']]] # ibench + throughput: 3.0 # ibench + uops: 4 # ibench +- name: vdivss # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 11 # ibench + port_pressure: [[1, '0'], [3, ['0DV']]] # ibench + throughput: 3.0 # ibench + uops: 3 # ibench +- name: vdivsd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 14 # ibench + port_pressure: [[1, '0'], [4, ['0DV']]] # ibench + throughput: 4.0 # ibench + uops: 4 # ibench +- name: vdivsd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 14 # ibench + port_pressure: [[1, '0'], [4, ['0DV']]] # ibench + throughput: 4.0 # ibench + uops: 4 # ibench +- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd] # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + mask: True # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd] # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd] # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + latency: 4 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd] # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + mask: True # ibench + latency: 4 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps] # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps] # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + mask: True # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps] # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + latency: 4 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps] # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + mask: True # ibench + latency: 4 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmadd213sd, vfmadd132sd, vfmadd231sd, vfnmadd213sd, vfnmadd132sd, vfnmadd231sd] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmadd213sd, vfmadd132sd, vfmadd231sd, vfnmadd213sd, vfnmadd132sd, vfnmadd231sd] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmadd213ss, vfmadd132ss, vfmadd231ss, vfnmadd213ss, vfnmadd132ss, vfnmadd231ss] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmadd213ss, vfmadd132ss, vfmadd231ss, vfnmadd213ss, vfnmadd132ss, vfnmadd231ss] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd] # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + mask: True # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd] # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd] # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + latency: 4 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd] # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + mask: True # ibench + latency: 4 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps] # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps] # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + mask: True # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps] # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + latency: 4 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps] # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + mask: True # ibench + latency: 4 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmsub213sd, vfmsub132sd, vfmsub231sd, vfnmsub213sd, vfnmsub132sd, vfnmsub231sd] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmsub213sd, vfmsub132sd, vfmsub231sd, vfnmsub213sd, vfnmsub132sd, vfnmsub231sd] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmsub213ss, vfmsub132ss, vfmsub231ss, vfnmsub213ss, vfnmsub132ss, vfnmsub231ss] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vfmsub213ss, vfmsub132ss, vfmsub231ss, vfnmsub213ss, vfnmsub132ss, vfnmsub231ss] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vgatherdpd # with load # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: memory # ibench + base: "*" # ibench + offset: "*" # ibench + index: "*" # ibench + scale: "*" # ibench + - class: register # ibench + name: xmm # ibench + latency: 20 # ibench + port_pressure: [[1, '015'], [1, '15'], [1, '0'], [3, ['2','3','11']]] # ibench + throughput: 1.0 # ibench + uops: 9 # ibench +- name: vgatherdpd # with load # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: memory # ibench + base: "*" # ibench + offset: "*" # ibench + index: "*" # ibench + scale: "*" # ibench + - class: register # ibench + name: ymm # ibench + latency: 22 # ibench + port_pressure: [[1, '015'], [1, '15'], [1, '0'], [6, ['2','3','11']]] # ibench + throughput: 2.0 # ibench + uops: 16 # ibench +- name: vgatherdpd # with load # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: memory # ibench + base: "*" # ibench + offset: "*" # ibench + index: "*" # ibench + scale: "*" # ibench + - class: register # ibench + name: zmm # ibench + latency: 26 # ibench + port_pressure: [[1, '015'], [1, '15'], [1, '0'], [9, ['2','3','11']]] # ibench + throughput: 3.0 # ibench + uops: 31 # ibench +- name: vgatherdpd # with load # ibench + operands: # ibench + - class: memory # ibench + base: "*" # ibench + offset: "*" # ibench + index: "*" # ibench + scale: "*" # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 20 # ibench + port_pressure: [[1, '015'], [1, '15'], [1, '0'], [3, ['2','3','11']]] # ibench + throughput: 1.0 # ibench + uops: 9 # ibench +- name: vgatherdpd # with load # ibench + operands: # ibench + - class: memory # ibench + base: "*" # ibench + offset: "*" # ibench + index: "*" # ibench + scale: "*" # ibench + - class: register # ibench + name: ymm # ibench + mask: True # ibench + latency: 22 # ibench + port_pressure: [[1, '015'], [1, '15'], [1, '0'], [6, ['2','3','11']]] # ibench + throughput: 2.0 # ibench + uops: 16 # ibench +- name: vgatherdpd # with load # ibench + operands: # ibench + - class: memory # ibench + base: "*" # ibench + offset: "*" # ibench + index: "*" # ibench + scale: "*" # ibench + - class: register # ibench + name: zmm # ibench + mask: True # ibench + latency: 26 # ibench + port_pressure: [[1, '015'], [1, '15'], [1, '0'], [9, ['2','3','11']]] # ibench + throughput: 3.0 # ibench + uops: 31 # ibench +- name: vgatherdps # with load # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: memory # ibench + base: "*" # ibench + offset: "*" # ibench + index: "*" # ibench + scale: "*" # ibench + - class: register # ibench + name: xmm # ibench + latency: 21 # ibench + port_pressure: [[1, '015'], [1, '15'], [1, '0'], [6, ['2','3','11']]] # ibench + throughput: 2.0 # ibench + uops: 15 # ibench +- name: vgatherdps # with load # ibench + operands: # ibench + - class: memory # ibench + base: "*" # ibench + offset: "*" # ibench + index: "*" # ibench + scale: "*" # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 21 # ibench + port_pressure: [[1, '015'], [1, '15'], [1, '0'], [6, ['2','3','11']]] # ibench + throughput: 2.0 # ibench + uops: 15 # ibench +- name: vgatherdps # with load # uops.info + operands: # uops.info + - class: register # uops.info + name: ymm # uops.info + - class: memory # uops.info + base: "*" # uops.info + offset: "*" # uops.info + index: "*" # uops.info + scale: "*" # uops.info + - class: register # uops.info + name: ymm # uops.info + latency: 23 # uops.info + port_pressure: [[1, '015'], [1, '15'], [1, '0'], [9, ['2','3','11']]] # ibench + throughput: 3.0 # uops.info + uops: 23 # uops.info +- name: vgatherdps # with load # uops.info + operands: # uops.info + - class: memory # uops.info + base: "*" # uops.info + offset: "*" # uops.info + index: "*" # uops.info + scale: "*" # uops.info + - class: register # uops.info + name: ymm # uops.info + mask: True # ibench + latency: 23 # uops.info + port_pressure: [[1, '015'], [1, '15'], [1, '0'], [9, ['2','3','11']]] # ibench + throughput: 3.0 # uops.info + uops: 23 #uops.info +- name: vgatherdps # with load # uops.info + operands: # uops.info + - class: register # uops.info + name: zmm # uops.info + - class: memory # uops.info + base: "*" # uops.info + offset: "*" # uops.info + index: "*" # uops.info + scale: "*" # uops.info + - class: register # uops.info + name: zmm # uops.info + latency: 26 # uops.info + port_pressure: [[1, '015'], [1, '15'], [1, '0'], [15, ['2','3','11']]] # ibench + throughput: 5.0 # uops.info + uops: 39 #uops.info +- name: vgatherdps # with load # uops.info + operands: # uops.info + - class: memory # uops.info + base: "*" # uops.info + offset: "*" # uops.info + index: "*" # uops.info + scale: "*" # uops.info + - class: register # uops.info + name: zmm # uops.info + mask: True # ibench + latency: 26 # uops.info + port_pressure: [[1, '015'], [1, '15'], [1, '0'], [15, ['2','3','11']]] # ibench + throughput: 5.0 # uops.info + uops: 39 #uops.info +- name: vmulpd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 5 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vmulpd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vmulpd # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vmulpd # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + mask: True # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vmulpd # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + latency: 4 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vmulpd # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + mask: True # ibench + latency: 4 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vmulps # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vmulps # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vmulps # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vmulps # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + mask: True # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vmulps # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + latency: 4 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vmulps # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + mask: True # ibench + latency: 4 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vmulsd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vmulsd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vmulss # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vmulss # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 4 # ibench + port_pressure: [[1, '01']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vpaddd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 1 # ibench + port_pressure: [[1, '015']] # ibench + throughput: 0.3333333333333333 # ibench + uops: 1 # ibench +- name: vpaddd # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + latency: 1 # ibench + port_pressure: [[1, '015']] # ibench + throughput: 0.3333333333333333 # ibench + uops: 1 # ibench +- name: vpaddd # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + latency: 1 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vpaddd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 1 # ibench + port_pressure: [[1, '015']] # ibench + throughput: 0.3333333333333333 # ibench + uops: 1 # ibench +- name: vpaddd # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + mask: True # ibench + latency: 1 # ibench + port_pressure: [[1, '015']] # ibench + throughput: 0.3333333333333333 # ibench + uops: 1 # ibench +- name: vpaddd # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + mask: True # ibench + latency: 1 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vrcp14pd, vrcp14ps] # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vrcp14pd, vrcp14ps] # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vrcp14pd, vrcp14ps] # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + latency: 6 # asmbench + port_pressure: [[4, '05']] # asmbench + throughput: 2.0 # asmbench + uops: 3 # asmbench +- name: [vrcp14pd, vrcp14ps] # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + mask: True # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vrcp14pd, vrcp14ps] # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + mask: True # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vrcp14pd, vrcp14ps] # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + mask: True # asmbench + latency: 6 # asmbench + port_pressure: [[4, '05']] # asmbench + throughput: 2.0 # asmbench + uops: 3 # asmbench +- name: vrcpss # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vrcpps # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vrcpps # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vrsqrt14pd, vrsqrt14ps] # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vrsqrt14pd, vrsqrt14ps] # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vrsqrt14pd, vrsqrt14ps] # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + latency: 6 # asmbench + port_pressure: [[4, '05']] # asmbench + throughput: 2.0 # asmbench + uops: 3 # asmbench +- name: [vrsqrt14pd, vrsqrt14ps] # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + mask: True # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vrsqrt14pd, vrsqrt14ps] # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + mask: True # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vrsqrt14pd, vrsqrt14ps] # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + mask: True # asmbench + latency: 6 # asmbench + port_pressure: [[4, '05']] # asmbench + throughput: 2.0 # asmbench + uops: 3 # asmbench +- name: vrsqrtpd # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vrsqrtpd # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vrsqrtps # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vrsqrtps # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vrsqrtpd # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + mask: True # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vrsqrtpd # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + mask: True # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vrsqrtps # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + mask: True # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vrsqrtps # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + mask: True # asmbench + latency: 4 # asmbench + port_pressure: [[1, '0']] # asmbench + throughput: 1.0 # asmbench + uops: 7 # asmbench +- name: vrsqrtpd # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + latency: 10 # asmbench + port_pressure: [[2, '0']] # asmbench + throughput: 2.0 # asmbench + uops: 19 # asmbench +- name: vrsqrtpd # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + mask: True # asmbench + latency: 10 # asmbench + port_pressure: [[2, '0']] # asmbench + throughput: 2.0 # asmbench + uops: 2 # asmbench +- name: vrsqrtps # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + latency: 10 # asmbench + port_pressure: [[2, '0']] # asmbench + throughput: 2.0 # asmbench + uops: 2 # asmbench +- name: vrsqrtps # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + mask: True # asmbench + latency: 10 # asmbench + port_pressure: [[2, '0']] # asmbench + throughput: 2.0 # asmbench + uops: 2 # asmbench +- name: [inc, dec] + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: vcvtss2si # uops.info + operands: # uops.info + - class: register # uops.info + name: xmm # uops.info + - class: register # uops.info + name: gpr # uops.info + latency: 8 # uops.info + port_pressure: [[1, '01'], [1, '5']] # uops.info + throughput: 1 # uops.info + uops: 3 # uops.info +- name: vcvtss2sd # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + latency: 5 # asmbench + port_pressure: [[1, '01'], [1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 2 # asmbench +- name: [vsubpd, vsubps] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 2 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vsubpd, vsubps] # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 3 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vsubpd, vsubps] # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + latency: 2 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vsubpd, vsubps] # ibench + operands: # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + - class: register # ibench + name: ymm # ibench + mask: True # ibench + latency: 3 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vsubpd, vsubps] # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + latency: 3 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: [vsubpd, vsubps] # ibench + operands: # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + - class: register # ibench + name: zmm # ibench + mask: True # ibench + latency: 3 # ibench + port_pressure: [[1, '05']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vsubsd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 2 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vsubsd # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 3 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vsubss # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + mask: True # ibench + latency: 3 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: vsubss # ibench + operands: # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + - class: register # ibench + name: xmm # ibench + latency: 2 # ibench + port_pressure: [[1, '15']] # ibench + throughput: 0.5 # ibench + uops: 1 # ibench +- name: lea # uops.info + operands: # uops.info + - class: memory # uops.info + base: "*" # uops.info + offset: "*" # uops.info + index: "*" # uops.info + scale: "*" # uops.info + - class: register # uops.info + name: gpr # uops.info + latency: 1 # uops.info + port_pressure: [[1, ['0','1','5','6','11']]] # uops.info + throughput: 0.2 # uops.info + uops: 1 # uops.info +- name: [shl, shr, sal, sar] # uops.info + operands: # uops.info + - class: immediate # uops.info + imd: int # uops.info + - class: register # uops.info + name: gpr # uops.info + latency: 1 # uops.info + port_pressure: [[1, '06']] # uops.info + throughput: 0.5 # uops.info + uops: 1 # uops.info +- name: [shl, shr, sal, sar] + operands: + - class: register + name: gpr + latency: 1 # uops.info + port_pressure: [[1, '06']] # uops.info + throughput: 0.5 # uops.info + uops: 1 # uops.info +############## || ################# +############## \/ assumed from ICX ################# +- name: vinsertf128 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vinserti128 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vinsertf32x4 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vinsertf32x8 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vinsertf64x2 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vinsertf64x4 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vinsertps + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vinserti64x4 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vinserti64x2 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vinserti32x8 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vinsertf32x4 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vcvtsi2ss + operands: + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '01'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: [vextractf128, vextracti128] + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vextractps + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: [vextractf32x4, vextracti32x4] # uops.info + operands: # uops.info + - class: immediate # uops.info + imd: int # uops.info + - class: register # uops.info + name: ymm # uops.info + - class: register # uops.info + name: xmm # uops.info + latency: 3 # uops.info + port_pressure: [[1, '5']] # uops.info + throughput: 1.0 # uops.info + uops: 1 # uops.info +- name: [vextractf32x4, vextracti32x4] # uops.info + operands: # uops.info + - class: immediate # uops.info + imd: int # uops.info + - class: register # uops.info + name: zmm # uops.info + - class: register # uops.info + name: xmm # uops.info + latency: 3 # uops.info + port_pressure: [[1, '5']] # uops.info + throughput: 1.0 # uops.info + uops: 1 # uops.info +- name: [vextractf32x4, vextracti32x4] # uops.info + operands: # uops.info + - class: immediate # uops.info + imd: int # uops.info + - class: register # uops.info + name: zmm # uops.info + - class: register # uops.info + name: xmm # uops.info + mask: True # uops.info + latency: 3 # uops.info + port_pressure: [[1, '5']] # uops.info + throughput: 1.0 # uops.info + uops: 1 # uops.info +- name: [vextractf32x4, vextracti32x4] # uops.info + operands: # uops.info + - class: immediate # uops.info + imd: int # uops.info + - class: register # uops.info + name: ymm # uops.info + - class: register # uops.info + name: xmm # uops.info + mask: True # uops.info + latency: 3 # uops.info + port_pressure: [[1, '5']] # uops.info + throughput: 1.0 # uops.info + uops: 1 # uops.info +- name: [vextractf32x8, vextracti32x8] # uops.info + operands: # uops.info + - class: immediate # uops.info + imd: int # uops.info + - class: register # uops.info + name: zmm # uops.info + - class: register # uops.info + name: ymm # uops.info + mask: True # uops.info + latency: 3 # uops.info + port_pressure: [[1, '5']] # uops.info + throughput: 1.0 # uops.info + uops: 1 # uops.info +- name: [vextractf32x8, vextracti32x8] # uops.info + operands: # uops.info + - class: immediate # uops.info + imd: int # uops.info + - class: register # uops.info + name: zmm # uops.info + - class: register # uops.info + name: ymm # uops.info + latency: 3 # uops.info + port_pressure: [[1, '5']] # uops.info + throughput: 1.0 # uops.info + uops: 1 # uops.info +- name: [vextractf64x2, vextracti64x2] # uops.info + operands: # uops.info + - class: immediate # uops.info + imd: int # uops.info + - class: register # uops.info + name: ymm # uops.info + - class: register # uops.info + name: xmm # uops.info + latency: 3 # uops.info + port_pressure: [[1, '5']] # uops.info + throughput: 1.0 # uops.info + uops: 1 # uops.info +- name: [vextractf64x2, vextracti64x2] # uops.info + operands: # uops.info + - class: immediate # uops.info + imd: int # uops.info + - class: register # uops.info + name: ymm # uops.info + - class: register # uops.info + name: xmm # uops.info + mask: True # uops.info + latency: 3 # uops.info + port_pressure: [[1, '5']] # uops.info + throughput: 1.0 # uops.info + uops: 1 # uops.info +- name: [vextractf64x2, vextracti64x2] # uops.info + operands: # uops.info + - class: immediate # uops.info + imd: int # uops.info + - class: register # uops.info + name: zmm # uops.info + - class: register # uops.info + name: xmm # uops.info + mask: True # uops.info + latency: 3 # uops.info + port_pressure: [[1, '5']] # uops.info + throughput: 1.0 # uops.info + uops: 1 # uops.info +- name: [vextractf64x2, vextracti64x2] # uops.info + operands: # uops.info + - class: immediate # uops.info + imd: int # uops.info + - class: register # uops.info + name: zmm # uops.info + - class: register # uops.info + name: xmm # uops.info + latency: 3 # uops.info + port_pressure: [[1, '5']] # uops.info + throughput: 1.0 # uops.info + uops: 1 # uops.info +- name: [vextractf64x4, vextracti64x4] # uops.info + operands: # uops.info + - class: immediate # uops.info + imd: int # uops.info + - class: register # uops.info + name: zmm # uops.info + - class: register # uops.info + name: ymm # uops.info + latency: 3 # uops.info + port_pressure: [[1, '5']] # uops.info + throughput: 1.0 # uops.info + uops: 1 # uops.info +- name: [vextractf64x4, vextracti64x4] # uops.info + operands: # uops.info + - class: immediate # uops.info + imd: int # uops.info + - class: register # uops.info + name: zmm # uops.info + - class: register # uops.info + name: ymm # uops.info + mask: True # uops.info + latency: 3 # uops.info + port_pressure: [[1, '5']] # uops.info + throughput: 1.0 # uops.info + uops: 1 # uops.info +- name: vpalignr # asmbench + operands: # asmbench + - class: immediate # asmbench + imd: int # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vpalignr # asmbench + operands: # asmbench + - class: immediate # asmbench + imd: int # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vpalignr # asmbench + operands: # asmbench + - class: immediate # asmbench + imd: int # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vpalignr # asmbench + operands: # asmbench + - class: immediate # asmbench + imd: int # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vpalignr # asmbench + operands: # asmbench + - class: immediate # asmbench + imd: int # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vpalignr # asmbench + operands: # asmbench + - class: immediate # asmbench + imd: int # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vperm2f128, vperm2i128] # asmbench + operands: # asmbench + - class: immediate # asmbench + imd: int # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + latency: 3 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vpermd # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + latency: 3 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vpermd # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + mask: True # asmbench + latency: 3 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vpermd # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + latency: 3 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: vpermd # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + mask: True # asmbench + latency: 3 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermpd, vpermps] # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + latency: 3 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermpd, vpermps] # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + mask: True # asmbench + latency: 3 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermpd, vpermps] # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + latency: 3 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermpd, vpermps] # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + mask: True # asmbench + latency: 3 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpcmpgtb, vpcmpgtw, vpcmpgtd, vpcmpgtq] + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: [vpcmpgtb, vpcmpgtw, vpcmpgtd, vpcmpgtq] + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: [vpcmpgtb, vpcmpgtw, vpcmpgtd, vpcmpgtq, vpcmpeqb, vpcmpeqw, vpcmpeqd, vpcmpeqq] + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vpcmpd + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vpcmpd + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vpcmpd + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: [vpcmpeqb, vpcmpeqw, vpcmpeqd, vpcmpeqq] + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: [vpcmpeqb, vpcmpeqw, vpcmpeqd, vpcmpeqq] + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: [vcmpltpd, vcmpltps] # uops.info + operands: # uops.info + - class: register # uops.info + name: zmm # uops.info + - class: register # uops.info + name: zmm # uops.info + - class: register # uops.info + name: k # uops.info + mask: True # uops.info + latency: 4 # uops.info + port_pressure: [[1, '05']] # uops.info + throughput: 0.5 # uops.info + uops: 1 # uops.info +- name: [vcmpltpd, vcmpltps] # uops.info + operands: # uops.info + - class: register # uops.info + name: ymm # uops.info + - class: register # uops.info + name: ymm # uops.info + - class: register # uops.info + name: ymm # uops.info + latency: 4 # uops.info + port_pressure: [[1, '05']] # uops.info + throughput: 0.5 # uops.info + uops: 1 # uops.info +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: True + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: True + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: True + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: True + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: True + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: True + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: vpunpckhqdq + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: vpunpckhqdq + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: vpunpckhqdq + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 + +########### /\ ########## +########### || assumed from ICX ########## +- name: AND + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: RET + operands: [] + latency: 0 + port_pressure: [[1, '49'], [1, '78']] + throughput: 0.5 + uops: 2 +- name: CALL + operands: + - class: identifier + latency: 0 + port_pressure: [[1, '49'], [1, '78']] + throughput: 0.5 + uops: 2 +- name: TEST + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: TEST + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: PTEST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPTEST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPTEST + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: [VTESTPD, VTESTPS] + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: [VTESTPD, VTESTPS] + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VXORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: VXORPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: VXORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: VXORPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: VBROADCASTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: [VBROADCASTSD, VBROADCASTSS] + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: [VBROADCASTSD, VBROADCASTSS] + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: [VBROADCASTSD, VBROADCASTSS] + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '23'], [1, ['2D', '3D']], [1, '015']] + throughput: 1.0 + uops: 1 +- name: [VBROADCASTSD, VBROADCASTSS] + operands: + - class: memory + base: "*" + offset: "*" + index: "*" + scale: "*" + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '23'], [1, ['2D', '3D']], [1, '015']] + throughput: 1.0 + uops: 1 +- name: vandpd + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.33333 + uops: 1 +- name: vandpd + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.33333 + uops: 1 +- name: vandpd + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: vshuff64x2 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 diff --git a/osaca/osaca.py b/osaca/osaca.py index 59e342e..c60e950 100755 --- a/osaca/osaca.py +++ b/osaca/osaca.py @@ -30,6 +30,7 @@ SUPPORTED_ARCHS = [ "CSX", "ICL", "ICX", + "SPR", "ZEN1", "ZEN2", "ZEN3", @@ -102,8 +103,8 @@ def create_parser(parser=None): parser.add_argument( "--arch", type=str, - help="Define architecture (SNB, IVB, HSW, BDW, SKX, CSX, ICL, ICX, ZEN1, ZEN2, ZEN3, TX2, N1, " - "A64FX, TSV110, A72, M1, V2). If no architecture is given, OSACA assumes a default uarch for " + help="Define architecture (SNB, IVB, HSW, BDW, SKX, CSX, ICL, ICX, SPR, ZEN1, ZEN2, ZEN3, " + "TX2, N1, A64FX, TSV110, A72, M1, V2). If no architecture is given, OSACA assumes a default uarch for " "x86/AArch64.", ) parser.add_argument( diff --git a/osaca/semantics/hw_model.py b/osaca/semantics/hw_model.py index cc19579..9bc67d5 100755 --- a/osaca/semantics/hw_model.py +++ b/osaca/semantics/hw_model.py @@ -303,6 +303,7 @@ class MachineModel(object): "cfl": "x86", "icl": "x86", "icx": "x86", + "spr": "x86", } arch = arch.lower() if arch in arch_dict: From 2ba04e614ab1d577b992cc02bd8ee72df532fa8a Mon Sep 17 00:00:00 2001 From: JanLJL Date: Thu, 2 May 2024 21:17:57 +0200 Subject: [PATCH 3/7] DB update --- osaca/data/m1.yml | 54 +-- osaca/data/spr.yml | 1017 ++++++++++++++++++++++++++++---------------- osaca/data/v2.yml | 414 ++++++++++++------ 3 files changed, 945 insertions(+), 540 deletions(-) diff --git a/osaca/data/m1.yml b/osaca/data/m1.yml index 229737b..a2667a1 100644 --- a/osaca/data/m1.yml +++ b/osaca/data/m1.yml @@ -24,7 +24,7 @@ port_model_scheme: | | 36 | | 36 | | 36 | | 36 | | 48 | | 24 | | 26 | | 16 | | 12 | | 28 | | 28 | +------+ +------+ +------+ +-------------+ +-----------------------------+ +------+ +------+ +------+ +------+ +-------------+ +------+ 0 |FP0 1 |FP1 2 |FP2 3 |FP3 4 |D0 5 |D1 6 |D2 7 |D3 8 |INT0 9 |INT1 10 |INT2 11 |INT3 12 |INT4 13 |INT5 - \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ + \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ +------+ +------+ +------+ +------+ +----+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ | ALU | | ALU | | ALU | | ALU | | DV | | LD | | ST | | LD | | LD | | ALU | | ALU | | ALU | | ALU | | ALU | | DV | | ALU | +------+ +------+ +------+ +------+ +----+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ @@ -37,15 +37,15 @@ port_model_scheme: | +------+ +------+ +------+ +------+ +------+ +------+ | FCSEL| | FCSEL| | FLAGS| | FLAGS| |MOV FP| silly | FMA | +------+ +------+ +------+ +------+ +------+ +------+ - +------+ +------+ - | 2INT | | 2INT | - +------+ +------+ - +------+ - | RCP | - +------+ - +------+ - | SHA | - +------+ + +------+ +------+ + | 2INT | | 2INT | + +------+ +------+ + +------+ + | RCP | + +------+ + +------+ + | SHA | + +------+ instruction_forms: - name: [adc, adcs] operands: @@ -105,7 +105,7 @@ instruction_forms: - name: adds operands: - class: register - prefix: '*' + prefix: '*' - class: register prefix: '*' - class: register @@ -116,7 +116,7 @@ instruction_forms: - name: adds operands: - class: register - prefix: '*' + prefix: '*' - class: register prefix: '*' - class: immediate @@ -127,7 +127,7 @@ instruction_forms: - name: adr operands: - class: register - prefix: '*' + prefix: '*' - class: identifier throughput: 0.5 latency: ~ # 1*p89 @@ -1521,7 +1521,7 @@ instruction_forms: throughput: 0.16666666 latency: ~ # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] -- name: [orn, orr] +- name: [orn, orr] operands: - class: register prefix: x @@ -1532,7 +1532,7 @@ instruction_forms: throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] -- name: [orn, orr] +- name: [orn, orr] operands: - class: register prefix: x @@ -1543,7 +1543,7 @@ instruction_forms: throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] -- name: [orn, orr] +- name: [orn, orr] operands: - class: register prefix: w @@ -1554,7 +1554,7 @@ instruction_forms: throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] -- name: [orn, orr] +- name: [orn, orr] operands: - class: register prefix: w @@ -1596,8 +1596,8 @@ instruction_forms: latency: ~ port_pressure: [] - name: ret - operands: - - class: identifier + operands: + - class: identifier throughput: 0.0 latency: ~ port_pressure: [] @@ -1650,7 +1650,7 @@ instruction_forms: - name: [scvtf, ucvtf] operands: - class: register - prefix: s + prefix: s - class: register prefix: w throughput: 0.33333333 @@ -1659,7 +1659,7 @@ instruction_forms: - name: [scvtf, ucvtf] operands: - class: register - prefix: d + prefix: d - class: register prefix: x throughput: 0.33333333 @@ -1668,7 +1668,7 @@ instruction_forms: - name: [scvtf, ucvtf] operands: - class: register - prefix: d + prefix: d - class: register prefix: x - class: immediate @@ -1679,7 +1679,7 @@ instruction_forms: - name: [scvtf, ucvtf] operands: - class: register - prefix: s + prefix: s - class: register prefix: w - class: immediate @@ -2831,9 +2831,9 @@ instruction_forms: prefix: "*" - class: register prefix: "*" - - class: immediate + - class: immediate imd: int - - class: immediate + - class: immediate imd: int throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 @@ -2912,7 +2912,7 @@ instruction_forms: prefix: s - class: immediate imd: int - - class: condition + - class: condition ccode: "*" throughput: 1.0 latency: 1.0 # 1*p3 @@ -3617,7 +3617,7 @@ instruction_forms: width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 - port_pressure: [[1, '0123']] + port_pressure: [[1, '0123']] - name: [fmla, fmls] operands: - class: register diff --git a/osaca/data/spr.yml b/osaca/data/spr.yml index 9b8ff68..c95540f 100644 --- a/osaca/data/spr.yml +++ b/osaca/data/spr.yml @@ -2,9 +2,9 @@ osaca_version: 0.5.3 micro_architecture: Sapphire Rapids arch_code: SPR isa: x86 -ROB_size: ~ +ROB_size: ~ retired_uOps_per_cycle: ~ -scheduler_size: ~ +scheduler_size: ~ hidden_loads: false load_latency: {gpr: 5.0, mm: 5.0, xmm: 5.0, ymm: 5.0, zmm: 5.0} load_throughput: @@ -13,7 +13,7 @@ load_throughput: - {dst: xmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['2', '3', '11']]]} - {dst: gpr, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['2', '3', '11']]]} load_throughput_default: [[1, ['2', '3', '11']]] -store_throughput: +store_throughput: - {src: zmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '78'], [1, '4'], [1, '9']]} - {src: ymm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '78'], [1, '49']]} - {src: xmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '78'], [1, '49']]} @@ -2946,7 +2946,7 @@ instruction_forms: name: xmm # ibench - class: register # ibench name: xmm # ibench - latency: 5 # ibench + latency: 4 # ibench port_pressure: [[1, '01']] # ibench throughput: 0.5 # ibench uops: 1 # ibench @@ -2959,7 +2959,7 @@ instruction_forms: - class: register # ibench name: xmm # ibench mask: True # ibench - latency: 5 # ibench + latency: 4 # ibench port_pressure: [[1, '01']] # ibench throughput: 0.5 # ibench uops: 1 # ibench @@ -3338,7 +3338,7 @@ instruction_forms: port_pressure: [[1, '01']] # ibench throughput: 0.5 # ibench uops: 1 # ibench -- name: vgatherdpd # with load # ibench +- name: [vgatherdpd, vgatherqpd] # with load # ibench operands: # ibench - class: register # ibench name: xmm # ibench @@ -3353,7 +3353,7 @@ instruction_forms: port_pressure: [[1, '015'], [1, '15'], [1, '0'], [3, ['2','3','11']]] # ibench throughput: 1.0 # ibench uops: 9 # ibench -- name: vgatherdpd # with load # ibench +- name: [vgatherdpd, vgatherqpd] # with load # ibench operands: # ibench - class: register # ibench name: ymm # ibench @@ -3368,7 +3368,7 @@ instruction_forms: port_pressure: [[1, '015'], [1, '15'], [1, '0'], [6, ['2','3','11']]] # ibench throughput: 2.0 # ibench uops: 16 # ibench -- name: vgatherdpd # with load # ibench +- name: [vgatherdpd, vgatherqpd] # with load # ibench operands: # ibench - class: register # ibench name: zmm # ibench @@ -3383,7 +3383,7 @@ instruction_forms: port_pressure: [[1, '015'], [1, '15'], [1, '0'], [9, ['2','3','11']]] # ibench throughput: 3.0 # ibench uops: 31 # ibench -- name: vgatherdpd # with load # ibench +- name: [vgatherdpd, vgatherqpd] # with load # ibench operands: # ibench - class: memory # ibench base: "*" # ibench @@ -3397,7 +3397,7 @@ instruction_forms: port_pressure: [[1, '015'], [1, '15'], [1, '0'], [3, ['2','3','11']]] # ibench throughput: 1.0 # ibench uops: 9 # ibench -- name: vgatherdpd # with load # ibench +- name: [vgatherdpd, vgatherqpd] # with load # ibench operands: # ibench - class: memory # ibench base: "*" # ibench @@ -3411,7 +3411,7 @@ instruction_forms: port_pressure: [[1, '015'], [1, '15'], [1, '0'], [6, ['2','3','11']]] # ibench throughput: 2.0 # ibench uops: 16 # ibench -- name: vgatherdpd # with load # ibench +- name: [vgatherdpd, vgatherqpd] # with load # ibench operands: # ibench - class: memory # ibench base: "*" # ibench @@ -3520,7 +3520,7 @@ instruction_forms: name: xmm # ibench - class: register # ibench name: xmm # ibench - latency: 5 # ibench + latency: 4 # ibench port_pressure: [[1, '01']] # ibench throughput: 0.5 # ibench uops: 1 # ibench @@ -3712,7 +3712,7 @@ instruction_forms: port_pressure: [[1, '01']] # ibench throughput: 0.5 # ibench uops: 1 # ibench -- name: vpaddd # ibench +- name: [vpaddd, vpaddq] # ibench operands: # ibench - class: register # ibench name: xmm # ibench @@ -3724,7 +3724,7 @@ instruction_forms: port_pressure: [[1, '015']] # ibench throughput: 0.3333333333333333 # ibench uops: 1 # ibench -- name: vpaddd # ibench +- name: [vpaddd, vpaddq] # ibench operands: # ibench - class: register # ibench name: ymm # ibench @@ -3736,7 +3736,7 @@ instruction_forms: port_pressure: [[1, '015']] # ibench throughput: 0.3333333333333333 # ibench uops: 1 # ibench -- name: vpaddd # ibench +- name: [vpaddd, vpaddq] # ibench operands: # ibench - class: register # ibench name: zmm # ibench @@ -3748,7 +3748,7 @@ instruction_forms: port_pressure: [[1, '05']] # ibench throughput: 0.5 # ibench uops: 1 # ibench -- name: vpaddd # ibench +- name: [vpaddd, vpaddq] # ibench operands: # ibench - class: register # ibench name: xmm # ibench @@ -3761,7 +3761,7 @@ instruction_forms: port_pressure: [[1, '015']] # ibench throughput: 0.3333333333333333 # ibench uops: 1 # ibench -- name: vpaddd # ibench +- name: [vpaddd, vpaddq] # ibench operands: # ibench - class: register # ibench name: ymm # ibench @@ -3774,7 +3774,7 @@ instruction_forms: port_pressure: [[1, '015']] # ibench throughput: 0.3333333333333333 # ibench uops: 1 # ibench -- name: vpaddd # ibench +- name: [vpaddd, vpaddq] # ibench operands: # ibench - class: register # ibench name: zmm # ibench @@ -4079,6 +4079,15 @@ instruction_forms: port_pressure: [[1, ['0','1','5','6','11']]] throughput: 0.20 uops: 1 +- name: vcvtdq2pd # uops.info + operands: # uops.info + - class: register # uops.info + name: ymm # uops.info + - class: register # uops.info + name: zmm # uops.info + latency: 7 # uops.info + port_pressure: [[1, '0'], [1, '5']] # uops.info + throughput: 1 # uops.info - name: vcvtss2si # uops.info operands: # uops.info - class: register # uops.info @@ -4258,7 +4267,7 @@ instruction_forms: throughput: 0.5 # uops.info uops: 1 # uops.info ############## || ################# -############## \/ assumed from ICX ################# +############## \/ assumed from ICX ################# - name: vinsertf128 operands: - class: immediate @@ -4413,6 +4422,28 @@ instruction_forms: port_pressure: [[1, '5']] throughput: 1.0 uops: 1 +- name: vcvtsi2sd + operands: + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01'], [1, '5']] + throughput: 1.0 + uops: 3 +- name: vcvtdq2pd + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '01'], [1, '5']] + throughput: 1.0 + uops: 2 - name: vcvtsi2ss operands: - class: register @@ -4421,9 +4452,9 @@ instruction_forms: name: xmm - class: register name: xmm - latency: 2 - port_pressure: [[1, '01'], [2, '5']] - throughput: 2.0 + latency: 4 + port_pressure: [[1, '01'], [1, '5']] + throughput: 1.0 uops: 3 - name: [vextractf128, vextracti128] operands: @@ -4599,6 +4630,20 @@ instruction_forms: port_pressure: [[1, '5']] # uops.info throughput: 1.0 # uops.info uops: 1 # uops.info +- name: vpinsrd # asmbench + operands: # asmbench + - class: immediate # asmbench + imd: int # asmbench + - class: register # asmbench + name: gpr # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '15'], [1, '1']] # asmbench + throughput: 1.0 # asmbench + uops: 2 # asmbench - name: vpalignr # asmbench operands: # asmbench - class: immediate # asmbench @@ -4725,7 +4770,7 @@ instruction_forms: port_pressure: [[1, '5']] # asmbench throughput: 1.0 # asmbench uops: 1 # asmbench -- name: vpermd # asmbench +- name: [vpermd, vpermt2q] # asmbench operands: # asmbench - class: register # asmbench name: zmm # asmbench @@ -4737,7 +4782,7 @@ instruction_forms: port_pressure: [[1, '5']] # asmbench throughput: 1.0 # asmbench uops: 1 # asmbench -- name: vpermd # asmbench +- name: [vpermd, vpermt2q] # asmbench operands: # asmbench - class: register # asmbench name: zmm # asmbench @@ -4800,6 +4845,156 @@ instruction_forms: port_pressure: [[1, '5']] # asmbench throughput: 1.0 # asmbench uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: immediate + imd: int + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: immediate + imd: int + - class: register # asmbench + name: xmm # asmbench + - class: register # asmbench + name: xmm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: immediate + imd: int + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: immediate + imd: int + - class: register # asmbench + name: ymm # asmbench + - class: register # asmbench + name: ymm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: immediate + imd: int + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench +- name: [vpermilpd, vpermilps] # asmbench + operands: # asmbench + - class: immediate + imd: int + - class: register # asmbench + name: zmm # asmbench + - class: register # asmbench + name: zmm # asmbench + mask: True # asmbench + latency: 1 # asmbench + port_pressure: [[1, '5']] # asmbench + throughput: 1.0 # asmbench + uops: 1 # asmbench - name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench operands: # asmbench - class: register # asmbench @@ -5002,180 +5197,180 @@ instruction_forms: port_pressure: [[1, '05']] # uops.info throughput: 0.5 # uops.info uops: 1 # uops.info -- name: VCMPPS - operands: - - class: immediate - imd: int - - class: register - name: xmm - - class: register - name: xmm - - class: register - name: xmm - latency: 4 - port_pressure: [[1, '01']] - throughput: 0.5 - uops: 1 -- name: VCMPPS - operands: - - class: immediate - imd: int - - class: register - name: ymm - - class: register - name: ymm - - class: register - name: ymm - latency: 4 - port_pressure: [[1, '01']] - throughput: 0.5 - uops: 1 -- name: VCMPPD - operands: - - class: immediate - imd: int - - class: register - name: xmm - - class: register - name: xmm - - class: register - name: xmm - latency: 4 - port_pressure: [[1, '01']] - throughput: 0.5 - uops: 1 -- name: VCMPPD - operands: - - class: immediate - imd: int - - class: register - name: ymm - - class: register - name: ymm - - class: register - name: ymm - latency: 4 - port_pressure: [[1, '01']] - throughput: 0.5 - uops: 1 -- name: VCMPPS - operands: - - class: immediate - imd: int - - class: register - name: zmm - - class: register - name: zmm - - class: register - name: k - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: VCMPPS - operands: - - class: immediate - imd: int - - class: register - name: zmm - - class: register - name: zmm - - class: register - name: k - mask: True - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: VCMPPS - operands: - - class: immediate - imd: int - - class: register - name: xmm - - class: register - name: xmm - - class: register - name: k - mask: True - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: VCMPPS - operands: - - class: immediate - imd: int - - class: register - name: ymm - - class: register - name: ymm - - class: register +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register name: k - mask: True - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: VCMPPD - operands: - - class: immediate - imd: int - - class: register - name: zmm - - class: register - name: zmm - - class: register - name: k - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: VCMPPD - operands: - - class: immediate - imd: int - - class: register - name: zmm - - class: register - name: zmm - - class: register - name: k mask: True - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: VCMPPD - operands: - - class: immediate - imd: int - - class: register - name: xmm - - class: register - name: xmm - - class: register - name: k + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k mask: True - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: VCMPPD - operands: - - class: immediate - imd: int - - class: register - name: ymm - - class: register - name: ymm - - class: register - name: k + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k mask: True - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: True + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: True + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: True + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 - name: vpunpckhqdq operands: - class: register @@ -5215,203 +5410,213 @@ instruction_forms: ########### /\ ########## ########### || assumed from ICX ########## -- name: AND - operands: - - class: immediate - imd: int - - class: register - name: gpr - latency: 1 - port_pressure: [[1, ['0','1','5','6','11']]] - throughput: 0.20 - uops: 1 -- name: RET - operands: [] - latency: 0 - port_pressure: [[1, '49'], [1, '78']] - throughput: 0.5 - uops: 2 -- name: CALL - operands: - - class: identifier - latency: 0 - port_pressure: [[1, '49'], [1, '78']] - throughput: 0.5 - uops: 2 -- name: TEST - operands: - - class: immediate - imd: int - - class: register - name: gpr - latency: 1 - port_pressure: [[1, ['0','1','5','6','11']]] - throughput: 0.20 - uops: 1 -- name: TEST - operands: - - class: register - name: gpr - - class: register - name: gpr - latency: 1 - port_pressure: [[1, ['0','1','5','6','11']]] +- name: AND + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] throughput: 0.20 - uops: 1 -- name: PTEST - operands: - - class: register - name: xmm - - class: register - name: xmm - latency: 4 - port_pressure: [[1, '0'], [1, '5']] - throughput: 1.0 - uops: 2 -- name: VPTEST - operands: - - class: register - name: xmm - - class: register - name: xmm - latency: 4 - port_pressure: [[1, '0'], [1, '5']] - throughput: 1.0 - uops: 2 -- name: VPTEST - operands: - - class: register - name: ymm - - class: register - name: ymm - latency: 6 - port_pressure: [[1, '0'], [1, '5']] - throughput: 1.0 - uops: 2 + uops: 1 +- name: RET + operands: [] + latency: 0 + port_pressure: [[1, '49'], [1, '78']] + throughput: 0.5 + uops: 2 +- name: CALL + operands: + - class: identifier + latency: 0 + port_pressure: [[1, '49'], [1, '78']] + throughput: 0.5 + uops: 2 +- name: TEST + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: TEST + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 0.20 + uops: 1 +- name: PTEST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPTEST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPTEST + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 - name: [VTESTPD, VTESTPS] - operands: - - class: register - name: xmm - - class: register - name: xmm - latency: 3 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 port_pressure: [[1, '0']] - throughput: 1.0 - uops: 1 + throughput: 1.0 + uops: 1 - name: [VTESTPD, VTESTPS] - operands: - - class: register - name: ymm - - class: register - name: ymm - latency: 5 + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 5 port_pressure: [[1, '0']] - throughput: 1.0 - uops: 1 -- name: VXORPD - operands: - - class: register - name: xmm - - class: register - name: xmm - - class: register - name: xmm - latency: 1 - port_pressure: [[1, ['0','1','5','6','11']]] + throughput: 1.0 + uops: 1 +- name: VXORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] throughput: 0.20 - uops: 1 -- name: VXORPD - operands: - - class: register - name: ymm - - class: register - name: ymm - - class: register - name: ymm - latency: 1 - port_pressure: [[1, ['0','1','5','6','11']]] + uops: 1 +- name: VXORPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] throughput: 0.20 - uops: 1 -- name: VXORPS - operands: - - class: register - name: xmm - - class: register - name: xmm - - class: register - name: xmm - latency: 1 - port_pressure: [[1, ['0','1','5','6','11']]] + uops: 1 +- name: VXORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] throughput: 0.20 - uops: 1 -- name: VXORPS - operands: - - class: register - name: ymm - - class: register - name: ymm - - class: register - name: ymm - latency: 1 - port_pressure: [[1, ['0','1','5','6','11']]] + uops: 1 +- name: VXORPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, ['0','1','5','6','11']]] throughput: 0.20 - uops: 1 -- name: VBROADCASTSS - operands: - - class: register - name: xmm - - class: register - name: xmm - latency: 1 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: [VBROADCASTSD, VBROADCASTSS] - operands: - - class: register - name: xmm - - class: register - name: ymm - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: [VBROADCASTSD, VBROADCASTSS] - operands: - - class: register - name: xmm - - class: register - name: zmm - latency: 3 - port_pressure: [[1, '5']] - throughput: 1.0 - uops: 1 -- name: [VBROADCASTSD, VBROADCASTSS] - operands: + uops: 1 +- name: VPBROADCASTD + operands: + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: [VBROADCASTSD, VBROADCASTSS] + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: [VBROADCASTSD, VBROADCASTSS] + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: [VBROADCASTSD, VBROADCASTSS] + operands: - class: memory base: "*" offset: "*" index: "*" scale: "*" - - class: register - name: ymm - latency: 5 - port_pressure: [[1, '23'], [1, ['2D', '3D']], [1, '015']] - throughput: 1.0 - uops: 1 -- name: [VBROADCASTSD, VBROADCASTSS] - operands: + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '23'], [1, ['2D', '3D']], [1, '015']] + throughput: 1.0 + uops: 1 +- name: [VBROADCASTSD, VBROADCASTSS] + operands: - class: memory base: "*" offset: "*" index: "*" scale: "*" - - class: register - name: zmm - latency: 5 - port_pressure: [[1, '23'], [1, ['2D', '3D']], [1, '015']] - throughput: 1.0 - uops: 1 + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '23'], [1, ['2D', '3D']], [1, '015']] + throughput: 1.0 + uops: 1 - name: vandpd operands: - class: register @@ -5462,3 +5667,71 @@ instruction_forms: port_pressure: [[1, '5']] throughput: 1.0 uops: 1 +- name: vmovd + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] + throughput: 0.2 + uops: 1.0 +- name: vmov + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] + throughput: 0.2 + uops: 1.0 +- name: [vpor, vpxor, vpord, vpxord] + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333 + uops: 1 +- name: [vpor, vpxor, vpord, vpxord] + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333 + uops: 1 +- name: [vpor, vpxor, vpord, vpxord] + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: [kxorb, kxorw, kxord, kxorq, kxnorb, kxnorw, kxnord, kxnorq] + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 diff --git a/osaca/data/v2.yml b/osaca/data/v2.yml index f7e8352..82e0c7d 100644 --- a/osaca/data/v2.yml +++ b/osaca/data/v2.yml @@ -9,11 +9,17 @@ hidden_loads: false load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 7.0, s: 6.0, d: 6.0, q: 6.0, v: 6.0, z: 6.0} p_index_latency: 1 load_throughput: +- {dst: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, ['12', '13', '14']]]} +- {dst: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '2367'], [1, ['12', '13', '14']]]} +- {dst: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '2367'], [1, ['12', '13', '14']]]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, ['12', '13', '14']]]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '2367'], [1, ['12', '13', '14']]]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '2367'], [1, ['12', '13', '14']]]} load_throughput_default: [[1, ['12', '13', '14']]] store_throughput: +- {src: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, ['12', '13']], [1, ['15', '16']]]} +- {src: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '2367'], [1, ['12', '13']], [1, ['15', '16']]]} +- {src: 'z', base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '2367'], [1, ['12', '13']], [1, ['15', '16']]]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, ['12', '13']], [1, ['15', '16']]]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '2367'], [1, ['12', '13']], [1, ['15', '16']]]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '2367'], [1, ['12', '13']], [1, ['15', '16']]]} @@ -25,18 +31,18 @@ port_model_scheme: | +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ 0 |BR0 1 |BR1 2 |ISC0 3 |ISC1 4 |ISC2 5 |ISC3 6 |IMC0 7 |IMC1 8 |FP0 9 |FP1 10 |FP2 11 |FP3 12 |LDST 13 |LDST 14 |LD 15 |ST 16 |ST \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ - +----+ +----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ +----+ +-------+ +----+ +-------+ +-------+ +----+ +-------+ +-----+ +-----+ +-----+ +-----+ +-----+ - | BR | | BR | | ALU | | ALU | | ALU | | ALU | | ALU | | DV | | ALU | | DV | |SIMD/FP| |FPDV| |SIMD/FP| |SIMD/FP| |FPDV| |SIMD/FP| | LD | | LD | | LD | | ST | | ST | - +----+ +----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ +----+ | ALU | +----+ | ALU | | ALU | +----+ | ALU | +-----+ +-----+ +-----+ +-----+ +-----+ - silly silly +------+ +------+ +-------+ +-------+ +-------+ +-------+ +-----+ +-----+ - | MUL | | MUL | +-------+ +-------+ +-------+ +-------+ | AGU | | AGU | - +------+ +------+ |SIMD/FP| |SIMD/FP| |SIMD/FP| |SIMD/FP| +-----+ +-----+ - +------+ +------+ | MISC | | MISC | | MISC | | MISC | - | CRC | | CRC | +-------+ +-------+ +-------+ +-------+ - +------+ +------+ +-------+ +-------+ +-------+ +-------+ - +------+ +------+ | SIMD | | SIMD | | SIMD | | SIMD | - | SHIFT| | SHIFT| |INT MUL| | SHIFT| |INT MUL| | SHIFT| - +------+ +------+ +-------+ +-------+ +-------+ +-------+ + +----+ +----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ +----+ +-------+ +----+ +-------+ +-------+ +----+ +-------+ +-----+ +-----+ +-----+ +-----+ +-----+ + | BR | | BR | | ALU | | ALU | | ALU | | ALU | | ALU | | DV | | ALU | | DV | |SIMD/FP| |FPDV| |SIMD/FP| |SIMD/FP| |FPDV| |SIMD/FP| | LD | | LD | | LD | | ST | | ST | + +----+ +----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ +----+ | ALU | +----+ | ALU | | ALU | +----+ | ALU | +-----+ +-----+ +-----+ +-----+ +-----+ + silly silly +------+ +------+ +-------+ +-------+ +-------+ +-------+ +-----+ +-----+ + | MUL | | MUL | +-------+ +-------+ +-------+ +-------+ | AGU | | AGU | + +------+ +------+ |SIMD/FP| |SIMD/FP| |SIMD/FP| |SIMD/FP| +-----+ +-----+ + +------+ +------+ | MISC | | MISC | | MISC | | MISC | + | CRC | | CRC | +-------+ +-------+ +-------+ +-------+ + +------+ +------+ +-------+ +-------+ +-------+ +-------+ + +------+ +------+ | SIMD | | SIMD | | SIMD | | SIMD | + | SHIFT| | SHIFT| |INT MUL| | SHIFT| |INT MUL| | SHIFT| + +------+ +------+ +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ | FPconv| | ST | | FPconv| +-------+ +-------+ +-------+ @@ -116,7 +122,7 @@ instruction_forms: - name: adds operands: - class: register - prefix: '*' + prefix: '*' - class: register prefix: '*' - class: register @@ -127,7 +133,7 @@ instruction_forms: - name: adds operands: - class: register - prefix: '*' + prefix: '*' - class: register prefix: '*' - class: immediate @@ -138,7 +144,7 @@ instruction_forms: - name: adr operands: - class: register - prefix: '*' + prefix: '*' - class: identifier throughput: 0.25 latency: ~ # 1*p67 @@ -1520,7 +1526,7 @@ instruction_forms: throughput: 0.0 latency: 0 # 0*p port_pressure: [] -- name: [orn, orr] +- name: [orn, orr] operands: - class: register prefix: x @@ -1531,7 +1537,7 @@ instruction_forms: throughput: 0.1666666 latency: 1.0 # 1*234567 port_pressure: [[1, '234567']] -- name: [orn, orr] +- name: [orn, orr] operands: - class: register prefix: x @@ -1542,7 +1548,7 @@ instruction_forms: throughput: 0.25 latency: 1.0 # 1*p2367 port_pressure: [[1, '2367']] -- name: [orn, orr] +- name: [orn, orr] operands: - class: register prefix: w @@ -1553,7 +1559,7 @@ instruction_forms: throughput: 0.1666666 latency: 1.0 # 1*p234567 port_pressure: [[1, '234567']] -- name: [orn, orr] +- name: [orn, orr] operands: - class: register prefix: w @@ -1595,8 +1601,8 @@ instruction_forms: latency: ~ port_pressure: [] - name: ret - operands: - - class: identifier + operands: + - class: identifier throughput: 0.0 latency: ~ port_pressure: [] @@ -1662,7 +1668,7 @@ instruction_forms: - name: [scvtf, ucvtf] operands: - class: register - prefix: s + prefix: s - class: register prefix: w throughput: 1.0 @@ -1671,7 +1677,16 @@ instruction_forms: - name: [scvtf, ucvtf] operands: - class: register - prefix: d + prefix: d + - class: register + prefix: w + throughput: 1.0 + latency: 3.0 # 1*p6 + port_pressure: [[1, '6']] +- name: [scvtf, ucvtf] + operands: + - class: register + prefix: d - class: register prefix: x throughput: 1.0 @@ -1680,7 +1695,7 @@ instruction_forms: - name: [scvtf, ucvtf] operands: - class: register - prefix: d + prefix: d - class: register prefix: x - class: immediate @@ -1691,7 +1706,7 @@ instruction_forms: - name: [scvtf, ucvtf] operands: - class: register - prefix: s + prefix: s - class: register prefix: w - class: immediate @@ -1719,6 +1734,8 @@ instruction_forms: - class: register prefix: w throughput: 5.0 + latency: 5.0 # 2*p67DV + port_pressure: [[1, '67'], [10, ['6DV', '7DV']]] - name: [smaddl, smsubl, umaddl, umsubl] operands: - class: register @@ -1778,7 +1795,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*12,13+1*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -1792,7 +1809,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+1*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -1806,7 +1823,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1+2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -1820,7 +1837,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1+2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -1834,7 +1851,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1+2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -1848,7 +1865,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1+2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1864,7 +1881,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+1*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1880,7 +1897,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+1*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1896,7 +1913,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1912,7 +1929,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1928,7 +1945,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1944,7 +1961,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1960,7 +1977,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1976,7 +1993,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+1*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -1992,7 +2009,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2008,7 +2025,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2024,7 +2041,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2040,7 +2057,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2056,7 +2073,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+1*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2072,7 +2089,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+1*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2088,7 +2105,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2104,7 +2121,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2120,7 +2137,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2136,7 +2153,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+1*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2152,7 +2169,7 @@ instruction_forms: pre-indexed: false throughput: 1.0 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2168,7 +2185,7 @@ instruction_forms: pre-indexed: false throughput: 1.0 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2184,7 +2201,7 @@ instruction_forms: pre-indexed: false throughput: 1.0 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2200,7 +2217,7 @@ instruction_forms: pre-indexed: false throughput: 1.0 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2216,7 +2233,7 @@ instruction_forms: pre-indexed: true throughput: 1.0 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2232,7 +2249,7 @@ instruction_forms: pre-indexed: true throughput: 1.0 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2248,7 +2265,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2264,7 +2281,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2280,7 +2297,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2296,7 +2313,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2312,7 +2329,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -2322,7 +2339,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -2332,7 +2349,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -2342,7 +2359,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -2352,7 +2369,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -2362,7 +2379,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: [str, stur] operands: - class: register @@ -2372,7 +2389,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2384,7 +2401,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2396,7 +2413,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2408,7 +2425,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2420,7 +2437,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2432,7 +2449,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2444,7 +2461,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2456,7 +2473,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2468,7 +2485,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2480,7 +2497,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2492,7 +2509,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2504,7 +2521,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2516,7 +2533,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2528,7 +2545,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2540,7 +2557,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2552,7 +2569,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2564,7 +2581,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2576,7 +2593,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [1, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [1, ['15','16']]] - name: stp operands: - class: register @@ -2588,7 +2605,7 @@ instruction_forms: pre-indexed: false throughput: 1.0 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2600,7 +2617,7 @@ instruction_forms: pre-indexed: false throughput: 1.0 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2612,7 +2629,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2624,7 +2641,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2636,7 +2653,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p12,13+2*p15,16 - port_pressure: [[1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2648,7 +2665,7 @@ instruction_forms: pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2660,7 +2677,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: stp operands: - class: register @@ -2676,7 +2693,7 @@ instruction_forms: pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p2367+1*p12,13+2*p15,16 - port_pressure: [[1, '2367'], [1, ['12','13'], [2, ['15','16']]]] + port_pressure: [[1, '2367'], [1, ['12','13']], [2, ['15','16']]] - name: sub operands: - class: register @@ -2780,9 +2797,9 @@ instruction_forms: prefix: "*" - class: register prefix: "*" - - class: immediate + - class: immediate imd: int - - class: immediate + - class: immediate imd: int throughput: 0.25 latency: 1.0 # 1*p2367 @@ -2823,7 +2840,22 @@ instruction_forms: shape: '*' width: '*' - class: immediate - imd: int + imd: '*' + throughput: 0.25 + latency: 2.0 # 1*p8,9,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: fadd + operands: + - class: register + prefix: '*' + shape: '*' + width: '*' + - class: register + prefix: '*' + shape: '*' + width: '*' + - class: immediate + imd: '*' throughput: 0.25 latency: 2.0 # 1*p8,9,10,11 port_pressure: [[1, ['8', '9', '10', '11']]] @@ -2860,8 +2892,8 @@ instruction_forms: - class: register prefix: s - class: immediate - imd: int - - class: condition + imd: '*' + - class: condition ccode: "*" throughput: 1.0 latency: 1.0 # 1*p8 @@ -2928,7 +2960,7 @@ instruction_forms: shape: d width: '*' throughput: 5.0 - latency: 12.0 # 1*p67 + latency: 12.0 # 1*p8,10 port_pressure: [[1, ['8', '10']], [5, ['8DV', '10DV']]] - name: fdiv operands: @@ -4162,7 +4194,7 @@ instruction_forms: post-indexed: false throughput: 1.0 latency: 6.0 # 1*p12,13,14 - port_pressure: [[3, ['12', '13', '14']]] + port_pressure: [[1, ['12', '13', '14']]] - name: [ld1d, ld1sw, ld1sh, ld1sb] operands: - class: register @@ -4180,7 +4212,7 @@ instruction_forms: post-indexed: false throughput: 1.0 latency: 6.0 # 1*p12,13,14 - port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] + port_pressure: [[1, ['8','9','10','11']], [1, ['12', '13', '14']]] - name: [ld1d, ld1sw, ld1sh, ld1sb] operands: - class: register @@ -4198,7 +4230,7 @@ instruction_forms: post-indexed: true throughput: 1.0 latency: 6.0 # 1*p12,13,14 - port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] + port_pressure: [[1, ['8','9','10','11']], [1, ['12', '13', '14']]] - name: [ld1d, ld1w, ld1h, ld1b] # gather operands: - class: register @@ -4216,7 +4248,7 @@ instruction_forms: post-indexed: false throughput: 1.0 latency: 9.0 # 1*p12,13,14 - port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] + port_pressure: [[1, ['8','9','10','11']], [1, ['12', '13', '14']]] - name: [ld1d, ld1w, ld1h, ld1b] # gather operands: - class: register @@ -4234,7 +4266,7 @@ instruction_forms: post-indexed: false throughput: 1.0 latency: 9.0 # 1*p12,13,14 - port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] + port_pressure: [[1, ['8','9','10','11']], [1, ['12', '13', '14']]] - name: [ld1d, ld1w, ld1h, ld1b] # gather operands: - class: register @@ -4252,15 +4284,15 @@ instruction_forms: post-indexed: true throughput: 1.0 latency: 9.0 # 1*p12,13,14 - port_pressure: [[1, ['8','9','10','11']], [3, ['12', '13', '14']]] + port_pressure: [[1, ['8','9','10','11']], [1, ['12', '13', '14']]] - name: [ld2d, ld2w, ld2h, ld2b] operands: - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register prefix: p predication: '*' @@ -4277,11 +4309,11 @@ instruction_forms: - name: [ld2d, ld2w, ld2h, ld2b] operands: - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register prefix: p predication: '*' @@ -4298,11 +4330,11 @@ instruction_forms: - name: [ld2d, ld2w, ld2h, ld2b] operands: - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register prefix: p predication: '*' @@ -4319,11 +4351,11 @@ instruction_forms: - name: [ld3d, ld3w, ld3h, ld3b] operands: - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register prefix: p predication: '*' @@ -4340,11 +4372,11 @@ instruction_forms: - name: [ld3d, ld3w, ld3h, ld3b] operands: - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register prefix: p predication: '*' @@ -4361,11 +4393,11 @@ instruction_forms: - name: [ld3d, ld3w, ld3h, ld3b] operands: - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register prefix: p predication: '*' @@ -4486,15 +4518,15 @@ instruction_forms: post-indexed: false throughput: 1.0 latency: 0 # 2*p89+2*p12,13 - port_pressure: [[2, '89'], [1, ['12','13']]] + port_pressure: [[2, ['15','16']], [1, ['12','13']]] - name: [st2d, st2w, st2b, st2h] operands: - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register prefix: p predication: '*' @@ -4507,15 +4539,15 @@ instruction_forms: post-indexed: false throughput: 2.0 latency: 0 # 2*p89+2*p12,13 - port_pressure: [[2, '89'], [1, ['12','13']]] + port_pressure: [[2, ['15','16']], [1, ['12','13']]] - name: [st3d, st3w, st3b, st3h] operands: - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register - prefix: 'z' - shape: 'd' + prefix: z + shape: d - class: register prefix: p predication: '*' @@ -4528,7 +4560,7 @@ instruction_forms: post-indexed: false throughput: 2.0 latency: 0 # 2*p89+2*p12,13 - port_pressure: [[4, '89'], [1, ['12','13']]] + port_pressure: [[4, ['15','16']], [1, ['12','13']]] - name: tbl operands: - class: register @@ -4572,7 +4604,7 @@ instruction_forms: throughput: 0.25 latency: 2.0 # 2*p89,10,11 port_pressure: [[1, ['8','9','10','11']]] -- name: scvtf +- name: [scvtf, ucvtf] operands: - class: register prefix: z @@ -4585,7 +4617,7 @@ instruction_forms: throughput: 1.0 latency: 4.0 port_pressure: [[2, ['8','10']]] -- name: scvtf +- name: [scvtf, ucvtf] operands: - class: register prefix: z @@ -4598,7 +4630,7 @@ instruction_forms: throughput: 2.0 latency: 6.0 port_pressure: [[4, ['8','10']]] -- name: scvtf +- name: [scvtf, ucvtf] operands: - class: register prefix: z @@ -4611,3 +4643,103 @@ instruction_forms: throughput: 0.5 latency: 3.0 port_pressure: [[1, ['8','10']]] +- name: [scvtf, ucvtf] + operands: + - class: register + prefix: z + shape: d + - class: register + prefix: p + - class: register + prefix: z + shape: s + throughput: 0.5 + latency: 3.0 + port_pressure: [[1, ['8','10']]] +- name: [fdiv, fdivr] + operands: + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: p + - class: register + prefix: z + shape: d + width: '*' + - class: register + prefix: z + shape: d + width: '*' + throughput: 3.0 + latency: 7.0 # 1*p8,10 + port_pressure: [[1, ['8', '10']], [6, ['8DV','10DV']]] +- name: fadd + operands: + - class: register + prefix: z + shape: '*' + width: '*' + - class: register + prefix: p + - class: register + prefix: z + shape: '*' + width: '*' + - class: register + prefix: z + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p8,9,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: fadd + operands: + - class: register + prefix: z + shape: '*' + width: '*' + - class: register + prefix: p + - class: register + prefix: z + shape: '*' + width: '*' + - class: immediate + imd: '*' + throughput: 0.25 + latency: 2.0 # 1*p8,9,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: add + operands: + - class: register + prefix: z + shape: '*' + width: '*' + - class: register + prefix: z + shape: '*' + width: '*' + - class: immediate + imd: '*' + throughput: 0.25 + latency: 2.0 # 1*p8,9,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: add + operands: + - class: register + prefix: z + shape: '*' + width: '*' + - class: register + prefix: z + shape: '*' + width: '*' + - class: register + prefix: z + shape: '*' + width: '*' + throughput: 0.25 + latency: 2.0 # 1*p8,9,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] From 5071d63b9ae44154a169208df2f582663fd7b42f Mon Sep 17 00:00:00 2001 From: Jan <20126033+JanLJL@users.noreply.github.com> Date: Thu, 2 May 2024 23:06:12 +0200 Subject: [PATCH 4/7] Fixed uarch table layout --- README.rst | 76 +++++++++++++++++++++++++++--------------------------- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/README.rst b/README.rst index bb67b57..10ea35d 100644 --- a/README.rst +++ b/README.rst @@ -142,57 +142,57 @@ Supported microarchitectures ----------------------------- **x86 CPUs** -+----------+----------------+------------+ -| Designer | Model/microarch| OSACA flag | -+==========+================+============+ -| | | Sandy Bridge | ``SNB`` | -| | +----------------+------------+ -| | | Ivy Bridge | ``IVB`` | -| | +----------------+------------+ -| | | Haswell | ``HSW`` | -| | +----------------+------------+ -| | | Broadwell | ``BDW`` | -| | +----------------+------------+ -| | | Skylake-X | ``SKX`` | -| | Intel +----------------+------------+ -| | | Cascadelake-X | ``CSX`` | -| | +----------------+------------+ -| | | Icelake client | ``ICL`` | -| | +----------------+------------+ -| | | Icelake server | ``ICX`` | -| | +----------------+------------+ -| | | Sapphire Rapids| ``SPR`` | -+----------+----------------+------------+ -| | | Naples / Zen 1 | ``ZEN1`` | -| | +----------------+------------+ -| | AMD | Rome / Zen 2 | ``ZEN2`` | -| | +----------------+------------+ -| | | Milan / Zen 3 | ``ZEN3`` | -+----------+----------------+------------+ ++----------+-----------------+------------+ +| Designer | Model/microarch | OSACA flag | ++==========+=================+============+ +| Intel | Sandy Bridge | ``SNB`` | ++----------+-----------------+------------+ +| Intel | Ivy Bridge | ``IVB`` | ++----------+-----------------+------------+ +| Intel | Haswell | ``HSW`` | ++----------+-----------------+------------+ +| Intel | Broadwell | ``BDW`` | ++----------+-----------------+------------+ +| Intel | Skylake-X | ``SKX`` | ++----------+-----------------+------------+ +| Intel | Cascadelake-X | ``CSX`` | ++----------+-----------------+------------+ +| Intel | Icelake client | ``ICL`` | ++----------+-----------------+------------+ +| Intel | Icelake server | ``ICX`` | ++----------+-----------------+------------+ +| Intel | Sapphire Rapids | ``SPR`` | ++----------+-----------------+------------+ +| AMD | Naples / Zen 1 | ``ZEN1`` | ++----------+-----------------+------------+ +| AMD | Rome / Zen 2 | ``ZEN2`` | ++----------+-----------------+------------+ +| AMD | Milan / Zen 3 | ``ZEN3`` | ++----------+-----------------+------------+ **ARM AArch64 CPUs** +-----------+-------------------+-------------+ | Designer | Model/microarch | OSACA flag | +===========+===================+=============+ -| | | Cortex-A72 | ``A72`` | -| | +-------------------+-------------+ -| | ARM | Neoverse N1 | ``N1`` | -| | +-------------------+-------------+ -| | | Neoverse V2 | ``V2`` | +| ARM | Cortex-A72 | ``A72`` | +-----------+-------------------+-------------+ -| Marvell | ThunderX2 | ``TX2`` | +| ARM | Neoverse N1 | ``N1`` | +-----------+-------------------+-------------+ -| Fujitsu | FX700/A64FX | ``A64FX`` | +| ARM | Neoverse V2 | ``V2`` | +-----------+-------------------+-------------+ -| HiSilicon | TaiShan v110 | ``TSV110`` | +| Marvell | ThunderX2 | ``TX2`` | +-----------+-------------------+-------------+ -| Apple | M1-Firestorm | ``M1`` | +| Fujitsu | FX700/A64FX | ``A64FX`` | +-----------+-------------------+-------------+ -| NVIDIA | Neoverse V2/Grace | ``V2`` | +| HiSilicon | TaiShan v110 | ``TSV110`` | ++-----------+-------------------+-------------+ +| Apple | M1-Firestorm | ``M1`` | ++-----------+-------------------+-------------+ +| NVIDIA | Neoverse V2/Grace | ``V2`` | +-----------+-------------------+-------------+ -______________________ +---- Hereinafter OSACA's scope of function will be described. From 8fa31a7fcae396ff90f0f8d25da89881c1eed725 Mon Sep 17 00:00:00 2001 From: JanLJL Date: Fri, 3 May 2024 12:31:25 +0200 Subject: [PATCH 5/7] formatting --- osaca/data/generate_mov_entries.py | 365 ++++++++++++++--------------- 1 file changed, 182 insertions(+), 183 deletions(-) diff --git a/osaca/data/generate_mov_entries.py b/osaca/data/generate_mov_entries.py index 7ffb9cf..96308bd 100644 --- a/osaca/data/generate_mov_entries.py +++ b/osaca/data/generate_mov_entries.py @@ -9,7 +9,7 @@ class MOVEntryBuilder: port_occupancy = defaultdict(Fraction) for uops, ports in port_pressure: for p in ports: - port_occupancy[p] += Fraction(int(uops*100), len(ports)*100) + port_occupancy[p] += Fraction(int(uops * 100), len(ports) * 100) return float(max(list(port_occupancy.values()) + [0])) @staticmethod @@ -121,17 +121,17 @@ class MOVEntryBuilderIntelPort11(MOVEntryBuilder): load, store, vec = self.classify(operand_types) if load: - if 'zmm' in operand_types: - port_pressure += [[1.5, ["2","3", "10"]]] + if "zmm" in operand_types: + port_pressure += [[1.5, ["2", "3", "10"]]] else: - port_pressure += [[1, ["2","3","10"]]] + port_pressure += [[1, ["2", "3", "10"]]] latency += 5 comment = "with load" return MOVEntryBuilder.build_description( self, instruction_name, operand_types, port_pressure, latency, comment ) if store: - if 'zmm' in operand_types: + if "zmm" in operand_types: port_pressure += [[2, "78"], [2, "49"]] else: port_pressure += [[1, "78"], [1, "49"]] @@ -1020,41 +1020,41 @@ spr_mov_instructions = [ ("vmovaps zmm mem", ("", 0)), ("vmovaps mem zmm", ("", 0)), ## https://www.felixcloutier.com/x86/movd:movq - #("movd gpr mm", ("1*p5", 1)), - #("movd mem mm", ("", 0)), - #("movq gpr mm", ("1*p5", 1)), - #("movq mem mm", ("", 0)), - #("movd mm gpr", ("1*p0", 1)), - #("movd mm mem", ("", 0)), - #("movq mm gpr", ("1*p0", 1)), - #("movq mm mem", ("", 0)), - #("movd gpr xmm", ("1*p5", 1)), - #("movd mem xmm", ("", 0)), - #("movq gpr xmm", ("1*p5", 1)), - #("movq mem xmm", ("", 0)), - #("movd xmm gpr", ("1*p0", 1)), - #("movd xmm mem", ("", 0)), - #("movq xmm gpr", ("1*p0", 1)), - #("movq xmm mem", ("", 0)), - #("vmovd gpr xmm", ("1*p5", 1)), - #("vmovd mem xmm", ("", 0)), - #("vmovq gpr xmm", ("1*p5", 1)), - #("vmovq mem xmm", ("", 0)), - #("vmovd xmm gpr", ("1*p0", 1)), - #("vmovd xmm mem", ("", 0)), - #("vmovq xmm gpr", ("1*p0", 1)), - #("vmovq xmm mem", ("", 0)), + # ("movd gpr mm", ("1*p5", 1)), + # ("movd mem mm", ("", 0)), + # ("movq gpr mm", ("1*p5", 1)), + # ("movq mem mm", ("", 0)), + # ("movd mm gpr", ("1*p0", 1)), + # ("movd mm mem", ("", 0)), + # ("movq mm gpr", ("1*p0", 1)), + # ("movq mm mem", ("", 0)), + # ("movd gpr xmm", ("1*p5", 1)), + # ("movd mem xmm", ("", 0)), + # ("movq gpr xmm", ("1*p5", 1)), + # ("movq mem xmm", ("", 0)), + # ("movd xmm gpr", ("1*p0", 1)), + # ("movd xmm mem", ("", 0)), + # ("movq xmm gpr", ("1*p0", 1)), + # ("movq xmm mem", ("", 0)), + # ("vmovd gpr xmm", ("1*p5", 1)), + # ("vmovd mem xmm", ("", 0)), + # ("vmovq gpr xmm", ("1*p5", 1)), + # ("vmovq mem xmm", ("", 0)), + # ("vmovd xmm gpr", ("1*p0", 1)), + # ("vmovd xmm mem", ("", 0)), + # ("vmovq xmm gpr", ("1*p0", 1)), + # ("vmovq xmm mem", ("", 0)), ## https://www.felixcloutier.com/x86/movddup - #("movddup xmm xmm", ("1*p5", 1)), - #("movddup mem xmm", ("", 0)), - #("vmovddup xmm xmm", ("1*p5", 1)), - #("vmovddup mem xmm", ("", 0)), - #("vmovddup ymm ymm", ("1*p5", 1)), - #("vmovddup mem ymm", ("", 0)), - #("vmovddup zmm zmm", ("1*p5", 1)), - #("vmovddup mem zmm", ("", 0)), + # ("movddup xmm xmm", ("1*p5", 1)), + # ("movddup mem xmm", ("", 0)), + # ("vmovddup xmm xmm", ("1*p5", 1)), + # ("vmovddup mem xmm", ("", 0)), + # ("vmovddup ymm ymm", ("1*p5", 1)), + # ("vmovddup mem ymm", ("", 0)), + # ("vmovddup zmm zmm", ("1*p5", 1)), + # ("vmovddup mem zmm", ("", 0)), # https://www.felixcloutier.com/x86/movdq2q - #("movdq2q xmm mm", ("1*p015+1*p5", 1)), + # ("movdq2q xmm mm", ("1*p015+1*p5", 1)), # https://www.felixcloutier.com/x86/movdqa:vmovdqa32:vmovdqa64 ("movdqa xmm xmm", ("1*p0,1,5,6,10", 1)), ("movdqa mem xmm", ("", 0)), @@ -1130,39 +1130,39 @@ spr_mov_instructions = [ ("vmovdqu64 mem zmm", ("", 0)), ("vmovdqu64 zmm mem", ("", 0)), ## https://www.felixcloutier.com/x86/movhlps - #("movhlps xmm xmm", ("1*p5", 1)), - #("vmovhlps xmm xmm xmm", ("1*p5", 1)), + # ("movhlps xmm xmm", ("1*p5", 1)), + # ("vmovhlps xmm xmm xmm", ("1*p5", 1)), ## https://www.felixcloutier.com/x86/movhpd - #("movhpd mem xmm", ("1*p5", 1)), - #("vmovhpd mem xmm xmm", ("1*p5", 1)), - #("movhpd xmm mem", ("", 0)), - #("vmovhpd mem xmm", ("", 0)), + # ("movhpd mem xmm", ("1*p5", 1)), + # ("vmovhpd mem xmm xmm", ("1*p5", 1)), + # ("movhpd xmm mem", ("", 0)), + # ("vmovhpd mem xmm", ("", 0)), ## https://www.felixcloutier.com/x86/movhps - #("movhps mem xmm", ("1*p5", 1)), - #("vmovhps mem xmm xmm", ("1*p5", 1)), - #("movhps xmm mem", ("", 0)), - #("vmovhps mem xmm", ("", 0)), + # ("movhps mem xmm", ("1*p5", 1)), + # ("vmovhps mem xmm xmm", ("1*p5", 1)), + # ("movhps xmm mem", ("", 0)), + # ("vmovhps mem xmm", ("", 0)), ## https://www.felixcloutier.com/x86/movlhps - #("movlhps xmm xmm", ("1*p5", 1)), - #("vmovlhps xmm xmm xmm", ("1*p5", 1)), + # ("movlhps xmm xmm", ("1*p5", 1)), + # ("vmovlhps xmm xmm xmm", ("1*p5", 1)), ## https://www.felixcloutier.com/x86/movlpd - #("movlpd mem xmm", ("1*p5", 1)), - #("vmovlpd mem xmm xmm", ("1*p5", 1)), - #("movlpd xmm mem", ("", 0)), - #("vmovlpd mem xmm", ("1*p5", 1)), + # ("movlpd mem xmm", ("1*p5", 1)), + # ("vmovlpd mem xmm xmm", ("1*p5", 1)), + # ("movlpd xmm mem", ("", 0)), + # ("vmovlpd mem xmm", ("1*p5", 1)), ## https://www.felixcloutier.com/x86/movlps - #("movlps mem xmm", ("1*p5", 1)), - #("vmovlps mem xmm xmm", ("1*p5", 1)), - #("movlps xmm mem", ("", 0)), - #("vmovlps mem xmm", ("1*p5", 1)), + # ("movlps mem xmm", ("1*p5", 1)), + # ("vmovlps mem xmm xmm", ("1*p5", 1)), + # ("movlps xmm mem", ("", 0)), + # ("vmovlps mem xmm", ("1*p5", 1)), ## https://www.felixcloutier.com/x86/movmskpd - #("movmskpd xmm gpr", ("1*p0", 1)), - #("vmovmskpd xmm gpr", ("1*p0", 1)), - #("vmovmskpd ymm gpr", ("1*p0", 1)), + # ("movmskpd xmm gpr", ("1*p0", 1)), + # ("vmovmskpd xmm gpr", ("1*p0", 1)), + # ("vmovmskpd ymm gpr", ("1*p0", 1)), ## https://www.felixcloutier.com/x86/movmskps - #("movmskps xmm gpr", ("1*p0", 1)), - #("vmovmskps xmm gpr", ("1*p0", 1)), - #("vmovmskps ymm gpr", ("1*p0", 1)), + # ("movmskps xmm gpr", ("1*p0", 1)), + # ("vmovmskps xmm gpr", ("1*p0", 1)), + # ("vmovmskps ymm gpr", ("1*p0", 1)), # https://www.felixcloutier.com/x86/movntdq ("movntdq xmm mem", ("", 0)), # TODO NT-store: what latency to use? ("vmovntdq xmm mem", ("", 0)), # TODO NT-store: what latency to use? @@ -1208,23 +1208,23 @@ spr_mov_instructions = [ ("vmovsd mem xmm", ("", 0)), ("vmovsd xmm mem", ("", 0)), ## https://www.felixcloutier.com/x86/movshdup - #("movshdup xmm xmm", ("1*p15", 1)), - #("movshdup mem xmm", ("", 0)), - #("vmovshdup xmm xmm", ("1*p15", 1)), - #("vmovshdup mem xmm", ("", 0)), - #("vmovshdup ymm ymm", ("1*p15", 1)), - #("vmovshdup mem ymm", ("", 0)), - #("vmovshdup zmm zmm", ("1*p5", 1)), - #("vmovshdup mem zmm", ("", 0)), + # ("movshdup xmm xmm", ("1*p15", 1)), + # ("movshdup mem xmm", ("", 0)), + # ("vmovshdup xmm xmm", ("1*p15", 1)), + # ("vmovshdup mem xmm", ("", 0)), + # ("vmovshdup ymm ymm", ("1*p15", 1)), + # ("vmovshdup mem ymm", ("", 0)), + # ("vmovshdup zmm zmm", ("1*p5", 1)), + # ("vmovshdup mem zmm", ("", 0)), ## https://www.felixcloutier.com/x86/movsldup - #("movsldup xmm xmm", ("1*p15", 1)), - #("movsldup mem xmm", ("", 0)), - #("vmovsldup xmm xmm", ("1*p15", 1)), - #("vmovsldup mem xmm", ("", 0)), - #("vmovsldup ymm ymm", ("1*p15", 1)), - #("vmovsldup mem ymm", ("", 0)), - #("vmovsldup zmm zmm", ("1*p5", 1)), - #("vmovsldup mem zmm", ("", 0)), + # ("movsldup xmm xmm", ("1*p15", 1)), + # ("movsldup mem xmm", ("", 0)), + # ("vmovsldup xmm xmm", ("1*p15", 1)), + # ("vmovsldup mem xmm", ("", 0)), + # ("vmovsldup ymm ymm", ("1*p15", 1)), + # ("vmovsldup mem ymm", ("", 0)), + # ("vmovsldup zmm zmm", ("1*p5", 1)), + # ("vmovsldup mem zmm", ("", 0)), # https://www.felixcloutier.com/x86/movss ("movss xmm xmm", ("1*p0,1,5,6,10", 1)), ("movss mem xmm", ("", 0)), @@ -1273,113 +1273,113 @@ spr_mov_instructions = [ ("vmovups mem zmm", ("", 0)), ("vmovups zmm mem", ("", 0)), ## https://www.felixcloutier.com/x86/movzx - #("movzx gpr gpr", ("1*p0,1,5,6,10", 1)), - #("movzx mem gpr", ("", 0)), - #("movzb gpr gpr", ("1*p0,1,5,6,10", 1)), # AT&T version - #("movzb mem gpr", ("", 0)), # AT&T version - #("movzw gpr gpr", ("1*p0,1,5,6,106", 1)), # AT&T version - #("movzw mem gpr", ("", 0)), # AT&T version - #("movzl gpr gpr", ("1*p0156", 1)), # AT&T version - #("movzl mem gpr", ("", 0)), # AT&T version - #("movzq gpr gpr", ("1*p0156", 1)), # AT&T version - #("movzq mem gpr", ("", 0)), # AT&T version + # ("movzx gpr gpr", ("1*p0,1,5,6,10", 1)), + # ("movzx mem gpr", ("", 0)), + # ("movzb gpr gpr", ("1*p0,1,5,6,10", 1)), # AT&T version + # ("movzb mem gpr", ("", 0)), # AT&T version + # ("movzw gpr gpr", ("1*p0,1,5,6,106", 1)), # AT&T version + # ("movzw mem gpr", ("", 0)), # AT&T version + # ("movzl gpr gpr", ("1*p0156", 1)), # AT&T version + # ("movzl mem gpr", ("", 0)), # AT&T version + # ("movzq gpr gpr", ("1*p0156", 1)), # AT&T version + # ("movzq mem gpr", ("", 0)), # AT&T version ## https://www.felixcloutier.com/x86/cmovcc - #("cmova gpr gpr", ("2*p06", 1)), - #("cmova mem gpr", ("", 0)), - #("cmovae gpr gpr", ("1*p06", 1)), - #("cmovae mem gpr", ("", 0)), - #("cmovb gpr gpr", ("2*p06", 1)), - #("cmovb mem gpr", ("", 0)), - #("cmovbe gpr gpr", ("2*p06", 1)), - #("cmovbe mem gpr", ("", 0)), - #("cmovc gpr gpr", ("1*p06", 1)), - #("cmovc mem gpr", ("", 0)), - #("cmove gpr gpr", ("1*p06", 1)), - #("cmove mem gpr", ("", 0)), - #("cmovg gpr gpr", ("1*p06", 1)), - #("cmovg mem gpr", ("", 0)), - #("cmovge gpr gpr", ("1*p06", 1)), - #("cmovge mem gpr", ("", 0)), - #("cmovl gpr gpr", ("1*p06", 1)), - #("cmovl mem gpr", ("", 0)), - #("cmovle gpr gpr", ("1*p06", 1)), - #("cmovle mem gpr", ("", 0)), - #("cmovna gpr gpr", ("2*p06", 1)), - #("cmovna mem gpr", ("", 0)), - #("cmovnae gpr gpr", ("1*p06", 1)), - #("cmovnae mem gpr", ("", 0)), - #("cmovnb gpr gpr", ("1*p06", 1)), - #("cmovnb mem gpr", ("", 0)), - #("cmovnbe gpr gpr", ("2*p06", 1)), - #("cmovnbe mem gpr", ("", 0)), - #("cmovnc gpr gpr", ("1*p06", 1)), - #("cmovnc mem gpr", ("", 0)), - #("cmovne gpr gpr", ("1*p06", 1)), - #("cmovne mem gpr", ("", 0)), - #("cmovng gpr gpr", ("1*p06", 1)), - #("cmovng mem gpr", ("", 0)), - #("cmovnge gpr gpr", ("1*p06", 1)), - #("cmovnge mem gpr", ("", 0)), - #("cmovnl gpr gpr", ("1*p06", 1)), - #("cmovnl mem gpr", ("", 0)), - #("cmovno gpr gpr", ("1*p06", 1)), - #("cmovno mem gpr", ("", 0)), - #("cmovnp gpr gpr", ("1*p06", 1)), - #("cmovnp mem gpr", ("", 0)), - #("cmovns gpr gpr", ("1*p06", 1)), - #("cmovns mem gpr", ("", 0)), - #("cmovnz gpr gpr", ("1*p06", 1)), - #("cmovnz mem gpr", ("", 0)), - #("cmovo gpr gpr", ("1*p06", 1)), - #("cmovo mem gpr", ("", 0)), - #("cmovp gpr gpr", ("1*p06", 1)), - #("cmovp mem gpr", ("", 0)), - #("cmovpe gpr gpr", ("1*p06", 1)), - #("cmovpe mem gpr", ("", 0)), - #("cmovpo gpr gpr", ("1*p06", 1)), - #("cmovpo mem gpr", ("", 0)), - #("cmovs gpr gpr", ("1*p06", 1)), - #("cmovs mem gpr", ("", 0)), - #("cmovz gpr gpr", ("1*p06", 1)), - #("cmovz mem gpr", ("", 0)), + # ("cmova gpr gpr", ("2*p06", 1)), + # ("cmova mem gpr", ("", 0)), + # ("cmovae gpr gpr", ("1*p06", 1)), + # ("cmovae mem gpr", ("", 0)), + # ("cmovb gpr gpr", ("2*p06", 1)), + # ("cmovb mem gpr", ("", 0)), + # ("cmovbe gpr gpr", ("2*p06", 1)), + # ("cmovbe mem gpr", ("", 0)), + # ("cmovc gpr gpr", ("1*p06", 1)), + # ("cmovc mem gpr", ("", 0)), + # ("cmove gpr gpr", ("1*p06", 1)), + # ("cmove mem gpr", ("", 0)), + # ("cmovg gpr gpr", ("1*p06", 1)), + # ("cmovg mem gpr", ("", 0)), + # ("cmovge gpr gpr", ("1*p06", 1)), + # ("cmovge mem gpr", ("", 0)), + # ("cmovl gpr gpr", ("1*p06", 1)), + # ("cmovl mem gpr", ("", 0)), + # ("cmovle gpr gpr", ("1*p06", 1)), + # ("cmovle mem gpr", ("", 0)), + # ("cmovna gpr gpr", ("2*p06", 1)), + # ("cmovna mem gpr", ("", 0)), + # ("cmovnae gpr gpr", ("1*p06", 1)), + # ("cmovnae mem gpr", ("", 0)), + # ("cmovnb gpr gpr", ("1*p06", 1)), + # ("cmovnb mem gpr", ("", 0)), + # ("cmovnbe gpr gpr", ("2*p06", 1)), + # ("cmovnbe mem gpr", ("", 0)), + # ("cmovnc gpr gpr", ("1*p06", 1)), + # ("cmovnc mem gpr", ("", 0)), + # ("cmovne gpr gpr", ("1*p06", 1)), + # ("cmovne mem gpr", ("", 0)), + # ("cmovng gpr gpr", ("1*p06", 1)), + # ("cmovng mem gpr", ("", 0)), + # ("cmovnge gpr gpr", ("1*p06", 1)), + # ("cmovnge mem gpr", ("", 0)), + # ("cmovnl gpr gpr", ("1*p06", 1)), + # ("cmovnl mem gpr", ("", 0)), + # ("cmovno gpr gpr", ("1*p06", 1)), + # ("cmovno mem gpr", ("", 0)), + # ("cmovnp gpr gpr", ("1*p06", 1)), + # ("cmovnp mem gpr", ("", 0)), + # ("cmovns gpr gpr", ("1*p06", 1)), + # ("cmovns mem gpr", ("", 0)), + # ("cmovnz gpr gpr", ("1*p06", 1)), + # ("cmovnz mem gpr", ("", 0)), + # ("cmovo gpr gpr", ("1*p06", 1)), + # ("cmovo mem gpr", ("", 0)), + # ("cmovp gpr gpr", ("1*p06", 1)), + # ("cmovp mem gpr", ("", 0)), + # ("cmovpe gpr gpr", ("1*p06", 1)), + # ("cmovpe mem gpr", ("", 0)), + # ("cmovpo gpr gpr", ("1*p06", 1)), + # ("cmovpo mem gpr", ("", 0)), + # ("cmovs gpr gpr", ("1*p06", 1)), + # ("cmovs mem gpr", ("", 0)), + # ("cmovz gpr gpr", ("1*p06", 1)), + # ("cmovz mem gpr", ("", 0)), ## https://www.felixcloutier.com/x86/pmovmskb - #("pmovmskb mm gpr", ("1*p0", 1)), - #("pmovmskb xmm gpr", ("1*p0", 1)), - #("vpmovmskb xmm gpr", ("1*p0", 1)), + # ("pmovmskb mm gpr", ("1*p0", 1)), + # ("pmovmskb xmm gpr", ("1*p0", 1)), + # ("vpmovmskb xmm gpr", ("1*p0", 1)), ## https://www.felixcloutier.com/x86/pmovsx - #("pmovsxbw xmm xmm", ("1*p15", 1)), - #("pmovsxbw mem xmm", ("1*p15", 1)), - #("pmovsxbd xmm xmm", ("1*p15", 1)), - #("pmovsxbd mem xmm", ("1*p15", 1)), - #("pmovsxbq xmm xmm", ("1*p15", 1)), - #("pmovsxbq mem xmm", ("1*p15", 1)), - #("vpmovsxbw xmm xmm", ("1*p15", 1)), - #("vpmovsxbw mem xmm", ("1*p15", 1)), - #("vpmovsxbd xmm xmm", ("1*p15", 1)), - #("vpmovsxbd mem xmm", ("1*p15", 1)), - #("vpmovsxbq xmm xmm", ("1*p15", 1)), - #("vpmovsxbq mem xmm", ("1*p15", 1)), - #("vpmovsxbw xmm ymm", ("1*p5", 1)), - #("vpmovsxbw mem ymm", ("1*p5", 1)), - #("vpmovsxbd xmm ymm", ("1*p5", 1)), - #("vpmovsxbd mem ymm", ("1*p5", 1)), - #("vpmovsxbq xmm ymm", ("1*p5", 1)), - #("vpmovsxbq mem ymm", ("1*p5", 1)), - #("vpmovsxbw ymm zmm", ("1*p5", 3)), - #("vpmovsxbw mem zmm", ("1*p5", 1)), + # ("pmovsxbw xmm xmm", ("1*p15", 1)), + # ("pmovsxbw mem xmm", ("1*p15", 1)), + # ("pmovsxbd xmm xmm", ("1*p15", 1)), + # ("pmovsxbd mem xmm", ("1*p15", 1)), + # ("pmovsxbq xmm xmm", ("1*p15", 1)), + # ("pmovsxbq mem xmm", ("1*p15", 1)), + # ("vpmovsxbw xmm xmm", ("1*p15", 1)), + # ("vpmovsxbw mem xmm", ("1*p15", 1)), + # ("vpmovsxbd xmm xmm", ("1*p15", 1)), + # ("vpmovsxbd mem xmm", ("1*p15", 1)), + # ("vpmovsxbq xmm xmm", ("1*p15", 1)), + # ("vpmovsxbq mem xmm", ("1*p15", 1)), + # ("vpmovsxbw xmm ymm", ("1*p5", 1)), + # ("vpmovsxbw mem ymm", ("1*p5", 1)), + # ("vpmovsxbd xmm ymm", ("1*p5", 1)), + # ("vpmovsxbd mem ymm", ("1*p5", 1)), + # ("vpmovsxbq xmm ymm", ("1*p5", 1)), + # ("vpmovsxbq mem ymm", ("1*p5", 1)), + # ("vpmovsxbw ymm zmm", ("1*p5", 3)), + # ("vpmovsxbw mem zmm", ("1*p5", 1)), ## https://www.felixcloutier.com/x86/pmovzx - #("pmovzxbw xmm xmm", ("1*p15", 1)), - #("pmovzxbw mem xmm", ("1*p15", 1)), - #("vpmovzxbw xmm xmm", ("1*p15", 1)), - #("vpmovzxbw mem xmm", ("1*p15", 1)), - #("vpmovzxbw xmm ymm", ("1*p5", 1)), - #("vpmovzxbw mem ymm", ("1*p5", 1)), - #("vpmovzxbw ymm zmm", ("1*p5", 1)), - #("vpmovzxbw mem zmm", ("1*p5", 1)), + # ("pmovzxbw xmm xmm", ("1*p15", 1)), + # ("pmovzxbw mem xmm", ("1*p15", 1)), + # ("vpmovzxbw xmm xmm", ("1*p15", 1)), + # ("vpmovzxbw mem xmm", ("1*p15", 1)), + # ("vpmovzxbw xmm ymm", ("1*p5", 1)), + # ("vpmovzxbw mem ymm", ("1*p5", 1)), + # ("vpmovzxbw ymm zmm", ("1*p5", 1)), + # ("vpmovzxbw mem zmm", ("1*p5", 1)), ################################################################## ## https://www.felixcloutier.com/x86/movbe - #("movbe gpr mem", ("1*p15", 6)), - #("movbe mem gpr", ("1*p15", 6)), + # ("movbe gpr mem", ("1*p15", 6)), + # ("movbe mem gpr", ("1*p15", 6)), ################################################ # https://www.felixcloutier.com/x86/movapd # TODO with masking! @@ -1392,7 +1392,7 @@ spr_mov_instructions = [ # https://www.felixcloutier.com/x86/movdqu:vmovdqu8:vmovdqu16:vmovdqu32:vmovdqu64 # TODO with masking! # https://www.felixcloutier.com/x86/movq2dq - #("movq2dq mm xmm", ("1*p0+1*p015", 1)), + # ("movq2dq mm xmm", ("1*p0+1*p015", 1)), # https://www.felixcloutier.com/x86/movsd # TODO with masking! # https://www.felixcloutier.com/x86/movshdup @@ -1410,7 +1410,6 @@ spr_mov_instructions = [ ] - class MOVEntryBuilderIntelWithPort7AGU(MOVEntryBuilder): # for HSW, BDW, SKX and CSX From 8d0900e46aeb5b36849b9f0ca5a66c473cc9ea43 Mon Sep 17 00:00:00 2001 From: JanLJL Date: Fri, 3 May 2024 12:31:50 +0200 Subject: [PATCH 6/7] added missing TP entries and removed duplicates --- osaca/data/v2.yml | 50 ++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 41 insertions(+), 9 deletions(-) diff --git a/osaca/data/v2.yml b/osaca/data/v2.yml index 82e0c7d..e9875dc 100644 --- a/osaca/data/v2.yml +++ b/osaca/data/v2.yml @@ -147,7 +147,7 @@ instruction_forms: prefix: '*' - class: identifier throughput: 0.25 - latency: ~ # 1*p67 + latency: 1.0 # 1*p67 port_pressure: [[1, '2367']] - name: and operands: @@ -2827,9 +2827,18 @@ instruction_forms: - name: fabs operands: - class: register - prefix: '*' + prefix: x - class: register - prefix: '*' + prefix: x + throughput: 0.25 + latency: 1.0 # 1*p0123 + port_pressure: [[1, '0123']] +- name: fabs + operands: + - class: register + prefix: w + - class: register + prefix: w throughput: 0.25 latency: 1.0 # 1*p0123 port_pressure: [[1, '0123']] @@ -3030,11 +3039,22 @@ instruction_forms: - name: [fmax, fmaxnm, fmin, fminnm] operands: - class: register - prefix: '*' + prefix: x - class: register - prefix: '*' + prefix: x - class: register - prefix: '*' + prefix: x + throughput: 0.25 + latency: 2.0 # 1*p8,9,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: [fmax, fmaxnm, fmin, fminnm] + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w throughput: 0.25 latency: 2.0 # 1*p8,9,10,11 port_pressure: [[1, ['8', '9', '10', '11']]] @@ -3046,6 +3066,7 @@ instruction_forms: imd: '*' latency: 2.0 # 1*p8,9,10,11 port_pressure: [[1, ['8', '9', '10', '11']]] + throughput: 0.25 - name: fmov operands: - class: register @@ -3107,11 +3128,22 @@ instruction_forms: - name: [fmul, fnmul] operands: - class: register - prefix: '*' + prefix: x - class: register - prefix: '*' + prefix: x - class: register - prefix: '*' + prefix: x + throughput: 0.25 + latency: 3.0 # 1*p89,10,11 + port_pressure: [[1, ['8', '9', '10', '11']]] +- name: [fmul, fnmul] + operands: + - class: register + prefix: w + - class: register + prefix: w + - class: register + prefix: w throughput: 0.25 latency: 3.0 # 1*p89,10,11 port_pressure: [[1, ['8', '9', '10', '11']]] From c87524384a898da30e0349836cbaf8abb8c7cf2f Mon Sep 17 00:00:00 2001 From: JanLJL Date: Fri, 3 May 2024 12:36:30 +0200 Subject: [PATCH 7/7] formatting --- osaca/data/generate_mov_entries.py | 36 +++++++++++++++--------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/osaca/data/generate_mov_entries.py b/osaca/data/generate_mov_entries.py index 96308bd..0bde448 100644 --- a/osaca/data/generate_mov_entries.py +++ b/osaca/data/generate_mov_entries.py @@ -1019,7 +1019,7 @@ spr_mov_instructions = [ ("vmovaps zmm zmm", ("1*p0,1,5,6,10", 1)), ("vmovaps zmm mem", ("", 0)), ("vmovaps mem zmm", ("", 0)), - ## https://www.felixcloutier.com/x86/movd:movq + # # https://www.felixcloutier.com/x86/movd:movq # ("movd gpr mm", ("1*p5", 1)), # ("movd mem mm", ("", 0)), # ("movq gpr mm", ("1*p5", 1)), @@ -1044,7 +1044,7 @@ spr_mov_instructions = [ # ("vmovd xmm mem", ("", 0)), # ("vmovq xmm gpr", ("1*p0", 1)), # ("vmovq xmm mem", ("", 0)), - ## https://www.felixcloutier.com/x86/movddup + # # https://www.felixcloutier.com/x86/movddup # ("movddup xmm xmm", ("1*p5", 1)), # ("movddup mem xmm", ("", 0)), # ("vmovddup xmm xmm", ("1*p5", 1)), @@ -1129,37 +1129,37 @@ spr_mov_instructions = [ ("vmovdqu64 zmm zmm", ("1*p0,1,5,6,10", 1)), ("vmovdqu64 mem zmm", ("", 0)), ("vmovdqu64 zmm mem", ("", 0)), - ## https://www.felixcloutier.com/x86/movhlps + # # https://www.felixcloutier.com/x86/movhlps # ("movhlps xmm xmm", ("1*p5", 1)), # ("vmovhlps xmm xmm xmm", ("1*p5", 1)), - ## https://www.felixcloutier.com/x86/movhpd + # # https://www.felixcloutier.com/x86/movhpd # ("movhpd mem xmm", ("1*p5", 1)), # ("vmovhpd mem xmm xmm", ("1*p5", 1)), # ("movhpd xmm mem", ("", 0)), # ("vmovhpd mem xmm", ("", 0)), - ## https://www.felixcloutier.com/x86/movhps + # # https://www.felixcloutier.com/x86/movhps # ("movhps mem xmm", ("1*p5", 1)), # ("vmovhps mem xmm xmm", ("1*p5", 1)), # ("movhps xmm mem", ("", 0)), # ("vmovhps mem xmm", ("", 0)), - ## https://www.felixcloutier.com/x86/movlhps + # # https://www.felixcloutier.com/x86/movlhps # ("movlhps xmm xmm", ("1*p5", 1)), # ("vmovlhps xmm xmm xmm", ("1*p5", 1)), - ## https://www.felixcloutier.com/x86/movlpd + # # https://www.felixcloutier.com/x86/movlpd # ("movlpd mem xmm", ("1*p5", 1)), # ("vmovlpd mem xmm xmm", ("1*p5", 1)), # ("movlpd xmm mem", ("", 0)), # ("vmovlpd mem xmm", ("1*p5", 1)), - ## https://www.felixcloutier.com/x86/movlps + # # https://www.felixcloutier.com/x86/movlps # ("movlps mem xmm", ("1*p5", 1)), # ("vmovlps mem xmm xmm", ("1*p5", 1)), # ("movlps xmm mem", ("", 0)), # ("vmovlps mem xmm", ("1*p5", 1)), - ## https://www.felixcloutier.com/x86/movmskpd + # # https://www.felixcloutier.com/x86/movmskpd # ("movmskpd xmm gpr", ("1*p0", 1)), # ("vmovmskpd xmm gpr", ("1*p0", 1)), # ("vmovmskpd ymm gpr", ("1*p0", 1)), - ## https://www.felixcloutier.com/x86/movmskps + # # https://www.felixcloutier.com/x86/movmskps # ("movmskps xmm gpr", ("1*p0", 1)), # ("vmovmskps xmm gpr", ("1*p0", 1)), # ("vmovmskps ymm gpr", ("1*p0", 1)), @@ -1207,7 +1207,7 @@ spr_mov_instructions = [ ("vmovsd xmm xmm xmm", ("1*p0,1,5,6,10", 1)), ("vmovsd mem xmm", ("", 0)), ("vmovsd xmm mem", ("", 0)), - ## https://www.felixcloutier.com/x86/movshdup + # # https://www.felixcloutier.com/x86/movshdup # ("movshdup xmm xmm", ("1*p15", 1)), # ("movshdup mem xmm", ("", 0)), # ("vmovshdup xmm xmm", ("1*p15", 1)), @@ -1216,7 +1216,7 @@ spr_mov_instructions = [ # ("vmovshdup mem ymm", ("", 0)), # ("vmovshdup zmm zmm", ("1*p5", 1)), # ("vmovshdup mem zmm", ("", 0)), - ## https://www.felixcloutier.com/x86/movsldup + # # https://www.felixcloutier.com/x86/movsldup # ("movsldup xmm xmm", ("1*p15", 1)), # ("movsldup mem xmm", ("", 0)), # ("vmovsldup xmm xmm", ("1*p15", 1)), @@ -1272,7 +1272,7 @@ spr_mov_instructions = [ ("vmovups zmm zmm", ("1*p0,1,5,6,10", 1)), ("vmovups mem zmm", ("", 0)), ("vmovups zmm mem", ("", 0)), - ## https://www.felixcloutier.com/x86/movzx + # # https://www.felixcloutier.com/x86/movzx # ("movzx gpr gpr", ("1*p0,1,5,6,10", 1)), # ("movzx mem gpr", ("", 0)), # ("movzb gpr gpr", ("1*p0,1,5,6,10", 1)), # AT&T version @@ -1283,7 +1283,7 @@ spr_mov_instructions = [ # ("movzl mem gpr", ("", 0)), # AT&T version # ("movzq gpr gpr", ("1*p0156", 1)), # AT&T version # ("movzq mem gpr", ("", 0)), # AT&T version - ## https://www.felixcloutier.com/x86/cmovcc + # # https://www.felixcloutier.com/x86/cmovcc # ("cmova gpr gpr", ("2*p06", 1)), # ("cmova mem gpr", ("", 0)), # ("cmovae gpr gpr", ("1*p06", 1)), @@ -1342,11 +1342,11 @@ spr_mov_instructions = [ # ("cmovs mem gpr", ("", 0)), # ("cmovz gpr gpr", ("1*p06", 1)), # ("cmovz mem gpr", ("", 0)), - ## https://www.felixcloutier.com/x86/pmovmskb + # # https://www.felixcloutier.com/x86/pmovmskb # ("pmovmskb mm gpr", ("1*p0", 1)), # ("pmovmskb xmm gpr", ("1*p0", 1)), # ("vpmovmskb xmm gpr", ("1*p0", 1)), - ## https://www.felixcloutier.com/x86/pmovsx + # # https://www.felixcloutier.com/x86/pmovsx # ("pmovsxbw xmm xmm", ("1*p15", 1)), # ("pmovsxbw mem xmm", ("1*p15", 1)), # ("pmovsxbd xmm xmm", ("1*p15", 1)), @@ -1367,7 +1367,7 @@ spr_mov_instructions = [ # ("vpmovsxbq mem ymm", ("1*p5", 1)), # ("vpmovsxbw ymm zmm", ("1*p5", 3)), # ("vpmovsxbw mem zmm", ("1*p5", 1)), - ## https://www.felixcloutier.com/x86/pmovzx + # # https://www.felixcloutier.com/x86/pmovzx # ("pmovzxbw xmm xmm", ("1*p15", 1)), # ("pmovzxbw mem xmm", ("1*p15", 1)), # ("vpmovzxbw xmm xmm", ("1*p15", 1)), @@ -1377,7 +1377,7 @@ spr_mov_instructions = [ # ("vpmovzxbw ymm zmm", ("1*p5", 1)), # ("vpmovzxbw mem zmm", ("1*p5", 1)), ################################################################## - ## https://www.felixcloutier.com/x86/movbe + # # https://www.felixcloutier.com/x86/movbe # ("movbe gpr mem", ("1*p15", 6)), # ("movbe mem gpr", ("1*p15", 6)), ################################################