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fixed read out of store TP from DB

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This commit is contained in:
JanLJL
2023-06-20 21:20:41 +02:00
parent 1ac20073ab
commit c6ed492db3
2 changed files with 11 additions and 16 deletions
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17
osaca/semantics/arch_semantics.py
View File

@@ -302,21 +302,10 @@ class ArchSemantics(ISASemantics):
+ instruction_form["semantic_operands"]["src_dst"]
)
store_perf_data = self._machine_model.get_store_throughput(
[x["memory"] for x in destinations if "memory" in x][0]
[x["memory"] for x in destinations if "memory" in x][0], dummy_reg
)
# if multiple options, choose based on reg type
st_data_port_uops = [
stp["port_pressure"]
for stp in store_perf_data
if "src" in stp
and self._machine_model._check_operands(
dummy_reg, {"register": {"name": stp["src"]}}
)
]
if len(st_data_port_uops) < 1:
st_data_port_uops = store_perf_data[0]["port_pressure"]
else:
st_data_port_uops = st_data_port_uops[0]
st_data_port_uops = store_perf_data[0]["port_pressure"]
# zero data port pressure and remove HAS_ST flag if
# - no mem operand in dst &&
# - all mem operands in src_dst are pre-/post-indexed

10
osaca/semantics/hw_model.py
View File

@@ -234,9 +234,15 @@ class MachineModel(object):
# assume 0 for now, since load-store-dependencies currently not detectable
return 0
def get_store_throughput(self, memory):
"""Return store throughput for given register type."""
def get_store_throughput(self, memory, src_reg=None):
"""Return store throughput for a given destination and register type."""
st_tp = [m for m in self._data["store_throughput"] if self._match_mem_entries(memory, m)]
if src_reg is not None:
st_tp = [
tp
for tp in st_tp
if "src" in tp and self._check_operands(src_reg, {"register": {"name": tp["src"]}})
]
if len(st_tp) > 0:
return st_tp.copy()
return [{"port_pressure": self._data["store_throughput_default"].copy()}]