From ca3ca56a015eaa05c01cf2900098c084c89ad8e2 Mon Sep 17 00:00:00 2001 From: Qingcai Jiang Date: Tue, 7 Dec 2021 18:27:42 +0800 Subject: [PATCH] add some instructions in tsv110.yml --- osaca/data/tsv110.yml | 549 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 547 insertions(+), 2 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 0994233..6cc98ac 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -29,6 +29,182 @@ instruction_forms: throughput: 0.5 latency: 0.0 port_pressure: [[1, '12']] +# logical instructions: and (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: and + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: and + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +# logical instructions: ands (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: ands + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '12']] + uops: 1 +- name: ands + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '12']] + uops: 1 +# logical instructions: orr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: orr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: orr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +# logical instructions: eor (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: eor + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: eor + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +# logical instructions: bic (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: bic + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +# logical instructions: bics (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: bics + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.5 + latency: 1.0 + port_pressure: [[1, '12']] + uops: 1 +# shift instructions: lsl (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: lsl + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: lsl + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +# shift instructions: lsr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: lsr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 +- name: lsr + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: immediate + imd: int + throughput: 0.3333 + latency: 1.0 + port_pressure: [[1, '012']] + uops: 1 # arithmetic instructions: add (from AArch64SchedTSV110.td and ibench) - name: add operands: @@ -140,6 +316,18 @@ instruction_forms: throughput: 0.33333 uops: 1 # arithmetic instructions: subs (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: subs + operands: + - class: register + prefix: x + - class: register + prefix: x + - class: register + prefix: x + latency: 1.0 + port_pressure: [[1, '12']] + throughput: 0.5 + uops: 1 - name: subs operands: - class: register @@ -165,6 +353,154 @@ instruction_forms: port_pressure: [[1, '3']] throughput: 1.0 uops: 1 +- name: mul + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 7.0 + port_pressure: [[1, '4']] + throughput: 2.5 + uops: 1 +- name: mla + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 7.0 + port_pressure: [[1, '4']] + throughput: 2.5 + uops: 1 +- name: mla + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 7.0 + port_pressure: [[1, '4']] + throughput: 2.5 + uops: 1 +# arithmetic instructions: mla (latency and throughput from asmbench, port data from AArch64SchedTSV110.td) +- name: mla + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 7.0 + port_pressure: [[1, '4']] + throughput: 2.5 + uops: 1 +- name: mla + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 7.0 + port_pressure: [[1, '4']] + throughput: 2.5 + uops: 1 +- name: mla + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 7.0 + port_pressure: [[1, '4']] + throughput: 2.5 + uops: 1 +# arithmetic instructions: neg (latency and throughput from ibench, port data from AArch64SchedTSV110.td) +- name: neg + operands: + - class: register + prefix: x + - class: register + prefix: x + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: neg + operands: + - class: register + prefix: d + - class: register + prefix: d + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: neg + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: neg + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: neg + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 1.0 + uops: 2 # arithmetic instructions: fadd (latency and throughput from ibench, port data from AArch64SchedTSV110.td) - name: fadd operands: @@ -558,7 +894,216 @@ instruction_forms: port_pressure: [1, '12'] throughput: 0.5 uops: 1 -# miscellaneous instructions: mov (assumed free register renaming, register to register moves without conversion) +# miscellaneous instructions: zip1 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: zip1 + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +- name: zip1 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +- name: zip1 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +# miscellaneous instructions: zip2 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: zip2 + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +- name: zip2 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +- name: zip2 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +# miscellaneous instructions: uzip1 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: uzip1 + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +- name: uzip1 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +- name: uzip1 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +# miscellaneous instructions: uzip2 (throughput from asmbench, latency and port data from AArch64SchedTSV110.td) +- name: uzip2 + operands: + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + - class: register + prefix: v + shape: b + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +- name: uzip2 + operands: + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + - class: register + prefix: v + shape: h + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +- name: uzip2 + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 2.0 + port_pressure: [[1, '4'], [1, '5']] + throughput: 0.5 + uops: 2 +# miscellaneous instructions: scvtf (throughput and latency from asmbench, port data from AArch64SchedTSV110.td, imformation missed with scala instructions) +- name: scvtf + operands: + - class: register + prefix: v + shape: d + - class: register + prefix: v + shape: d + latency: 3.0 + port_pressure: [[1, '45']] + throughput: 1.0 + uops: 1 +- name: scvtf + operands: + - class: register + prefix: v + shape: s + - class: register + prefix: v + shape: s + latency: 3.0 + port_pressure: [[2, '45']] + throughput: 2.0 + uops: 1 +# miscellaneous instructions: fmov (assumed free register renaming, register to register moves without conversion) - name: fmov operands: - class: register @@ -570,7 +1115,7 @@ instruction_forms: throughput: 0.0 uops: 0 # memory instructions: ldur (data from AArch64SchedTSV110.td) - - name: ldr +- name: ldr operands: - class: register prefix: w