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flake8 standards

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This commit is contained in:
stefandesouza
2023-12-03 21:04:58 +01:00
parent cef7f8098d
commit cac4a0ebf2
17 changed files with 88 additions and 99 deletions
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11
osaca/db_interface.py
View File

@@ -10,7 +10,6 @@ from collections import OrderedDict
import ruamel.yaml
from osaca.semantics import MachineModel
from osaca.parser import instructionForm
from osaca.parser.memory import MemoryOperand
from osaca.parser.register import RegisterOperand
from osaca.parser.immediate import ImmediateOperand
@@ -437,7 +436,7 @@ def _check_sanity_arch_db(arch_mm, isa_mm, internet_check=True):
# Check operands
for operand in instr_form["operands"]:
if isinstance(operand, RegisterOperand) and not (
operand.name != None or operand.prefix != None
operand.name is not None or operand.prefix is not None
):
# Missing 'name' key
bad_operand.append(instr_form)
@@ -449,7 +448,7 @@ def _check_sanity_arch_db(arch_mm, isa_mm, internet_check=True):
):
# Missing at least one key necessary for memory operands
bad_operand.append(instr_form)
elif isinstance(operand, ImmediateOperand) and operand.type == None:
elif isinstance(operand, ImmediateOperand) and operand.type is None:
# Missing 'imd' key
bad_operand.append(instr_form)
# every entry exists twice --> uniquify
@@ -613,11 +612,11 @@ def _get_full_instruction_name(instruction_form):
for op in instruction_form["operands"]:
if isinstance(op, RegisterOperand):
op_attrs = []
if op.name != None:
if op.name is not None:
op_attrs.append("name:" + op.name)
if op.prefix != None:
if op.prefix is not None:
op_attrs.append("prefix:" + op.prefix)
if op.shape != None:
if op.shape is not None:
op_attrs.append("shape:" + op.shape)
operands.append("{}({})".format("register", ",".join(op_attrs)))
return "{} {}".format(instruction_form["name"].lower(), ",".join(operands))

1
osaca/parser/base_parser.py
View File

@@ -13,6 +13,7 @@ class BaseParser(object):
IDENTIFIER_ID = "identifier"
MEMORY_ID = "memory"
REGISTER_ID = "register"
CONDITION_ID = "condition"
segment_ext_id = "segment_extension"
instruction_id = "instruction"
operands_id = "operands"

2
osaca/parser/instruction_form.py
View File

@@ -1,7 +1,5 @@
#!/usr/bin/env python3
from osaca.parser.directive import DirectiveOperand
class instructionForm:
def __init__(

16
osaca/parser/parser_AArch64.py
View File

@@ -291,7 +291,7 @@ class ParserAArch64(BaseParser):
try:
result = self.process_operand(self.label.parseString(line, parseAll=True).asDict())
instruction_form.label = result.name
if result.comment != None:
if result.comment is not None:
instruction_form.comment = " ".join(result.comment)
except pp.ParseException:
pass
@@ -390,8 +390,8 @@ class ParserAArch64(BaseParser):
if "comment" in operand["directive"]
else None,
)
if "condition" in operand:
return self.process_condition(operand["condition"])
if self.CONDITION_ID in operand:
return self.process_condition(operand[self.CONDITION_ID])
return operand
def process_register_operand(self, operand):
@@ -449,7 +449,7 @@ class ParserAArch64(BaseParser):
return new_reg
def process_condition(self, condition):
return ConditionOperand(ccode=condition.lower())
return ConditionOperand(ccode=condition.upper())
def resolve_range_list(self, operand):
"""
@@ -502,7 +502,7 @@ class ParserAArch64(BaseParser):
index = register_list.get("index", None)
new_dict = {dict_name: rlist, "index": index}
if len(new_dict[dict_name]) == 1:
return {self.REGISTER_ID: new_dict[dict_name][0]}
return {self.REGISTER_ID: new_dict}
return {self.REGISTER_ID: new_dict}
def process_immediate(self, immediate):
@@ -581,11 +581,11 @@ class ParserAArch64(BaseParser):
"""Normalize immediate to decimal based representation"""
if isinstance(imd, IdentifierOperand):
return imd
if imd.value != None and imd.type == "float":
if imd.value is not None and imd.type == "float":
return self.ieee_to_float(imd.value)
elif imd.value != None and imd.type == "double":
elif imd.value is not None and imd.type == "double":
return self.ieee_to_float(imd.value)
elif imd.value != None:
elif imd.value is not None:
if isinstance(imd.value, str):
# hex or bin, return decimal
return int(imd.value, 0)

11
osaca/parser/parser_x86att.py
View File

@@ -14,7 +14,6 @@ from osaca.parser.label import LabelOperand
from osaca.parser.register import RegisterOperand
from osaca.parser.identifier import IdentifierOperand
from osaca.parser.immediate import ImmediateOperand
from osaca.parser.operand import Operand
class ParserX86ATT(BaseParser):
@@ -223,7 +222,7 @@ class ParserX86ATT(BaseParser):
try:
result = self.process_operand(self.label.parseString(line, parseAll=True).asDict())
instruction_form.label = result.name
if result.comment != None:
if result.comment is not None:
instruction_form.comment = " ".join(result.comment)
except pp.ParseException:
pass
@@ -239,7 +238,7 @@ class ParserX86ATT(BaseParser):
parameter_id=result.parameters,
)
if result.comment != None:
if result.comment is not None:
instruction_form.comment = " ".join(result.comment)
except pp.ParseException:
pass
@@ -340,11 +339,11 @@ class ParserX86ATT(BaseParser):
offset = ImmediateOperand(value_id=offset)
elif offset is not None and "value" in offset:
offset = ImmediateOperand(value_id=int(offset["value"], 0))
if base != None:
if base is not None:
baseOp = RegisterOperand(
name=base["name"], prefix_id=base["prefix"] if "prefix" in base else None
)
if index != None:
if index is not None:
indexOp = RegisterOperand(
name=index["name"], prefix_id=index["prefix"] if "prefix" in index else None
)
@@ -386,7 +385,7 @@ class ParserX86ATT(BaseParser):
"""Normalize immediate to decimal based representation"""
if isinstance(imd, IdentifierOperand):
return imd
if imd.value != None:
if imd.value is not None:
if isinstance(imd.value, str):
# return decimal
return int(imd.value, 0)

6
osaca/semantics/arch_semantics.py
View File

@@ -11,8 +11,6 @@ from .hw_model import MachineModel
from .isa_semantics import INSTR_flags, ISASemantics
from osaca.parser.memory import MemoryOperand
from osaca.parser.register import RegisterOperand
from osaca.parser.immediate import ImmediateOperand
from osaca.parser.identifier import IdentifierOperand
class ArchSemantics(ISASemantics):
@@ -278,7 +276,7 @@ class ArchSemantics(ISASemantics):
data_port_uops = [
ldp.port_pressure
for ldp in load_perf_data
if ldp.dst != None
if ldp.dst is not None
and self._machine_model._check_operands(
dummy_reg, RegisterOperand(name=ldp.dst)
)
@@ -391,7 +389,7 @@ class ArchSemantics(ISASemantics):
latency = 0.0
latency_wo_load = latency
instruction_form.port_pressure = [0.0 for i in range(port_number)]
instruction_formport_uops = []
# instruction_formport_uops = []
flags += [INSTR_flags.TP_UNKWN, INSTR_flags.LT_UNKWN]
# flatten flag list
flags = list(set(flags))

42
osaca/semantics/hw_model.py
View File

@@ -233,7 +233,7 @@ class MachineModel(object):
elif o["class"] == "condition":
new_operands.append(
ConditionOperand(
ccode=o["ccode"],
ccode=o["ccode"].upper(),
source=o["source"] if "source" in o else False,
destination=o["destination"] if "destination" in o else False,
)
@@ -319,7 +319,7 @@ class MachineModel(object):
def set_instruction_entry(self, entry):
"""Import instruction as entry object form information."""
if entry.instruction == None and entry.operands == []:
if entry.instruction is None and entry.operands == []:
raise KeyError
self.set_instruction(
entry.instruction,
@@ -401,11 +401,11 @@ class MachineModel(object):
operands = []
for op in instruction_form.operands:
op_attrs = []
if op.name != None:
if op.name is not None:
op_attrs.append("name:" + op.name)
if op.prefix != None:
if op.prefix is not None:
op_attrs.append("prefix:" + op.prefix)
if op.shape != None:
if op.shape is not None:
op_attrs.append("shape:" + op.shape)
operands.append("{}({})".format("register", ",".join(op_attrs)))
return "{} {}".format(instruction_form.instruction.lower(), ",".join(operands))
@@ -465,7 +465,7 @@ class MachineModel(object):
formatted_load_throughput.append(cm)
# Create YAML object
yaml = self._create_yaml_object()
# yaml = self._create_yaml_object()
if not stream:
stream = StringIO()
"""
@@ -701,32 +701,32 @@ class MachineModel(object):
return self._is_AArch64_mem_type(i_operand, operand)
# immediate
if isinstance(i_operand, ImmediateOperand) and i_operand.type == self.WILDCARD:
return isinstance(operand, ImmediateOperand) and (operand.value != None)
return isinstance(operand, ImmediateOperand) and (operand.value is not None)
if isinstance(i_operand, ImmediateOperand) and i_operand.type == "int":
return (
isinstance(operand, ImmediateOperand)
and operand.type == "int"
and operand.value != None
and operand.value is not None
)
if isinstance(i_operand, ImmediateOperand) and i_operand.type == "float":
return (
isinstance(operand, ImmediateOperand)
and operand.type == "float"
and operand.value != None
and operand.value is not None
)
if isinstance(i_operand, ImmediateOperand) and i_operand.type == "double":
return (
isinstance(operand, ImmediateOperand)
and operand.type == "double"
and operand.value != None
and operand.value is not None
)
# identifier
if isinstance(operand, IdentifierOperand) or (
isinstance(operand, ImmediateOperand) and operand.identifier != None
isinstance(operand, ImmediateOperand) and operand.identifier is not None
):
return isinstance(i_operand, IdentifierOperand)
# prefetch option
@@ -786,8 +786,8 @@ class MachineModel(object):
"""Check if register type match."""
# check for wildcards
if reg.prefix == self.WILDCARD or i_reg.prefix == self.WILDCARD:
if reg.shape != None:
if i_reg.shape != None and (
if reg.shape is not None:
if i_reg.shape is not None and (
reg.shape == i_reg.shape or self.WILDCARD in (reg.shape + i_reg.shape)
):
return True
@@ -796,14 +796,14 @@ class MachineModel(object):
# check for prefix and shape
if reg.prefix != i_reg.prefix:
return False
if reg.shape != None:
if i_reg.shape != None and (
if reg.shape is not None:
if i_reg.shape is not None and (
reg.shape == i_reg.shape or self.WILDCARD in (reg.shape + i_reg.shape)
):
return True
return False
if reg.lanes != None:
if i_reg.lanes != None and (
if reg.lanes is not None:
if i_reg.lanes is not None and (
reg.lanes == i_reg.lanes or self.WILDCARD in (reg.lanes + i_reg.lanes)
):
return True
@@ -832,13 +832,13 @@ class MachineModel(object):
# Consider masking and zeroing for AVX512
if consider_masking:
mask_ok = zero_ok = True
if reg.mask != None or i_reg.mask != None:
if reg.mask is not None or i_reg.mask is not None:
# one instruction is missing the masking while the other has it
mask_ok = False
# check for wildcard
if (
(
reg.mask != None
reg.mask is not None
and reg.mask.rstrip(string.digits).lower() == i_reg.mask
)
or reg.mask == self.WILDCARD
@@ -891,7 +891,7 @@ class MachineModel(object):
or i_mem.index == self.WILDCARD
or (
mem.index is not None
and mem.index.prefix != None
and mem.index.prefix is not None
and mem.index.prefix == i_mem.index
)
)
@@ -907,7 +907,7 @@ class MachineModel(object):
and (
i_mem.post_indexed == self.WILDCARD
or mem.post_indexed == i_mem.post_indexed
or (type(mem.post_indexed) == dict and i_mem.post_indexed == True)
or (isinstance(mem.post_indexed, dict) and i_mem.post_indexed)
)
):
return True

14
osaca/semantics/isa_semantics.py
View File

@@ -2,7 +2,7 @@
from itertools import chain
from osaca import utils
from osaca.parser import AttrDict, ParserAArch64, ParserX86ATT
from osaca.parser import ParserAArch64, ParserX86ATT
from osaca.parser.memory import MemoryOperand
from osaca.parser.operand import Operand
from osaca.parser.register import RegisterOperand
@@ -164,7 +164,7 @@ class ISASemantics(object):
if instruction_form.instruction is None:
return {}
dest_reg_names = [
(op.prefix if op.prefix != None else "") + op.name
(op.prefix if op.prefix is not None else "") + op.name
for op in chain(
instruction_form.semantic_operands["destination"],
instruction_form.semantic_operands["src_dst"],
@@ -194,13 +194,13 @@ class ISASemantics(object):
for o in instruction_form.operands:
if (
isinstance(o, MemoryOperand)
and o.base != None
and o.base is not None
and isinstance(o.post_indexed, dict)
):
base_name = (o.base.prefix if o.base.prefix != None else "") + o.base.name
base_name = (o.base.prefix if o.base.prefix is not None else "") + o.base.name
return {
base_name: {
"name": (o.base.prefix if o.base.prefix != None else "") + o.base.name,
"name": (o.base.prefix if o.base.prefix is not None else "") + o.base.name,
"value": o.post_indexed["value"],
}
}
@@ -218,7 +218,7 @@ class ISASemantics(object):
"This is currently not supprted.".format(instruction_form.line)
)
base_name = (o.base.prefix if o.base.prefix != None else "") + o.base.name
base_name = (o.base.prefix if o.base.prefix is not None else "") + o.base.name
reg_operand_names = {base_name: "op1"}
operand_state = {"op1": {"name": base_name, "value": o.offset.value}}
@@ -227,7 +227,7 @@ class ISASemantics(object):
operand_name = "op{}".format(i + 1)
if isinstance(o, RegisterOperand):
o_reg_name = (o.prefix if o.prefix != None else "") + o.name
o_reg_name = (o.prefix if o.prefix is not None else "") + o.name
reg_operand_names[o_reg_name] = operand_name
operand_state[operand_name] = {"name": o_reg_name, "value": 0}
elif isinstance(o, ImmediateOperand):

30
osaca/semantics/kernel_dg.py
View File

@@ -85,7 +85,7 @@ class KernelDG(nx.DiGraph):
# print(instruction_form.line_number,"\t",dep.line_number,"\n")
edge_weight = (
instruction_form.latency
if "mem_dep" in dep_flags or instruction_form.latency_wo_load == None
if "mem_dep" in dep_flags or instruction_form.latency_wo_load is None
else instruction_form.latency_wo_load
)
if "storeload_dep" in dep_flags and self.model is not None:
@@ -299,7 +299,7 @@ class KernelDG(nx.DiGraph):
# write to register -> abort
if self.is_written(dst, instr_form):
break
if not isinstance(dst, Operand) and dst["class"] == "flag" and flag_dependencies:
if not isinstance(dst, Operand) and ("flag" in dst or dst["class"] == "flag" if "class" in dst else False) and flag_dependencies:
# read of flag
if self.is_read(dst, instr_form):
yield instr_form, []
@@ -317,7 +317,7 @@ class KernelDG(nx.DiGraph):
# if dst.memory.index:
# if self.is_read(dst.memory.index, instr_form):
# yield instr_form, []
if dst.post_indexed != False:
if dst.post_indexed:
# Check for read of base register until overwrite
if self.is_written(dst.base, instr_form):
break
@@ -377,7 +377,7 @@ class KernelDG(nx.DiGraph):
):
if isinstance(src, RegisterOperand):
is_read = self.parser.is_reg_dependend_of(register, src) or is_read
if not isinstance(src, Operand) and src["class"] == "flag":
if not isinstance(src, Operand) and ("flag" in src or src["class"] == "flag" if "class" in src else False):
is_read = self.parser.is_flag_dependend_of(register, src) or is_read
if isinstance(src, MemoryOperand):
if src.base is not None:
@@ -411,15 +411,15 @@ class KernelDG(nx.DiGraph):
# determine absolute address change
addr_change = 0
if isinstance(src.offset, ImmediateOperand) and src.offset.value != None:
if isinstance(src.offset, ImmediateOperand) and src.offset.value is not None:
addr_change += src.offset.value
if mem.offset:
addr_change -= mem.offset.value
if mem.base and src.base:
base_change = register_changes.get(
(src.base.prefix if src.base.prefix != None else "") + src.base.name,
(src.base.prefix if src.base.prefix is not None else "") + src.base.name,
{
"name": (src.base.prefix if src.base.prefix != None else "")
"name": (src.base.prefix if src.base.prefix is not None else "")
+ src.base.name,
"value": 0,
},
@@ -429,7 +429,7 @@ class KernelDG(nx.DiGraph):
continue
if (
mem.base.prefix
if mem.base.prefix != None
if mem.base.prefix is not None
else "" + mem.base.name != base_change["name"]
):
# base registers do not match
@@ -440,9 +440,9 @@ class KernelDG(nx.DiGraph):
continue
if mem.index and src.index:
index_change = register_changes.get(
(src.index.prefix if src.index.prefix != None else "") + src.index.name,
(src.index.prefix if src.index.prefix is not None else "") + src.index.name,
{
"name": (src.index.prefix if src.index.prefix != None else "")
"name": (src.index.prefix if src.index.prefix is not None else "")
+ src.index.name,
"value": 0,
},
@@ -455,7 +455,7 @@ class KernelDG(nx.DiGraph):
continue
if (
mem.index.prefix
if mem.index.prefix != None
if mem.index.prefix is not None
else "" + mem.index.name != index_change["name"]
):
# index registers do not match
@@ -480,7 +480,7 @@ class KernelDG(nx.DiGraph):
):
if isinstance(dst, RegisterOperand):
is_written = self.parser.is_reg_dependend_of(register, dst) or is_written
if not isinstance(dst, Operand) and dst["class"] == "flag":
if not isinstance(dst, Operand) and ("flag" in dst or dst["class"] == "flag" if "class" in dst else False):
is_written = self.parser.is_flag_dependend_of(register, dst) or is_written
if isinstance(dst, MemoryOperand):
if dst.pre_indexed or dst.post_indexed:
@@ -591,9 +591,9 @@ class KernelDG(nx.DiGraph):
if node.instruction is not None:
mapping[n] = "{}: {}".format(n, node.instruction)
else:
label = "label" if node.label != None else None
label = "directive" if node.directive != None else label
label = "comment" if node.comment != None and label is None else label
label = "label" if node.label is not None else None
label = "directive" if node.directive is not None else label
label = "comment" if node.comment is not None and label is None else label
mapping[n] = "{}: {}".format(n, label)
graph.nodes[n]["fontname"] = "italic"
graph.nodes[n]["fontsize"] = 11.0

8
osaca/semantics/marker_utils.py
View File

@@ -2,12 +2,12 @@
from collections import OrderedDict
from osaca.parser import ParserAArch64, ParserX86ATT, get_parser
COMMENT_MARKER = {"start": "OSACA-BEGIN", "end": "OSACA-END"}
from osaca.parser.register import RegisterOperand
from osaca.parser.identifier import IdentifierOperand
from osaca.parser.immediate import ImmediateOperand
COMMENT_MARKER = {"start": "OSACA-BEGIN", "end": "OSACA-END"}
def reduce_to_section(kernel, isa):
"""
@@ -255,7 +255,7 @@ def find_basic_blocks(lines):
terminate = False
blocks[label].append(line)
# Find end of block by searching for references to valid jump labels
if line.instruction != None and line.operands != []:
if line.instruction is not None and line.operands != []:
for operand in [o for o in line.operands if isinstance(o, IdentifierOperand)]:
if operand.name in valid_jump_labels:
terminate = True
@@ -284,7 +284,7 @@ def find_basic_loop_bodies(lines):
terminate = False
current_block.append(line)
# Find end of block by searching for references to valid jump labels
if line.instruction != None and line.operands != []:
if line.instruction is not None and line.operands != []:
# Ignore `b.none` instructions (relevant von ARM SVE code)
# This branch instruction is often present _within_ inner loop blocks, but usually
# do not terminate

10
tests/test_base_parser.py
View File

@@ -6,7 +6,9 @@ Unit tests for base assembly parser
import os
import unittest
from osaca.parser import AttrDict, BaseParser
from osaca.parser import BaseParser
from osaca.parser.register import RegisterOperand
from osaca.parser.immediate import ImmediateOperand
class TestBaseParser(unittest.TestCase):
@@ -44,8 +46,8 @@ class TestBaseParser(unittest.TestCase):
self.parser.parse_instruction(instr1)
def test_register_funcs(self):
reg_a1 = {"name": "rax"}
reg_a2 = {"name": "eax"}
reg_a1 = RegisterOperand(name="rax")
reg_a2 = RegisterOperand(name="eax")
register_string = "v1.2d"
with self.assertRaises(NotImplementedError):
self.parser.is_reg_dependend_of(reg_a1, reg_a2)
@@ -61,7 +63,7 @@ class TestBaseParser(unittest.TestCase):
self.parser.get_full_reg_name(reg_a1)
def test_normalize_imd(self):
imd_hex_1 = {"value": "0x4f"}
imd_hex_1 = ImmediateOperand(value_id="0x4f")
with self.assertRaises(NotImplementedError):
self.parser.normalize_imd(imd_hex_1)

4
tests/test_cli.py
View File

@@ -124,7 +124,6 @@ class TestCLI(unittest.TestCase):
# remove copy again
os.remove(name_copy)
"""
def test_examples(self):
kernels = [
"add",
@@ -157,7 +156,6 @@ class TestCLI(unittest.TestCase):
output = StringIO()
osaca.run(args, output_file=output)
self.assertTrue("WARNING" not in output.getvalue())
"""
def test_architectures(self):
parser = osaca.create_parser()
@@ -171,7 +169,6 @@ class TestCLI(unittest.TestCase):
output = StringIO()
osaca.run(args, output_file=output)
"""
def test_architectures_sanity(self):
# Run sanity check for all architectures
archs = osaca.SUPPORTED_ARCHS
@@ -180,7 +177,6 @@ class TestCLI(unittest.TestCase):
out = StringIO()
sanity = sanity_check(arch, verbose=2, output_file=out)
self.assertTrue(sanity, msg=out)
"""
def test_without_arch(self):
# Run test kernels without --arch flag

10
tests/test_db_interface.py
View File

@@ -33,13 +33,13 @@ class TestDBInterface(unittest.TestCase):
self.entry_tx2 = copy.copy(sample_entry)
self.entry_zen1 = copy.copy(sample_entry)
# self.entry_csx['port_pressure'] = [1.25, 0, 1.25, 0.5, 0.5, 0.5, 0.5, 0, 1.25, 1.25, 0]
self.entry_csx.port_pressure = [1.25, 0, 1.25, 0.5, 0.5, 0.5, 0.5, 0, 1.25, 1.25, 0]
self.entry_csx.port_pressure = [[5, "0156"], [1, "23"], [1, ["2D", "3D"]]]
# self.entry_tx2['port_pressure'] = [2.5, 2.5, 0, 0, 0.5, 0.5]
self.entry_tx2.port_pressure = [2.5, 2.5, 0, 0, 0.5, 0.5]
self.entry_tx2.port_pressure = [[5, "01"], [1, "45"]]
self.entry_tx2.operands[1].name = None
self.entry_tx2.operands[1].prefix = "x"
# self.entry_zen1['port_pressure'] = [1, 1, 1, 1, 0, 1, 0, 0, 0, 0.5, 1, 0.5, 1]
self.entry_zen1.port_pressure = [1, 1, 1, 1, 0, 1, 0, 0, 0, 0.5, 1, 0.5, 1]
self.entry_zen1.port_pressure = [
[4, "0123"],
[1, "4"],
@@ -73,8 +73,8 @@ class TestDBInterface(unittest.TestCase):
def test_invalid_add(self):
entry = instructionForm()
# with self.assertRaises(KeyError):
# MachineModel("csx").set_instruction_entry(entry)
with self.assertRaises(KeyError):
MachineModel("csx").set_instruction_entry(entry)
with self.assertRaises(TypeError):
MachineModel("csx").set_instruction()

1
tests/test_frontend.py
View File

@@ -9,7 +9,6 @@ import unittest
from osaca.frontend import Frontend
from osaca.parser import ParserAArch64, ParserX86ATT
from osaca.semantics import ArchSemantics, KernelDG, MachineModel, reduce_to_section
from osaca.parser.operand import Operand
class TestFrontend(unittest.TestCase):

7
tests/test_parser_AArch64.py
View File

@@ -9,7 +9,6 @@ import unittest
from pyparsing import ParseException
from osaca.parser import ParserAArch64, instructionForm
from osaca.parser.operand import Operand
from osaca.parser.directive import DirectiveOperand
from osaca.parser.memory import MemoryOperand
from osaca.parser.register import RegisterOperand
@@ -169,7 +168,7 @@ class TestParserAArch64(unittest.TestCase):
self.assertEqual(parsed_9.instruction, "ccmp")
self.assertEqual(parsed_9.operands[0].name, "0")
self.assertEqual(parsed_9.operands[0].prefix, "x")
self.assertEqual(parsed_9.operands[3]["condition"], "CC")
self.assertEqual(parsed_9.operands[3].ccode, "CC")
def test_parse_line(self):
line_comment = "// -- Begin main"
@@ -403,7 +402,7 @@ class TestParserAArch64(unittest.TestCase):
self.assertEqual(plist.operands, reg_list)
self.assertEqual(p_idx_range.operands, reg_list_idx)
self.assertEqual(p_idx_list.operands, reg_list_idx)
# self.assertEqual(p_single.operands, reg_list_single)
self.assertEqual(p_single.operands, reg_list_single)
def test_reg_dependency(self):
reg_1_1 = RegisterOperand(prefix_id="b", name="1")
@@ -472,7 +471,7 @@ class TestParserAArch64(unittest.TestCase):
def _get_condition(self, parser, condition):
return parser.process_operand(
parser.condition.parseString(condition, parseAll=True).asDict()
)["condition"]
).ccode
@staticmethod
def _find_file(name):

3
tests/test_parser_x86att.py
View File

@@ -11,7 +11,6 @@ from pyparsing import ParseException
from osaca.parser import ParserX86ATT, instructionForm
from osaca.parser.register import RegisterOperand
from osaca.parser.immediate import ImmediateOperand
from osaca.parser.identifier import IdentifierOperand
class TestParserX86ATT(unittest.TestCase):
@@ -222,7 +221,7 @@ class TestParserX86ATT(unittest.TestCase):
self.assertEqual(parsed_1, instruction_form_1)
self.assertEqual(parsed_2, instruction_form_2)
self.assertEqual(parsed_3, instruction_form_3)
# self.assertEqual(parsed_4, instruction_form_4)
self.assertEqual(parsed_4, instruction_form_4)
def test_parse_file(self):
parsed = self.parser.parse_file(self.triad_code)

11
tests/test_semantics.py
View File

@@ -10,7 +10,7 @@ from copy import deepcopy
import networkx as nx
from osaca.osaca import get_unmatched_instruction_ratio
from osaca.parser import AttrDict, ParserAArch64, ParserX86ATT
from osaca.parser import ParserAArch64, ParserX86ATT
from osaca.semantics import (
INSTR_flags,
ArchSemantics,
@@ -22,7 +22,6 @@ from osaca.semantics import (
from osaca.parser.register import RegisterOperand
from osaca.parser.memory import MemoryOperand
from osaca.parser.identifier import IdentifierOperand
from osaca.parser.operand import Operand
class TestSemanticTools(unittest.TestCase):
@@ -296,8 +295,8 @@ class TestSemanticTools(unittest.TestCase):
port_num = len(self.machine_model_csx["ports"])
for instruction_form in self.kernel_x86:
with self.subTest(instruction_form=instruction_form):
self.assertTrue(instruction_form.throughput != None)
self.assertTrue(instruction_form.latency != None)
self.assertTrue(instruction_form.throughput is not None)
self.assertTrue(instruction_form.latency is not None)
self.assertIsInstance(instruction_form.port_pressure, list)
self.assertEqual(len(instruction_form.port_pressure), port_num)
@@ -306,8 +305,8 @@ class TestSemanticTools(unittest.TestCase):
port_num = len(self.machine_model_tx2["ports"])
for instruction_form in self.kernel_AArch64:
with self.subTest(instruction_form=instruction_form):
self.assertTrue(instruction_form.throughput != None)
self.assertTrue(instruction_form.latency != None)
self.assertTrue(instruction_form.throughput is not None)
self.assertTrue(instruction_form.latency is not None)
self.assertIsInstance(instruction_form.port_pressure, list)
self.assertEqual(len(instruction_form.port_pressure), port_num)