diff --git a/osaca/data/isa/aarch64.yml b/osaca/data/isa/aarch64.yml index 6ba17e0..f941d31 100644 --- a/osaca/data/isa/aarch64.yml +++ b/osaca/data/isa/aarch64.yml @@ -50,50 +50,12 @@ instruction_forms: source: false destination: true - class: "memory" - base: "x" - offset: "imd" - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - source: true - destination: false - - name: "ldp" - operands: - - class: "register" - prefix: "d" - source: false - destination: true - - class: "register" - prefix: "d" - source: false - destination: true - - class: "memory" - base: "x" - offset: "imd" - index: ~ - scale: 1 - pre-indexed: false - post-indexed: true - source: true - destination: false - - name: "ldp" - operands: - - class: "register" - prefix: "d" - source: false - destination: true - - class: "register" - prefix: "d" - source: false - destination: true - - class: "memory" - base: "x" - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: true + base: "*" + offset: "*" + index: "*" + scale: "*" + pre-indexed: "*" + post-indexed: "*" source: true destination: false - name: "ldp" @@ -107,71 +69,14 @@ instruction_forms: source: false destination: true - class: "memory" - base: "x" - offset: "imd" - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false + base: "*" + offset: "*" + index: "*" + scale: "*" + pre-indexed: "*" + post-indexed: "*" source: true destination: false - - name: "ldp" - operands: - - class: "register" - prefix: "q" - source: false - destination: true - - class: "register" - prefix: "q" - source: false - destination: true - - class: "memory" - base: "x" - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: true - source: true - destination: false - - name: "ldp" - operands: - - class: "register" - prefix: "q" - source: false - destination: true - - class: "register" - prefix: "q" - source: false - destination: true - - class: "memory" - base: "x" - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - source: true - destination: false - - name: "ldp" - operands: - - class: "register" - prefix: "q" - source: false - destination: true - - class: "register" - prefix: "q" - source: false - destination: true - - class: "memory" - base: "x" - offset: "imd" - index: ~ - scale: 1 - pre-indexed: true - post-indexed: false - source: true - destination: true - name: "stp" operands: - class: "register" @@ -183,33 +88,14 @@ instruction_forms: source: true destination: false - class: "memory" - base: "x" - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false + base: "*" + offset: "*" + index: "*" + scale: "*" + pre-indexed: "*" + post-indexed: "*" source: false destination: true - - name: "stp" - operands: - - class: "register" - prefix: "d" - source: true - destination: false - - class: "register" - prefix: "d" - source: true - destination: false - - class: "memory" - base: "x" - offset: "imd" - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - source: false - destination: true - name: "stp" operands: - class: "register" @@ -221,50 +107,12 @@ instruction_forms: source: true destination: false - class: "memory" - base: "x" - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - source: false - destination: true - - name: "stp" - operands: - - class: "register" - prefix: "q" - source: true - destination: false - - class: "register" - prefix: "q" - source: true - destination: false - - class: "memory" - base: "x" - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: True - source: false - destination: true - - name: "stp" - operands: - - class: "register" - prefix: "q" - source: true - destination: false - - class: "register" - prefix: "q" - source: true - destination: false - - class: "memory" - base: "x" - offset: "imd" - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false + base: "*" + offset: "*" + index: "*" + scale: "*" + pre-indexed: "*" + post-indexed: "*" source: false destination: true - name: "str" @@ -274,12 +122,12 @@ instruction_forms: source: true destination: false - class: "memory" - base: "x" - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false + base: "*" + offset: "*" + index: "*" + scale: "*" + pre-indexed: "*" + post-indexed: "*" source: false destination: true - name: "str" @@ -289,27 +137,12 @@ instruction_forms: source: true destination: false - class: "memory" - base: "x" - offset: "imd" - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - source: false - destination: true - - name: "str" - operands: - - class: "register" - prefix: "d" - source: true - destination: false - - class: "memory" - base: "x" - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: true + base: "*" + offset: "*" + index: "*" + scale: "*" + pre-indexed: "*" + post-indexed: "*" source: false destination: true - name: "str" @@ -319,56 +152,11 @@ instruction_forms: source: true destination: false - class: "memory" - base: "x" - offset: ~ - index: "x" - scale: 1 - pre-indexed: false - post-indexed: false - source: false - destination: true - - name: "str" - operands: - - class: "register" - prefix: "q" - source: true - destination: false - - class: "memory" - base: "x" - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: true - source: false - destination: true - - name: "str" - operands: - - class: "register" - prefix: "x" - source: true - destination: false - - class: "memory" - base: "x" - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: true - source: false - destination: true - - name: "str" - operands: - - class: "register" - prefix: "x" - source: true - destination: false - - class: "memory" - base: "x" - offset: ~ - index: "x" - scale: 1 - pre-indexed: false - post-indexed: false + base: "*" + offset: "*" + index: "*" + scale: "*" + pre-indexed: "*" + post-indexed: "*" source: false destination: true diff --git a/osaca/semantics/isa_semantics.py b/osaca/semantics/isa_semantics.py index 8879106..7e97b77 100755 --- a/osaca/semantics/isa_semantics.py +++ b/osaca/semantics/isa_semantics.py @@ -3,6 +3,7 @@ from itertools import chain from osaca import utils from osaca.parser import AttrDict, ParserAArch64v81, ParserX86ATT + from .hw_model import MachineModel @@ -46,14 +47,19 @@ class ISASemantics(object): # if the instruction form doesn't have operands or is None, there's nothing to do if instruction_form['operands'] is None or instruction_form['instruction'] is None: instruction_form['semantic_operands'] = AttrDict( - {'source': [], 'destination': [], 'src_dst': []}) + {'source': [], 'destination': [], 'src_dst': []} + ) return # check if instruction form is in ISA yaml, otherwise apply standard operand assignment # (one dest, others source) isa_data = self._isa_model.get_instruction( instruction_form['instruction'], instruction_form['operands'] ) - if isa_data is None and instruction_form['instruction'][-1] in self.GAS_SUFFIXES: + if ( + isa_data is None + and self._isa == 'x86' + and instruction_form['instruction'][-1] in self.GAS_SUFFIXES + ): # Check for instruction without GAS suffix isa_data = self._isa_model.get_instruction( instruction_form['instruction'][:-1], instruction_form['operands'] @@ -80,6 +86,20 @@ class ISASemantics(object): if op['destination']: op_dict['destination'].append(operands[i]) continue + # post-process pre- and post-indexing for aarch64 memory operands + if self._isa == 'aarch64': + for operand in [op for op in op_dict['source'] if 'memory' in op]: + if ('post_indexed' in operand['memory'] and operand['memory']['post_indexed']) or ( + 'pre_indexed' in operand['memory'] and operand['memory']['pre_indexed'] + ): + op_dict['source'].remove(operand) + op_dict['src_dst'].append(operand) + for operand in [op for op in op_dict['destination'] if 'memory' in op]: + if ('post_indexed' in operand['memory'] and operand['memory']['post_indexed']) or ( + 'pre_indexed' in operand['memory'] and operand['memory']['pre_indexed'] + ): + op_dict['destination'].remove(operand) + op_dict['src_dst'].append(operand) # store operand list in dict and reassign operand key/value pair instruction_form['semantic_operands'] = AttrDict.convert_dict(op_dict) # assign LD/ST flags @@ -92,15 +112,19 @@ class ISASemantics(object): instruction_form['flags'] += [INSTR_FLAGS.HAS_ST] def _has_load(self, instruction_form): - for operand in chain(instruction_form['semantic_operands']['source'], - instruction_form['semantic_operands']['src_dst']): + for operand in chain( + instruction_form['semantic_operands']['source'], + instruction_form['semantic_operands']['src_dst'], + ): if 'memory' in operand: return True return False def _has_store(self, instruction_form): - for operand in chain(instruction_form['semantic_operands']['destination'], - instruction_form['semantic_operands']['src_dst']): + for operand in chain( + instruction_form['semantic_operands']['destination'], + instruction_form['semantic_operands']['src_dst'], + ): if 'memory' in operand: return True return False