diff --git a/README.rst b/README.rst index 3f7b2cd..4163795 100644 --- a/README.rst +++ b/README.rst @@ -92,7 +92,7 @@ The usage of OSACA can be listed as: Keep in mind you have to provide a (dummy) filename in anyway. --import MICROBENCH Import a given microbenchmark output file into the corresponding architecture instruction database. - Define the type of microbenchmark either as "ibench", "asmbench" or "uopsinfo". + Define the type of microbenchmark either as "ibench" or "asmbench". --insert-marker OSACA calls the Kerncraft module for the interactively insertion of `IACA `_ marker in suggested assembly blocks. --export-graph EXPORT_PATH diff --git a/osaca/data/bdw.yml b/osaca/data/bdw.yml new file mode 100644 index 0000000..ac0fc32 --- /dev/null +++ b/osaca/data/bdw.yml @@ -0,0 +1,14084 @@ +osaca_version: 0.3.1.dev1 +micro_architecture: Intel Broadwell +arch_code: BDW +isa: x86 +ROB_size: 192 +retired_uOps_per_cycle: 4 +scheduler_size: 64 +hidden_loads: false +load_latency: {gpr: 4.0, xmm: 4.0, ymm: 4.0} +load_throughput: +- {base: gpr, index: ~, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: ~, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: ~, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: ~, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: gpr, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: gpr, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: gpr, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: gpr, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +ports: ['0', 0DV, '1', '2', 2D, '3', 3D, '4', '5', '6', '7'] +port_model_scheme: | + ┌------------------------------------------------------------------------┐ + | 64 entry unified scheduler | + └------------------------------------------------------------------------┘ + 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | + ▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼ + ┌-------┐ ┌-------┐ ┌-----┐ ┌-----┐ ┌-----┐ ┌-------┐ ┌--------┐ ┌------┐ + | ALU | | ALU | | LD | | LD | | ST | | ALU | | ALU & | |SIMPLE| + └-------┘ └-------┘ └-----┘ └-----┘ └-----┘ └-------┘ | Shift | | AGU | + ┌-------┐ ┌-------┐ ┌-----┐ ┌-----┐ ┌-------┐ └--------┘ └------┘ + | 2ND | | Fast | | AGU | | AGU | | Fast | ┌--------┐ + | BRANCH| | LEA | └-----┘ └-----┘ | LEA | | BRANCH | + └-------┘ └-------┘ └-------┘ └--------┘ + ┌-------┐ ┌-------┐ ┌-------┐ + |AVX DIV| |AVX FMA| | AVX | + └-------┘ └-------┘ | ALU | + ┌-------┐ ┌-------┐ └-------┘ + |AVX FMA| |AVX MUL| + └-------┘ └-------┘ + ┌-------┐ ┌-------┐ + |AVX MUL| |AVX ADD| + └-------┘ └-------┘ +instruction_forms: +- name: MOV + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: MOVSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: MOVAPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: MOVUPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: MOVSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: MOVDQU + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: MOVQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: MOVAPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: MOVUPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: MOVDQA + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: MOVQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: VMOVSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: VMOVSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: VMOVQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: VMOVDQA + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: VMOVDQA + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: VMOVDQU + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: VMOVDQU + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: VMOVUPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: VMOVUPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: VMOVUPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: VMOVUPD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: VMOVAPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: VMOVAPD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: VMOVAPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: VMOVAPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 + +- name: MOV + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: gpr + latency: 4.0 # 1*p23+1*p2D3D + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVSS + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVAPS + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVUPS + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVSD + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVDQU + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVQ + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVAPD + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVUPD + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVDQA + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVQ + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVQ + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVDQA + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVDQA + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVDQU + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVDQU + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVUPS + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVUPS + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVUPD + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVUPD + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVAPD + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVAPD + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVAPS + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVAPS + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOV + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 # 1*p23+1*p2D3D + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVSS + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVAPS + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVUPS + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVSD + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVDQU + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVQ + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVAPD + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVUPD + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVDQA + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVQ + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVQ + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVDQA + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVDQA + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVDQU + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVDQU + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVUPS + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVUPS + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVUPD + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVUPD + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVAPD + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVAPD + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVAPS + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVAPS + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOV + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 # 1*p23+1*p2D3D + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVSS + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVAPS + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVUPS + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVSD + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVDQU + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVQ + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVAPD + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVUPD + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVDQA + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: MOVQ + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVQ + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVDQA + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVDQA + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVDQU + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVDQU + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVUPS + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVUPS + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVUPD + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVUPD + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVAPD + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVAPD + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVAPS + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 +- name: VMOVAPS + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'],[1, [2D, 3D]]] + throughput: 0.5 + uops: 1 + + +- name: MOV + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ # 1*p23+1*4 + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVSS + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVAPS + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVUPS + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVSD + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVDQU + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVQ + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVAPD + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVUPD + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVDQA + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVQ + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVQ + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVDQA + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVDQA + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVDQU + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVDQU + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVUPS + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVUPS + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVUPD + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVUPD + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVAPD + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVAPD + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVAPS + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVAPS + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOV + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ # 1*p23+1*4 + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVSS + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVAPS + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVUPS + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVSD + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVDQU + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVQ + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVAPD + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVUPD + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVDQA + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: MOVQ + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVQ + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVDQA + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVDQA + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVDQU + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVDQU + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVUPS + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVUPS + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVUPD + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVUPD + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVAPD + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVAPD + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVAPS + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 +- name: VMOVAPS + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 0.5 + uops: 1 + + +- name: SLDT + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0156'], [2, '06'], [1, '1']] + throughput: 1.25 + uops: 5 +- name: POPFW + operands: [] + latency: ~ + port_pressure: [[11, '0156'], [1, '23']] + throughput: 2.75 + uops: 10 +- name: CALL + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: OUTSW + operands: [] + latency: ~ + port_pressure: [[7, '0'], [2, '01'], [4, '0156'], [22, '06'], [13, '1'], [1, '15'], [1, '23'], [1, '237'], [1, '4'], [6, + '5']] + throughput: 20.0 + uops: 58 +- name: OUTSB + operands: [] + latency: ~ + port_pressure: [[7, '0'], [2, '01'], [4, '0156'], [22, '06'], [13, '1'], [1, '15'], [1, '23'], [1, '237'], [1, '4'], [6, + '5']] + throughput: 20.0 + uops: 58 +- name: OUTSD + operands: [] + latency: ~ + port_pressure: [[7, '0'], [2, '01'], [4, '0156'], [22, '06'], [13, '1'], [1, '15'], [1, '23'], [1, '237'], [1, '4'], [6, + '5']] + throughput: 20.0 + uops: 58 +- name: JNLE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: WRMSR + operands: [] + latency: ~ + port_pressure: [[11, '0'], [56, '06'], [14, '1'], [13, '15'], [1, '4'], [12, '5']] + throughput: 39.0 + uops: 107 +- name: REPE SCASW + operands: [] + latency: ~ + port_pressure: [[11, '0156'], [5, '06'], [1, '15'], [1, '23']] + throughput: 5.25 + uops: 12 +- name: REPE SCASD + operands: [] + latency: ~ + port_pressure: [[11, '0156'], [5, '06'], [1, '15'], [1, '23']] + throughput: 5.25 + uops: 12 +- name: REPE SCASB + operands: [] + latency: ~ + port_pressure: [[11, '0156'], [5, '06'], [1, '15'], [1, '23']] + throughput: 5.25 + uops: 12 +- name: REX64 REPE SCASB + operands: [] + latency: ~ + port_pressure: [[11, '0156'], [5, '06'], [1, '15'], [1, '23']] + throughput: 5.25 + uops: 12 +- name: JNS + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JL + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNP + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNZ + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNB + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNO + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNL + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: CMC + operands: [] + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: CMP + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: CMP + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX CMP + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: CMOVLE + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: LAHF + operands: [] + latency: 0 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: CBW + operands: [] + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: PUSHFW + operands: [] + latency: 9 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 4 +- name: NOT + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX NOT + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: NOP + operands: [] + latency: ~ + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: INC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX INC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: CMPSW + operands: [] + latency: 4 + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: CMPSB + operands: [] + latency: 4 + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: CMPSD + operands: [] + latency: 4 + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: SETB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SETL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SETO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BSR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SETP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: OUT + operands: + - class: register + name: gpr + - class: immediate + imd: int + latency: ~ + port_pressure: [[9, '0156'], [9, '06'], [2, '23'], [1, '237'], [1, '4'], [1, '5']] + throughput: 6.75 + uops: 55 +- name: OUT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[9, '0156'], [9, '06'], [2, '23'], [1, '237'], [1, '4'], [1, '5']] + throughput: 6.75 + uops: 54 +- name: CMOVNLE + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SBB + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SBB + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 1 +- name: LODSB + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: LODSW + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: LODSD + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '23']] + throughput: 0.5 + uops: 2 +- name: JNBE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: STD + operands: [] + latency: ~ + port_pressure: [[5, '0156'], [1, '06']] + throughput: 1.75 + uops: 3 +- name: STOSD + operands: [] + latency: 0 + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: XOR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX XOR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: SAR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SAR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: STC + operands: [] + latency: ~ + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: STI + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [4, '06'], [1, '1']] + throughput: 2.25 + uops: 6 +- name: STR + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[2, '06'], [1, '1']] + throughput: 1.0 + uops: 5 +- name: STOSB + operands: [] + latency: 0 + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: REPE LODSW + operands: [] + latency: ~ + port_pressure: [[9, '06'], [1, '1']] + throughput: 4.5 + uops: 10 +- name: REPNE LODSW + operands: [] + latency: ~ + port_pressure: [[9, '06'], [1, '1']] + throughput: 4.5 + uops: 10 +- name: RDMSR + operands: [] + latency: ~ + port_pressure: [[1, '0'], [4, '01'], [10, '015'], [38, '06'], [5, '1'], [6, '15'], [4, '5']] + throughput: 25.333333333333336 + uops: 68 +- name: REPE LODSB + operands: [] + latency: ~ + port_pressure: [[9, '06'], [1, '1']] + throughput: 4.5 + uops: 10 +- name: REX64 REPE LODSB + operands: [] + latency: ~ + port_pressure: [[9, '06'], [1, '1']] + throughput: 4.5 + uops: 10 +- name: REPNE LODSB + operands: [] + latency: ~ + port_pressure: [[9, '06'], [1, '1']] + throughput: 4.5 + uops: 10 +- name: REX64 REPNE LODSB + operands: [] + latency: ~ + port_pressure: [[9, '06'], [1, '1']] + throughput: 4.5 + uops: 10 +- name: REPE LODSD + operands: [] + latency: ~ + port_pressure: [[9, '06'], [1, '1']] + throughput: 4.5 + uops: 10 +- name: REPNE LODSD + operands: [] + latency: ~ + port_pressure: [[9, '06'], [1, '1']] + throughput: 4.5 + uops: 10 +- name: IDIV + operands: + - class: register + name: gpr + latency: 24 + port_pressure: [[2, '0'], [3, '0156'], [2, '1'], [2, '5'], [6, [0DV]]] + throughput: 6.0 + uops: 9 +- name: REX IDIV + operands: + - class: register + name: gpr + latency: 24 + port_pressure: [[2, '0'], [3, '0156'], [2, '1'], [2, '5'], [6, [0DV]]] + throughput: 6.0 + uops: 9 +- name: REPNE CMPSB + operands: [] + latency: ~ + port_pressure: [[10, '06'], [1, '1'], [1, '5']] + throughput: 5.0 + uops: 12 +- name: REX64 REPNE CMPSB + operands: [] + latency: ~ + port_pressure: [[10, '06'], [1, '1'], [1, '5']] + throughput: 5.0 + uops: 12 +- name: REPNE CMPSD + operands: [] + latency: ~ + port_pressure: [[10, '06'], [1, '1'], [1, '5']] + throughput: 5.0 + uops: 12 +- name: SETS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SHR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SHR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: '{store} SHRD' + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: MOVSD + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [2, '23'], [1, '4']] + throughput: 1.0 + uops: 5 +- name: MOVSB + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [2, '23'], [1, '4']] + throughput: 1.0 + uops: 5 +- name: MOVSX + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX MOVSX + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: MOVSW + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [2, '23'], [1, '4']] + throughput: 1.0 + uops: 5 +- name: SHL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SHL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BTS + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BTS + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BTR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BTR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: LOOP + operands: + - class: identifier + latency: 2 + port_pressure: [[2, '0156'], [4, '06'], [1, '15']] + throughput: 2.5 + uops: 8 +- name: BTC + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BTC + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: WBINVD + operands: [] + latency: ~ + port_pressure: [[78778, '0'], [55532, '06'], [113455, '1'], [132069, '4'], [38166, '5'], [1, [0DV]]] + throughput: 132069.0 + uops: 418000 +- name: JBE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: MUL + operands: + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 3 +- name: REX MUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PUSH + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '1'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: PUSHW + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: PUSH + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: PUSHW + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '1'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: SETNO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SETNL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: CLI + operands: [] + latency: ~ + port_pressure: [[2, '06'], [1, '1']] + throughput: 1.0 + uops: 3 +- name: CLD + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '06']] + throughput: 1.0 + uops: 3 +- name: SETNB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: CLC + operands: [] + latency: ~ + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: SETNZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SETNS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SETNP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: LLDT + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0156'], [7, '06'], [3, '1'], [1, '23'], [1, '237'], [1, '4']] + throughput: 3.75 + uops: 14 +- name: RET + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: 5 +- name: RET + operands: [] + latency: ~ + port_pressure: [[3, '06']] + throughput: 1.5 + uops: 3 +- name: SETNBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 2 +- name: REX SETNBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 2 +- name: REPE INSW + operands: [] + latency: ~ + port_pressure: [[3, '0'], [1, '01'], [5, '015'], [2, '0156'], [17, '06'], [10, '1'], [5, '5']] + throughput: 14.166666666666668 + uops: 43 +- name: REPNE INSW + operands: [] + latency: ~ + port_pressure: [[3, '0'], [1, '01'], [5, '015'], [2, '0156'], [17, '06'], [10, '1'], [5, '5']] + throughput: 14.166666666666668 + uops: 43 +- name: REPE INSB + operands: [] + latency: ~ + port_pressure: [[4, '0'], [1, '01'], [4, '015'], [3, '0156'], [16, '06'], [10, '1'], [5, '5']] + throughput: 14.583333333333332 + uops: 43 +- name: REX64 REPE INSB + operands: [] + latency: ~ + port_pressure: [[4, '0'], [1, '01'], [4, '015'], [3, '0156'], [16, '06'], [10, '1'], [5, '5']] + throughput: 14.583333333333332 + uops: 43 +- name: REPNE INSB + operands: [] + latency: ~ + port_pressure: [[4, '0'], [1, '01'], [4, '015'], [3, '0156'], [16, '06'], [10, '1'], [5, '5']] + throughput: 14.583333333333332 + uops: 43 +- name: REX64 REPNE INSB + operands: [] + latency: ~ + port_pressure: [[4, '0'], [1, '01'], [4, '015'], [3, '0156'], [16, '06'], [10, '1'], [5, '5']] + throughput: 14.583333333333332 + uops: 43 +- name: REPE INSD + operands: [] + latency: ~ + port_pressure: [[4, '0'], [5, '015'], [3, '0156'], [16, '06'], [10, '1'], [5, '5']] + throughput: 14.416666666666668 + uops: 43 +- name: REX64 REPE INSD + operands: [] + latency: ~ + port_pressure: [[4, '0'], [5, '015'], [3, '0156'], [16, '06'], [10, '1'], [5, '5']] + throughput: 14.416666666666668 + uops: 43 +- name: REPNE INSD + operands: [] + latency: ~ + port_pressure: [[4, '0'], [5, '015'], [3, '0156'], [16, '06'], [10, '1'], [5, '5']] + throughput: 14.416666666666668 + uops: 43 +- name: REX64 REPNE INSD + operands: [] + latency: ~ + port_pressure: [[4, '0'], [5, '015'], [3, '0156'], [16, '06'], [10, '1'], [5, '5']] + throughput: 14.416666666666668 + uops: 43 +- name: REPE STOSD + operands: [] + latency: ~ + port_pressure: [[17, '015'], [7, '0156'], [5, '06'], [16, '23'], [16, '4']] + throughput: 16.0 + uops: 65 +- name: REPNE STOSD + operands: [] + latency: ~ + port_pressure: [[17, '015'], [7, '0156'], [5, '06'], [16, '23'], [16, '4']] + throughput: 16.0 + uops: 65 +- name: VERR + operands: + - class: register + name: gpr + latency: 60 + port_pressure: [[2, '0'], [3, '06'], [5, '1'], [3, '5']] + throughput: 5.0 + uops: 13 +- name: REPE STOSB + operands: [] + latency: ~ + port_pressure: [[7, '01'], [15, '015'], [2, '0156'], [19, '06'], [9, '15'], [11, '23'], [9, '4'], [2, '5']] + throughput: 18.5 + uops: 76 +- name: REX64 REPE STOSB + operands: [] + latency: ~ + port_pressure: [[7, '01'], [15, '015'], [2, '0156'], [19, '06'], [9, '15'], [11, '23'], [9, '4'], [2, '5']] + throughput: 18.5 + uops: 76 +- name: REPNE STOSB + operands: [] + latency: ~ + port_pressure: [[7, '01'], [15, '015'], [2, '0156'], [19, '06'], [9, '15'], [11, '23'], [9, '4'], [2, '5']] + throughput: 18.5 + uops: 76 +- name: REX64 REPNE STOSB + operands: [] + latency: ~ + port_pressure: [[7, '01'], [15, '015'], [2, '0156'], [19, '06'], [9, '15'], [11, '23'], [9, '4'], [2, '5']] + throughput: 18.5 + uops: 76 +- name: REPE STOSW + operands: [] + latency: ~ + port_pressure: [[1, '01'], [16, '015'], [7, '0156'], [5, '06'], [16, '23'], [16, '4']] + throughput: 16.0 + uops: 65 +- name: REPNE STOSW + operands: [] + latency: ~ + port_pressure: [[1, '01'], [16, '015'], [7, '0156'], [5, '06'], [16, '23'], [16, '4']] + throughput: 16.0 + uops: 65 +- name: CWD + operands: [] + latency: 2 + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 2 +- name: TEST + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX TEST + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: TEST + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX TEST + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: JZ + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: SCASW + operands: [] + latency: 1 + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: JP + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JS + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JO + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: SCASD + operands: [] + latency: 1 + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: SCASB + operands: [] + latency: 1 + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: JB + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: RDPMC + operands: [] + latency: ~ + port_pressure: [[2, '01'], [10, '015'], [17, '06'], [1, '1'], [1, '15'], [3, '5']] + throughput: 12.833333333333334 + uops: 34 +- name: CMOVNP + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: RETFW + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: RETF + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: RETFQ + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: RETFW + operands: [] + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: RETF + operands: [] + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: RETFQ + operands: [] + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: ENTERW + operands: + - class: immediate + imd: int + - class: immediate + imd: int + latency: ~ + port_pressure: [[3, '0156'], [1, '06'], [1, '1'], [1, '237'], [1, '4']] + throughput: 1.75 + uops: 12 +- name: ENTER + operands: + - class: immediate + imd: int + - class: immediate + imd: int + latency: ~ + port_pressure: [[3, '0156'], [1, '06'], [1, '1'], [1, '237'], [1, '4']] + throughput: 1.75 + uops: 12 +- name: REPNE SCASB + operands: [] + latency: ~ + port_pressure: [[19, '0156'], [9, '06'], [1, '15'], [3, '23']] + throughput: 9.25 + uops: 12 +- name: REX64 REPNE SCASB + operands: [] + latency: ~ + port_pressure: [[19, '0156'], [9, '06'], [1, '15'], [3, '23']] + throughput: 9.25 + uops: 12 +- name: REPNE SCASD + operands: [] + latency: ~ + port_pressure: [[9, '06'], [1, '1'], [1, '23'], [1, '5']] + throughput: 4.5 + uops: 12 +- name: REPNE SCASW + operands: [] + latency: ~ + port_pressure: [[15, '0156'], [7, '06'], [1, '15'], [2, '23']] + throughput: 7.25 + uops: 12 +- name: LEAVEW + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '23']] + throughput: 0.5 + uops: 4 +- name: LEAVE + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: REPE OUTSW + operands: [] + latency: ~ + port_pressure: [[5, '0'], [3, '015'], [4, '0156'], [15, '06'], [10, '1'], [5, '5']] + throughput: 14.5 + uops: 42 +- name: REPNE OUTSW + operands: [] + latency: ~ + port_pressure: [[5, '0'], [3, '015'], [4, '0156'], [15, '06'], [10, '1'], [5, '5']] + throughput: 14.5 + uops: 42 +- name: REPE OUTSB + operands: [] + latency: ~ + port_pressure: [[4, '0'], [1, '01'], [3, '015'], [3, '0156'], [16, '06'], [10, '1'], [5, '5']] + throughput: 14.25 + uops: 42 +- name: REX64 REPE OUTSB + operands: [] + latency: ~ + port_pressure: [[4, '0'], [1, '01'], [3, '015'], [3, '0156'], [16, '06'], [10, '1'], [5, '5']] + throughput: 14.25 + uops: 42 +- name: REPNE OUTSB + operands: [] + latency: ~ + port_pressure: [[4, '0'], [1, '01'], [3, '015'], [3, '0156'], [16, '06'], [10, '1'], [5, '5']] + throughput: 14.25 + uops: 42 +- name: REX64 REPNE OUTSB + operands: [] + latency: ~ + port_pressure: [[4, '0'], [1, '01'], [3, '015'], [3, '0156'], [16, '06'], [10, '1'], [5, '5']] + throughput: 14.25 + uops: 42 +- name: REPE OUTSD + operands: [] + latency: ~ + port_pressure: [[4, '0'], [1, '01'], [3, '015'], [3, '0156'], [15, '06'], [10, '1'], [5, '5']] + throughput: 13.75 + uops: 42 +- name: REX64 REPE OUTSD + operands: [] + latency: ~ + port_pressure: [[4, '0'], [1, '01'], [3, '015'], [3, '0156'], [15, '06'], [10, '1'], [5, '5']] + throughput: 13.75 + uops: 42 +- name: REPNE OUTSD + operands: [] + latency: ~ + port_pressure: [[4, '0'], [1, '01'], [3, '015'], [3, '0156'], [15, '06'], [10, '1'], [5, '5']] + throughput: 13.75 + uops: 42 +- name: REX64 REPNE OUTSD + operands: [] + latency: ~ + port_pressure: [[4, '0'], [1, '01'], [3, '015'], [3, '0156'], [15, '06'], [10, '1'], [5, '5']] + throughput: 13.75 + uops: 42 +- name: XLAT + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: SMSW + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0156'], [2, '06'], [1, '5']] + throughput: 1.25 + uops: 4 +- name: AND + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX AND + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: MOV + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX MOV + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: JLE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: CPUID + operands: [] + latency: ~ + port_pressure: [[5, '0156'], [2, '06'], [1, '5']] + throughput: 2.25 + uops: 52 +- name: RDTSC + operands: [] + latency: ~ + port_pressure: [[5, '0156'], [2, '06'], [1, '5']] + throughput: 2.25 + uops: 13 +- name: CDQ + operands: [] + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: INSB + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [2, '06'], [1, '23'], [1, '237'], [1, '4'], [1, '5']] + throughput: 1.5 + uops: 60 +- name: INSD + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [2, '06'], [1, '23'], [1, '237'], [1, '4'], [1, '5']] + throughput: 1.5 + uops: 60 +- name: IMUL + operands: + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 3 +- name: REX IMUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: IMUL + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: RCR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '0156'], [1, '06']] + throughput: 1.0 + uops: 3 +- name: REX RCR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '0156'], [1, '06']] + throughput: 1.0 + uops: 3 +- name: RCL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '0156'], [1, '06']] + throughput: 1.0 + uops: 3 +- name: REX RCL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '0156'], [1, '06']] + throughput: 1.0 + uops: 3 +- name: INSW + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [2, '06'], [1, '23'], [1, '237'], [1, '4'], [1, '5']] + throughput: 1.5 + uops: 60 +- name: STOSW + operands: [] + latency: 0 + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: REPE MOVSD + operands: [] + latency: ~ + port_pressure: [[16, '015'], [7, '0156'], [6, '06'], [1, '15'], [32, '23'], [16, '4']] + throughput: 16.0 + uops: 82 +- name: REPNE MOVSD + operands: [] + latency: ~ + port_pressure: [[16, '015'], [7, '0156'], [6, '06'], [1, '15'], [32, '23'], [16, '4']] + throughput: 16.0 + uops: 82 +- name: REPE MOVSB + operands: [] + latency: ~ + port_pressure: [[11, '01'], [16, '015'], [27, '06'], [2, '1'], [10, '15'], [17, '23'], [7, '4']] + throughput: 24.333333333333332 + uops: 90 +- name: REX64 REPE MOVSB + operands: [] + latency: ~ + port_pressure: [[11, '01'], [16, '015'], [27, '06'], [2, '1'], [10, '15'], [17, '23'], [7, '4']] + throughput: 24.333333333333332 + uops: 90 +- name: REPNE MOVSB + operands: [] + latency: ~ + port_pressure: [[11, '01'], [16, '015'], [27, '06'], [2, '1'], [10, '15'], [17, '23'], [7, '4']] + throughput: 24.333333333333332 + uops: 90 +- name: REX64 REPNE MOVSB + operands: [] + latency: ~ + port_pressure: [[11, '01'], [16, '015'], [27, '06'], [2, '1'], [10, '15'], [17, '23'], [7, '4']] + throughput: 24.333333333333332 + uops: 90 +- name: REPE MOVSW + operands: [] + latency: ~ + port_pressure: [[17, '015'], [6, '0156'], [6, '06'], [1, '15'], [32, '23'], [16, '4']] + throughput: 16.0 + uops: 82 +- name: REPNE MOVSW + operands: [] + latency: ~ + port_pressure: [[17, '015'], [6, '0156'], [6, '06'], [1, '15'], [32, '23'], [16, '4']] + throughput: 16.0 + uops: 82 +- name: IN + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: ~ + port_pressure: [[10, '0156'], [9, '06'], [3, '23'], [1, '5']] + throughput: 7.0 + uops: 61 +- name: IN + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[10, '0156'], [9, '06'], [3, '23'], [1, '5']] + throughput: 7.0 + uops: 60 +- name: CMOVNZ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: CMOVNS + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: CMOVNO + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: CMOVNL + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: CMOVNB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: CMOVO + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BT + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: POP + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: 1 +- name: JRCXZ + operands: + - class: identifier + latency: ~ + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 2 +- name: 'SHLD' + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SAHF + operands: [] + latency: 0 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: CMOVZ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: CMOVP + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: CMOVS + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: CMOVL + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: CMOVB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: LMSW + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[3, '015'], [14, '06'], [1, '1'], [1, '23'], [2, '4'], [4, '5']] + throughput: 8.0 + uops: 25 +- name: REPE CMPSD + operands: [] + latency: ~ + port_pressure: [[10, '06'], [1, '1'], [1, '5']] + throughput: 5.0 + uops: 12 +- name: OR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX OR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REPE CMPSB + operands: [] + latency: ~ + port_pressure: [[10, '06'], [1, '1'], [1, '5']] + throughput: 5.0 + uops: 12 +- name: REX64 REPE CMPSB + operands: [] + latency: ~ + port_pressure: [[10, '06'], [1, '1'], [1, '5']] + throughput: 5.0 + uops: 12 +- name: REPE CMPSW + operands: [] + latency: ~ + port_pressure: [[10, '06'], [1, '1'], [1, '5']] + throughput: 5.0 + uops: 12 +- name: CLTS + operands: [] + latency: ~ + port_pressure: [[4, '06'], [2, '5']] + throughput: 2.0 + uops: 7 +- name: MOVZX + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX MOVZX + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 0 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REPNE CMPSW + operands: [] + latency: ~ + port_pressure: [[10, '06'], [1, '1'], [1, '5']] + throughput: 5.0 + uops: 12 +- name: ROL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: REX ROL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: VERW + operands: + - class: register + name: gpr + latency: 61 + port_pressure: [[2, '0'], [3, '06'], [4, '1'], [4, '5']] + throughput: 4.0 + uops: 13 +- name: JMP + operands: + - class: register + name: gpr + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JMP + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: ROR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: REX ROR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: SETLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SUB + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX SUB + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: NEG + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX NEG + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: SETNLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: ADD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX ADD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: ADC + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX ADC + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 1 +- name: CWDE + operands: [] + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: BSF + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SETZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: DEC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX DEC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: SETBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 2 +- name: REX SETBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 2 +- name: BSWAP + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '06'], [1, '15']] + throughput: 0.5 + uops: 2 +- name: UNPCKHPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: DIVS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 11 + port_pressure: [[1, '0'], [5, [0DV]]] + throughput: 5.0 + uops: 1 +- name: ADDSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTPI2PS + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CMPSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ANDNPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CVTTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: ORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MOVMSKPS + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: DIVS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 11 + port_pressure: [[1, '0'], [2, [0DV]]] + throughput: 2.0 + uops: 1 +- name: RCPSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: MOVLHPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: SQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: SUBSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CMPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: XORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: SUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SHUFPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MINSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTSI2SS + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: SFENCE + operands: [] + latency: ~ + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: RSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: UNPCKLPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MULSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: SQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: CVTTPS2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: RSQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: MINPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTPS2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: MULPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: CVTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: ANDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MAXPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: MOVHLPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: COMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: RCPPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: MAXSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: UCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: UNPCKHPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PUNPCKHDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: CVTTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: DIVD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[1, '0'], [8, [0DV]]] + throughput: 8.0 + uops: 1 +- name: PCMPGTW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTPI2PD + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PACKUSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MASKMOVDQU + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 10 +- name: ANDNPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSLLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: UNPCKLPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSADBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PADDUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PACKSSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMULLW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: DIVD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[1, '0'], [4, [0DV]]] + throughput: 4.0 + uops: 1 +- name: PCMPEQW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPEQB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPEQD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PUNPCKLWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: ORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PXOR + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CMPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: MOVQ2DQ + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSUBB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMAXSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSRLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PADDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CMPSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PMULHUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: MINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: ADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: POR + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CVTSD2SS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PSLLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: SQRTSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [13, [0DV]]] + throughput: 13.0 + uops: 1 +- name: PSLLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: CVTSI2SD + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PSLLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMOVMSKB + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PUNPCKLDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MULSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PANDN + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: SHUFPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: SUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SQRTPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [13, [0DV]]] + throughput: 13.0 + uops: 1 +- name: ANDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMULHW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMINSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PSHUFD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CVTSS2SD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: XORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: MINPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ADDSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PSRLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: SUBSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PADDSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: LFENCE + operands: [] + latency: ~ + port_pressure: [[2, '0156']] + throughput: 0.5 + uops: 2 +- name: CVTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: CVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: MOVD + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MOVD + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: MULPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: MOVDQ2Q + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '01'], [1, '015']] + throughput: 0.8333333333333333 + uops: 2 +- name: MOVMSKPD + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMULUDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMULUDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMADDWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PEXTRW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PAND + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CVTDQ2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PMAXUB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CVTPD2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: CVTPD2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: MFENCE + operands: [] + latency: ~ + port_pressure: [[2, '0156']] + throughput: 0.5 + uops: 3 +- name: PSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MAXPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PMINUB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PINSRW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: '{store} MOVDQA' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PAVGW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PAVGB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSRAW + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: COMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PSRAD + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PACKSSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PUNPCKLBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: UCOMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTTPD2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: FCHS + operands: [] + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: ~ +- name: FUCOM + operands: [] + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: FLDL2T + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FLDL2E + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FYL2X + operands: [] + latency: ~ + port_pressure: [[2, '0'], [2, '01'], [2, '0156'], [2, '06'], [3, '1']] + throughput: 4.5 + uops: ~ +- name: FADDP + operands: [] + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: FXTRACT + operands: [] + latency: ~ + port_pressure: [[1, '01'], [2, '1']] + throughput: 2.5 + uops: ~ +- name: FCOMPP + operands: [] + latency: ~ + port_pressure: [[1, '01'], [1, '1']] + throughput: 1.5 + uops: ~ +- name: FYL2XP1 + operands: [] + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: FRNDINT + operands: [] + latency: ~ + port_pressure: [[5, '0'], [2, '01'], [3, '0156'], [2, '06'], [5, '1'], [1, '5']] + throughput: 7.75 + uops: ~ +- name: FNCLEX + operands: [] + latency: ~ + port_pressure: [[4, '0156']] + throughput: 1.0 + uops: ~ +- name: FPTAN + operands: [] + latency: ~ + port_pressure: [[3, '0'], [2, '1']] + throughput: 3.0 + uops: ~ +- name: FCOS + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '0156'], [3, '06'], [5, '1'], [2, '5']] + throughput: 9.5 + uops: ~ +- name: FSCALE + operands: [] + latency: ~ + port_pressure: [[1, '0'], [3, '0156'], [1, '06'], [2, '1']] + throughput: 2.75 + uops: ~ +- name: FXAM + operands: [] + latency: ~ + port_pressure: [[2, '1']] + throughput: 2.0 + uops: ~ +- name: FPREM1 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FNINIT + operands: [] + latency: ~ + port_pressure: [[3, '01'], [6, '0156'], [6, '5']] + throughput: 7.5 + uops: ~ +- name: FNOP + operands: [] + latency: ~ + port_pressure: [[1, '01']] + throughput: 0.5 + uops: ~ +- name: FLDPI + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FNSTSW + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '0156']] + throughput: 1.25 + uops: ~ +- name: FWAIT + operands: [] + latency: ~ + port_pressure: [[2, '0156']] + throughput: 0.5 + uops: ~ +- name: F2XM1 + operands: [] + latency: ~ + port_pressure: [[3, '0'], [3, '0156'], [3, '06'], [3, '1']] + throughput: 5.25 + uops: ~ +- name: FPREM + operands: [] + latency: ~ + port_pressure: [[1, '0'], [2, '01'], [1, '0156'], [1, '1']] + throughput: 2.25 + uops: ~ +- name: FINCSTP + operands: [] + latency: ~ + port_pressure: [[1, '01']] + throughput: 0.5 + uops: ~ +- name: FTST + operands: [] + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: FPATAN + operands: [] + latency: ~ + port_pressure: [[25, '0'], [2, '01'], [10, '0156'], [5, '06'], [10, '1'], [3, '5']] + throughput: 31.0 + uops: ~ +- name: FABS + operands: [] + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: ~ +- name: FSIN + operands: [] + latency: ~ + port_pressure: [[8, '0'], [3, '0156'], [4, '06'], [5, '1'], [2, '5']] + throughput: 10.75 + uops: ~ +- name: FLDLN2 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FXCH + operands: [] + latency: ~ + port_pressure: [[2, '0'], [5, '0156'], [4, '06'], [1, '1']] + throughput: 5.25 + uops: ~ +- name: FDECSTP + operands: [] + latency: ~ + port_pressure: [[2, '01']] + throughput: 1.0 + uops: ~ +- name: FLDLG2 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FLDZ + operands: [] + latency: ~ + port_pressure: [[1, '01']] + throughput: 0.5 + uops: ~ +- name: FUCOMPP + operands: [] + latency: ~ + port_pressure: [[1, '01'], [1, '1']] + throughput: 1.5 + uops: ~ +- name: FLD1 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '01']] + throughput: 1.5 + uops: ~ +- name: FSINCOS + operands: [] + latency: ~ + port_pressure: [[2, '0'], [1, '01'], [3, '1']] + throughput: 3.5 + uops: ~ +- name: PUNPCKHDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PCMPGTW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PACKUSWB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [2, '5']] + throughput: 2.25 + uops: 3 +- name: PSUBD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSADBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PADDUSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDUSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PACKSSDW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [2, '5']] + throughput: 2.25 + uops: 3 +- name: PMULLW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PCMPEQW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPEQB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPEQD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLWD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PADDSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PXOR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PSUBB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBUSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMAXSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMULHUW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: POR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PSLLD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLW + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLQ + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBUSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMOVMSKB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PUNPCKLDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PANDN + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PMULHW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMINSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSHUFW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSRLQ + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLW + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PADDSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: MOVD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: EMMS + operands: [] + latency: ~ + port_pressure: [[8, '01'], [21, '015'], [1, '0156'], [1, '15']] + throughput: 11.75 + uops: 31 +- name: PUNPCKHBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMADDWD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PEXTRW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PAND + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PMAXUB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHWD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMINUB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PINSRW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: PSUBSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PAVGW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PAVGB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: MASKMOVQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 4 +- name: PSRAW + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PACKSSWB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [2, '5']] + throughput: 2.25 + uops: 3 +- name: PUNPCKLBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: REPE SCASQ + operands: [] + latency: ~ + port_pressure: [[11, '0156'], [5, '06'], [1, '15'], [1, '23']] + throughput: 5.25 + uops: 12 +- name: CMPSQ + operands: [] + latency: 4 + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: LODSQ + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '23']] + throughput: 0.5 + uops: 2 +- name: CDQE + operands: [] + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REPE LODSQ + operands: [] + latency: ~ + port_pressure: [[9, '06'], [1, '1']] + throughput: 4.5 + uops: 10 +- name: REPNE LODSQ + operands: [] + latency: ~ + port_pressure: [[9, '06'], [1, '1']] + throughput: 4.5 + uops: 10 +- name: SYSCALL + operands: [] + latency: ~ + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: ~ +- name: REPNE CMPSQ + operands: [] + latency: ~ + port_pressure: [[10, '06'], [1, '1'], [1, '5']] + throughput: 5.0 + uops: 12 +- name: MOVSQ + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [2, '23'], [1, '4']] + throughput: 1.0 + uops: 5 +- name: PUSHFQ + operands: [] + latency: 9 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 4 +- name: REPE MOVSQ + operands: [] + latency: ~ + port_pressure: [[17, '015'], [6, '0156'], [6, '06'], [1, '15'], [32, '23'], [16, '4']] + throughput: 16.0 + uops: 82 +- name: REPNE MOVSQ + operands: [] + latency: ~ + port_pressure: [[17, '015'], [6, '0156'], [6, '06'], [1, '15'], [32, '23'], [16, '4']] + throughput: 16.0 + uops: 82 +- name: MOVSXD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REPE STOSQ + operands: [] + latency: ~ + port_pressure: [[1, '01'], [16, '015'], [7, '0156'], [5, '06'], [16, '23'], [16, '4']] + throughput: 16.0 + uops: 65 +- name: REPNE STOSQ + operands: [] + latency: ~ + port_pressure: [[1, '01'], [16, '015'], [7, '0156'], [5, '06'], [16, '23'], [16, '4']] + throughput: 16.0 + uops: 65 +- name: SCASQ + operands: [] + latency: 1 + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: REPNE SCASQ + operands: [] + latency: ~ + port_pressure: [[9, '06'], [1, '1'], [1, '23'], [1, '5']] + throughput: 4.5 + uops: 12 +- name: POPFQ + operands: [] + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: 10 +- name: STOSQ + operands: [] + latency: 0 + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: CQO + operands: [] + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REPE CMPSQ + operands: [] + latency: ~ + port_pressure: [[10, '06'], [1, '1'], [1, '5']] + throughput: 5.0 + uops: 12 +- name: POPCNT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PMOVZXBQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMOVZXBD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMOVSXWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: ROUNDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: ROUNDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: PCMPGTQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PBLENDW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MPSADBW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '0'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: PHMINPOSUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: INSERTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMOVSXDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMOVSXBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMULLD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[2, '0']] + throughput: 2.0 + uops: 2 +- name: PCMPEQQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PACKUSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: EXTRACTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMAXSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: BLENDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PTEST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMOVZXBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMULDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMOVZXDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMINSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMOVSXBD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMOVSXWQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMOVSXBQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CRC32 + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: REX CRC32 + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: DPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '0'], [1, '1'], [1, '5']] + throughput: 1.0 + uops: 3 +- name: DPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 12 + port_pressure: [[2, '0'], [1, '1'], [1, '5']] + throughput: 2.0 + uops: 4 +- name: PCMPISTRI + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 11 + port_pressure: [[3, '0']] + throughput: 3.0 + uops: 3 +- name: REX64 PCMPISTRI + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 11 + port_pressure: [[3, '0']] + throughput: 3.0 + uops: 3 +- name: PEXTRD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMAXUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMAXUD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: BLENDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PEXTRB + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMINUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMINUD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PINSRQ + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: PINSRD + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: PINSRB + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: BLENDVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: BLENDVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: ROUNDSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: ROUNDSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: PEXTRQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMOVZXWQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PBLENDVB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: PMOVZXWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PHSUBD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PHSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PMULHRSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMULHRSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PHSUBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PHSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PSIGNW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGNW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGND + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGND + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGNB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGNB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PHADDSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PHADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PMADDUBSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMADDUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PHSUBSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PHSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PABSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PHADDD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PHADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PALIGNR + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PALIGNR + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSHUFB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSHUFB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PABSD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PHADDW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PHADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: ADDSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ADDSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: HSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: HSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: HADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: MOVSHDUP + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: HADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: MOVSLDUP + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MOVDDUP + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: XSETBV + operands: [] + latency: ~ + port_pressure: [[4, '0156'], [1, '06']] + throughput: 1.5 + uops: ~ +- name: XGETBV + operands: [] + latency: ~ + port_pressure: [[2, '0156']] + throughput: 0.5 + uops: ~ +- name: TZCNT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: BLSMSK + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: ANDN + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: BEXTR + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '06'], [1, '15']] + throughput: 0.5 + uops: 2 +- name: BLSI + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: BLSR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: RDTSCP + operands: [] + latency: ~ + port_pressure: [[20, '0156'], [2, '5']] + throughput: 7.0 + uops: 21 +- name: AESDEC + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: AESKEYGENASSIST + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[2, '0'], [2, '015'], [7, '5']] + throughput: 7.666666666666667 + uops: 10 +- name: AESENCLAST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: AESIMC + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: AESDECLAST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: AESENC + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CLAC + operands: [] + latency: ~ + port_pressure: [[2, '0156']] + throughput: 0.5 + uops: ~ +- name: ADOX + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: ADCX + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: MWAIT + operands: [] + latency: ~ + port_pressure: [[7, '0156'], [2, '06'], [1, '5']] + throughput: 2.75 + uops: ~ +- name: RDSEED + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[2, '015'], [2, '0156'], [7, '06'], [1, '1'], [1, '23'], [2, '5']] + throughput: 4.666666666666666 + uops: 15 +- name: LZCNT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PCLMULQDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: RDRAND + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[3, '0156'], [1, '06'], [1, '23']] + throughput: 1.25 + uops: 15 +- name: PAUSE + operands: [] + latency: ~ + port_pressure: [[4, '0156'], [1, '06']] + throughput: 1.5 + uops: 6 +- name: VMOVMSKPD + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VMOVMSKPD + operands: + - class: register + name: ymm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VMOVMSKPS + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VMOVMSKPS + operands: + - class: register + name: ymm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMULHUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMULUDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCPSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMULHRSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPERM2F128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VHADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 3 +- name: VHADDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 3 +- name: VPUNPCKLBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMOVSHDUP + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMOVSHDUP + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMOVZXWQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPEQW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPAVGW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPAVGB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMOVSXDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VMULSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VANDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VANDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMOVDDUP + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMOVDDUP + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VANDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VANDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMULSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMAXSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPTEST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPTEST + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPACKSSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPINSRB + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPMAXUB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VADDSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPXOR + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VSQRTSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [13, [0DV]]] + throughput: 13.0 + uops: 1 +- name: VPMOVSXBQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: VUNPCKHPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCOMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPBLENDVB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VZEROALL + operands: [] + latency: ~ + port_pressure: [[16, '5']] + throughput: 16.0 + uops: 20 +- name: VCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSRAD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMOVSXBD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSRAW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSHUFB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMOVSLDUP + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMOVSLDUP + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VDIVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[1, '0'], [8, [0DV]]] + throughput: 8.0 + uops: 1 +- name: VDIVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 23 + port_pressure: [[2, '0'], [1, '01'], [16, [0DV]]] + throughput: 16.0 + uops: 3 +- name: VDIVS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 11 + port_pressure: [[1, '0'], [5, [0DV]]] + throughput: 5.0 + uops: 1 +- name: VDIVS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 17 + port_pressure: [[2, '0'], [1, '01'], [10, [0DV]]] + throughput: 10.0 + uops: 3 +- name: VCMPSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSLLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMOVMSKB + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VCMPSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSLLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VBLENDVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VBLENDVPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPSLLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPAND + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPHADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VPANDN + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VSHUFPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSUBSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: VSQRTPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 21 + port_pressure: [[2, '0'], [1, '01'], [14, [0DV]]] + throughput: 14.0 + uops: 3 +- name: VCVTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTPS2DQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPHADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VSQRTPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [13, [0DV]]] + throughput: 13.0 + uops: 1 +- name: VSQRTPD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 35 + port_pressure: [[2, '0'], [1, '01'], [26, [0DV]]] + throughput: 26.0 + uops: 3 +- name: VSUBSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSHUFPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMULDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VDPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 3 +- name: VDPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 12 + port_pressure: [[2, '0'], [1, '1']] + throughput: 2.0 + uops: 4 +- name: VDPPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 12 + port_pressure: [[2, '0'], [1, '1']] + throughput: 2.0 + uops: 4 +- name: VMOVLHPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTPD2DQ + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VMULPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMOVZXBD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMOVZXBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMOVZXBQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VINSERTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPALIGNR + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VMAXPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMAXPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPACKUSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMAXPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMAXPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSIGNW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSIGNB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VUNPCKHPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKLWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSIGND + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMULHW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VXORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VXORPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VROUNDSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: VROUNDSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: VPMADDUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VXORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VXORPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTF128 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VHSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 3 +- name: VHSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 3 +- name: VHSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 3 +- name: VHSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 3 +- name: VHADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 3 +- name: VHADDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 3 +- name: VCVTTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTTPS2DQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VTESTPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VTESTPD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VDIVS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 11 + port_pressure: [[1, '0'], [3, [0DV]]] + throughput: 3.0 + uops: 1 +- name: VDIVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[1, '0'], [4, [0DV]]] + throughput: 4.0 + uops: 1 +- name: VTESTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VTESTPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VMINSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPABSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPHADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSUBUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VBLENDVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VBLENDVPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VMPSADBW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '0'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VPSUBUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPGTB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VZEROUPPER + operands: [] + latency: ~ + port_pressure: [[1, '015'], [3, '0156']] + throughput: 1.0833333333333333 + uops: 4 +- name: VANDNPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VANDNPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPABSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VBLENDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VBLENDPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VBLENDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VBLENDPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRSQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRTPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 7 + port_pressure: [[2, '0'], [1, '01']] + throughput: 2.5 + uops: 3 +- name: VPEXTRB + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPEXTRD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPHSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VPEXTRQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPEXTRW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPHSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPBLENDW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPOR + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPMULLD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[2, '0']] + throughput: 2.0 + uops: 2 +- name: VUCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPCMPISTRI + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 11 + port_pressure: [[3, '0']] + throughput: 3.0 + uops: 3 +- name: VPMULLW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VUCOMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTF128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMOVSXBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKUSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPINSRD + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPINSRQ + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPINSRW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPMAXUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSRLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSRLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMINPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMINPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTDQ2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTDQ2PS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 2 +- name: VCVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 2 +- name: VMINPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMINPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSUBB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSADBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VROUNDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: VROUNDPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: VROUNDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: VROUNDPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: VPSUBSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMOVZXDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCLMULQDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCPPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCPPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 7 + port_pressure: [[2, '0'], [1, '01']] + throughput: 2.5 + uops: 3 +- name: VCVTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VPMOVSXWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMOVHLPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMOVSXWQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VORPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VORPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMASKMOVDQU + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 10 +- name: VPMINUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VUNPCKLPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINUD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VUNPCKLPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTTPD2DQ + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPCMPGTD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMADDWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPHMINPOSUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPABSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMOVZXWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPHSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VCVTTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VCVTPD2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTPD2PS + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VADDSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPACKSSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VADDSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 2 +- name: VCVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 2 +- name: VPMULHUW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMULUDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLDQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMULHRSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMOVZXWQ + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPEQW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPAVGW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPAVGB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMOVSXDQ + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXSD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSRLVQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLVQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMAXSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSRLVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '0'], [1, '5']] + throughput: 2.0 + uops: 3 +- name: VPSRLVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[2, '0'], [1, '5']] + throughput: 2.0 + uops: 3 +- name: VPSRLDQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINSD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPACKSSDW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPXOR + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPMOVSXBQ + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBLENDVB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPSRAD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMOVSXBD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSRAW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSHUFB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSLLD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMOVMSKB + operands: + - class: register + name: ymm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPAND + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPHADDW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VPANDN + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPHADDD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VPMULDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMOVZXBD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMOVZXBW + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMOVZXBQ + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPALIGNR + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPACKUSWB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHQDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSIGNW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSIGNB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDUSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKLWD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDUSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSIGND + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPBROADCASTD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTB + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMULHW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTW + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMADDUBSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRAVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '0'], [1, '5']] + throughput: 2.0 + uops: 3 +- name: VPSRAVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[2, '0'], [1, '5']] + throughput: 2.0 + uops: 3 +- name: VPABSW + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPHADDSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VPSUBUSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VMPSADBW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '0'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VPSUBUSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPGTB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPABSB + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPHSUBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VPHSUBD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VPBLENDW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPOR + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPMULLD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 10 + port_pressure: [[2, '0']] + throughput: 2.0 + uops: 2 +- name: VPMULLW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPERM2I128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMOVSXBW + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKUSDW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXUW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSRLW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLQDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSRLD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTSD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTSS + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTQ + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSUBB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSADBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSUBSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VINSERTI128 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTI128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSUBSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMOVZXDQ + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMOVSXWD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMOVSXWQ + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBLENDD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPBLENDD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINUW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPERMPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINUD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPERMPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMADDWD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPABSD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMOVZXWD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHWD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPHSUBSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VPSLLVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '0'], [1, '5']] + throughput: 2.0 + uops: 3 +- name: VPSLLVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[2, '0'], [1, '5']] + throughput: 2.0 + uops: 3 +- name: VPACKSSWB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSLLVQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLVQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VFMADDSUB231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPH2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 2 +- name: VCVTPH2PS + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 2 +- name: VCVTPS2PH + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTPS2PH + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VAESDEC + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VAESDECLAST + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VAESIMC + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VAESENC + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VAESENCLAST + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VAESKEYGENASSIST + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[2, '0'], [2, '015'], [7, '5']] + throughput: 7.666666666666667 + uops: 10 +- name: SHRX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SARX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BZHI + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PDEP + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: RORX + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: MULX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0156'], [1, '06'], [1, '1']] + throughput: 1.25 + uops: 3 +- name: SHLX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: PEXT + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 diff --git a/osaca/data/csx.yml b/osaca/data/csx.yml index b3ac7e9..bef3fcf 100644 --- a/osaca/data/csx.yml +++ b/osaca/data/csx.yml @@ -27,12 +27,12 @@ port_model_scheme: | | ALU | | ALU | | LD | | LD | | ST | | ALU | | ALU & | | AGU | └-------┘ └-------┘ └-----┘ └-----┘ └-----┘ └-------┘ | Shift | └-----┘ ┌-------┐ ┌-------┐ ┌-----┐ ┌-----┐ ┌-------┐ └--------┘ - | 2ND | | Fast | | AGU | | AGU | | Fast | - | BRANCH| | LEA | └-----┘ └-----┘ | LEA | - └-------┘ └-------┘ └-------┘ - ┌-------┐ ┌-------┐ ┌-------┐ - |AVX DIV| |AVX FMA| | AVX | - └-------┘ └-------┘ | SHUF | + | 2ND | | Fast | | AGU | | AGU | | Fast | ┌--------┐ + | BRANCH| | LEA | └-----┘ └-----┘ | LEA | | BRANCH | + └-------┘ └-------┘ └-------┘ └--------┘ + ┌-------┐ ┌-------┐ ┌-------┐ + |AVX DIV| |AVX FMA| | AVX | + └-------┘ └-------┘ | SHUF | ┌-------┐ ┌-------┐ └-------┘ |AVX FMA| |AVX MUL| ┌-------┐ └-------┘ └-------┘ |AVX-512| @@ -50,9 +50,9 @@ port_model_scheme: | | Shift | | Slow | |AVX-512| └-------┘ | LEA | | ALU | ┌-------┐ └-------┘ └-------┘ - | VNNI | ┌-------┐ - └-------┘ | VNNI | - └-------┘ + | VNNI | ┌-------┐ + └-------┘ | VNNI | + └-------┘ instruction_forms: - name: addsd operands: diff --git a/osaca/data/hsw.yml b/osaca/data/hsw.yml new file mode 100644 index 0000000..d396ecf --- /dev/null +++ b/osaca/data/hsw.yml @@ -0,0 +1,13756 @@ +osaca_version: 0.3.1.dev1 +micro_architecture: Intel Haswell +arch_code: HSW +isa: x86 +ROB_size: 192 +retired_uOps_per_cycle: 4 +scheduler_size: 60 +hidden_loads: false +load_latency: {gpr: 4.0, xmm: 4.0, ymm: 4.0} +load_throughput: +- {base: gpr, index: gpr, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: gpr, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: gpr, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: gpr, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: ~, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: ~, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: ~, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: ~, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +ports: ['0', 0DV, '1', '2', '2D', '3', '3D', '4', '5', '6', '7'] +port_model_scheme: | + ┌------------------------------------------------------------------------┐ + | 60 entry unified scheduler | + └------------------------------------------------------------------------┘ + 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | + ▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼ + ┌-------┐ ┌-------┐ ┌-----┐ ┌-----┐ ┌-----┐ ┌-------┐ ┌--------┐ ┌------┐ + | ALU | | ALU | | LD | | LD | | ST | | ALU | | ALU & | |SIMPLE| + └-------┘ └-------┘ └-----┘ └-----┘ └-----┘ └-------┘ | Shift | | AGU | + ┌-------┐ ┌-------┐ ┌-----┐ ┌-----┐ ┌-------┐ └--------┘ └------┘ + | 2ND | | Fast | | AGU | | AGU | | Fast | ┌--------┐ + | BRANCH| | LEA | └-----┘ └-----┘ | LEA | | BRANCH | + └-------┘ └-------┘ └-------┘ └--------┘ + ┌-------┐ ┌-------┐ ┌-------┐ + |AVX DIV| |AVX FMA| | AVX | + └-------┘ └-------┘ | ALU | + ┌-------┐ ┌-------┐ └-------┘ + |AVX FMA| |AVX MUL| + └-------┘ └-------┘ + ┌-------┐ ┌-------┐ + |AVX MUL| |AVX ADD| + └-------┘ └-------┘ +instruction_forms: +- name: mov + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: mov + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: mov + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: mov + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: mov + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: mov + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movq + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movapd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movapd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movapd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movaps + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movaps + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movaps + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movdqa + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqa + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqa + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movdqu + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqu + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqu + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movq + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movsd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movsd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movsd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movss + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movss + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movss + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movupd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movupd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movupd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movups + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movups + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movups + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovq + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovss + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovups + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovq + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovss + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovups + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 + + +- name: SLDT + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0156'], [2, '06'], [1, '1']] + throughput: 1.25 + uops: 5 +- name: POPFW + operands: [] + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: 10 +- name: CALL + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: OUTSW + operands: [] + latency: ~ + port_pressure: [[8, '0'], [1, '01'], [4, '0156'], [22, '06'], [13, '1'], [1, '23'], [1, '237'], [1, '4'], [8, '5']] + throughput: 20.5 + uops: 59 +- name: OUTSB + operands: [] + latency: ~ + port_pressure: [[8, '0'], [1, '01'], [5, '0156'], [22, '06'], [12, '1'], [1, '15'], [1, '23'], [1, '237'], [1, '4'], [7, + '5']] + throughput: 20.75 + uops: 59 +- name: OUTSD + operands: [] + latency: ~ + port_pressure: [[7, '0'], [2, '01'], [4, '0156'], [23, '06'], [12, '1'], [1, '15'], [1, '23'], [1, '237'], [1, '4'], [7, + '5']] + throughput: 20.5 + uops: 59 +- name: JNLE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: WRMSR + operands: [] + latency: ~ + port_pressure: [[11, '0'], [57, '06'], [14, '1'], [13, '15'], [1, '4'], [12, '5']] + throughput: 39.5 + uops: 108 +- name: REPE SCASW + operands: [] + latency: ~ + port_pressure: [[11, '0156'], [5, '06'], [1, '15'], [1, '23']] + throughput: 5.25 + uops: 12 +- name: REPE SCASD + operands: [] + latency: ~ + port_pressure: [[11, '0156'], [5, '06'], [1, '15'], [1, '23']] + throughput: 5.25 + uops: 12 +- name: REPE SCASB + operands: [] + latency: ~ + port_pressure: [[11, '0156'], [5, '06'], [1, '15'], [1, '23']] + throughput: 5.25 + uops: 12 +- name: REX64 REPE SCASB + operands: [] + latency: ~ + port_pressure: [[11, '0156'], [5, '06'], [1, '15'], [1, '23']] + throughput: 5.25 + uops: 12 +- name: JNE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNS + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JL + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNP + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNZ + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.5 + uops: 1 +- name: JNB + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNO + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNL + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: CMC + operands: [] + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: CMP + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: CMP + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX CMP + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: LAHF + operands: [] + latency: 0 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: CBW + operands: [] + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: PUSHFW + operands: [] + latency: 9 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 4 +- name: NOT + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX NOT + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: NOP + operands: [] + latency: ~ + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: INC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX INC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: CMPSW + operands: [] + latency: 4 + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: CMPSB + operands: [] + latency: 4 + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: CMPSD + operands: [] + latency: 4 + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: SETB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SETL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SETO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BSR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SETP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: OUT + operands: + - class: register + name: gpr + - class: immediate + imd: int + latency: ~ + port_pressure: [[9, '0156'], [9, '06'], [2, '23'], [1, '237'], [1, '4'], [1, '5']] + throughput: 6.75 + uops: 56 +- name: OUT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[9, '0156'], [9, '06'], [2, '23'], [1, '237'], [1, '4'], [1, '5']] + throughput: 6.75 + uops: 55 +- name: LODSB + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: LODSW + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: LODSD + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '23']] + throughput: 0.5 + uops: 2 +- name: JNBE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: STD + operands: [] + latency: ~ + port_pressure: [[5, '0156'], [1, '06']] + throughput: 1.75 + uops: 3 +- name: STOSD + operands: [] + latency: 0 + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: XOR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX XOR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: SAR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SAR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: STC + operands: [] + latency: ~ + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: STI + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [4, '06'], [1, '1']] + throughput: 2.25 + uops: 6 +- name: STR + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[2, '06'], [1, '1']] + throughput: 1.0 + uops: 5 +- name: STOSB + operands: [] + latency: 0 + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: REPE LODSW + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: REPNE LODSW + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: RDMSR + operands: [] + latency: ~ + port_pressure: [[1, '0'], [7, '01'], [6, '015'], [37, '06'], [5, '1'], [6, '15'], [3, '5']] + throughput: 25.0 + uops: 65 +- name: REPE LODSB + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: REX64 REPE LODSB + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: REPNE LODSB + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: REX64 REPNE LODSB + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: REPE LODSD + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: REPNE LODSD + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: IDIV + operands: + - class: register + name: gpr + latency: 24 + port_pressure: [[2, '0'], [3, '0156'], [2, '1'], [2, '5']] + throughput: 2.75 + uops: 9 +- name: REX IDIV + operands: + - class: register + name: gpr + latency: 24 + port_pressure: [[2, '0'], [3, '0156'], [2, '1'], [2, '5']] + throughput: 2.75 + uops: 9 +- name: REPNE CMPSB + operands: [] + latency: ~ + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: REX64 REPNE CMPSB + operands: [] + latency: ~ + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: REPNE CMPSD + operands: [] + latency: ~ + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: SETS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SHR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SHR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SHL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SHL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BTS + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BTS + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BTR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BTR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: LOOP + operands: + - class: identifier + latency: 2 + port_pressure: [[2, '0156'], [4, '06'], [1, '15']] + throughput: 2.5 + uops: 8 +- name: BTC + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BTC + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: WBINVD + operands: [] + latency: ~ + port_pressure: [[138146, '0'], [272381, '06'], [182639, '1'], [235356, '4'], [56450, '5']] + throughput: 274336.5 + uops: 884972 +- name: JBE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: MUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: REX MUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PUSH + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '1'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: PUSHW + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: PUSH + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: PUSHW + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '1'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: SETNO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SETNL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: CLI + operands: [] + latency: ~ + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: CLD + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '06']] + throughput: 1.0 + uops: 3 +- name: SETNB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: CLC + operands: [] + latency: ~ + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: SETNZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SETNS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SETNP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: LLDT + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0156'], [7, '06'], [3, '1'], [1, '23'], [1, '237'], [1, '4']] + throughput: 3.75 + uops: 14 +- name: RET + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: 5 +- name: RET + operands: [] + latency: ~ + port_pressure: [[3, '06']] + throughput: 1.5 + uops: 3 +- name: SETNBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 2 +- name: REX SETNBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 2 +- name: REPE INSW + operands: [] + latency: ~ + port_pressure: [[4, '0'], [3, '015'], [3, '0156'], [18, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 14.75 + uops: 44 +- name: REPNE INSW + operands: [] + latency: ~ + port_pressure: [[4, '0'], [3, '015'], [3, '0156'], [18, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 14.75 + uops: 44 +- name: REPE INSB + operands: [] + latency: ~ + port_pressure: [[5, '0'], [2, '015'], [4, '0156'], [17, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 15.166666666666668 + uops: 44 +- name: REX64 REPE INSB + operands: [] + latency: ~ + port_pressure: [[5, '0'], [2, '015'], [4, '0156'], [17, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 15.166666666666668 + uops: 44 +- name: REPNE INSB + operands: [] + latency: ~ + port_pressure: [[5, '0'], [2, '015'], [4, '0156'], [17, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 15.166666666666668 + uops: 44 +- name: REX64 REPNE INSB + operands: [] + latency: ~ + port_pressure: [[5, '0'], [2, '015'], [4, '0156'], [17, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 15.166666666666668 + uops: 44 +- name: REPE INSD + operands: [] + latency: ~ + port_pressure: [[4, '0'], [3, '015'], [4, '0156'], [17, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 14.5 + uops: 44 +- name: REX64 REPE INSD + operands: [] + latency: ~ + port_pressure: [[4, '0'], [3, '015'], [4, '0156'], [17, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 14.5 + uops: 44 +- name: REPNE INSD + operands: [] + latency: ~ + port_pressure: [[4, '0'], [3, '015'], [4, '0156'], [17, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 14.5 + uops: 44 +- name: REX64 REPNE INSD + operands: [] + latency: ~ + port_pressure: [[4, '0'], [3, '015'], [4, '0156'], [17, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 14.5 + uops: 44 +- name: REPE STOSD + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 65 +- name: REPNE STOSD + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 65 +- name: VERR + operands: + - class: register + name: gpr + latency: 60 + port_pressure: [[2, '0'], [3, '06'], [5, '1'], [3, '5']] + throughput: 5.0 + uops: 13 +- name: REPE STOSB + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 76 +- name: REX64 REPE STOSB + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 76 +- name: REPNE STOSB + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 76 +- name: REX64 REPNE STOSB + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 76 +- name: REPE STOSW + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 65 +- name: REPNE STOSW + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 65 +- name: CWD + operands: [] + latency: 2 + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 2 +- name: TEST + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX TEST + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: TEST + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX TEST + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: JZ + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: SCASW + operands: [] + latency: 1 + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: JP + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JS + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JO + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: SCASD + operands: [] + latency: 1 + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: SCASB + operands: [] + latency: 1 + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: JB + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: RDPMC + operands: [] + latency: ~ + port_pressure: [[2, '01'], [10, '015'], [17, '06'], [1, '1'], [1, '15'], [3, '5']] + throughput: 12.833333333333334 + uops: 34 +- name: RETFW + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: RETF + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: RETFQ + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: RETFW + operands: [] + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: RETF + operands: [] + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: RETFQ + operands: [] + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: ENTERW + operands: + - class: immediate + imd: int + - class: immediate + imd: int + latency: ~ + port_pressure: [[3, '0156'], [1, '06'], [1, '1'], [1, '237'], [1, '4']] + throughput: 1.75 + uops: 12 +- name: ENTER + operands: + - class: immediate + imd: int + - class: immediate + imd: int + latency: ~ + port_pressure: [[3, '0156'], [1, '06'], [1, '1'], [1, '237'], [1, '4']] + throughput: 1.75 + uops: 12 +- name: REPNE SCASB + operands: [] + latency: ~ + port_pressure: [[19, '0156'], [9, '06'], [1, '15'], [3, '23']] + throughput: 9.25 + uops: 12 +- name: REX64 REPNE SCASB + operands: [] + latency: ~ + port_pressure: [[19, '0156'], [9, '06'], [1, '15'], [3, '23']] + throughput: 9.25 + uops: 12 +- name: REPNE SCASD + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 12 +- name: REPNE SCASW + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 12 +- name: LEAVEW + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '23']] + throughput: 0.5 + uops: 4 +- name: LEAVE + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: REPE OUTSW + operands: [] + latency: ~ + port_pressure: [[4, '0'], [2, '015'], [5, '0156'], [16, '06'], [10, '1'], [6, '5']] + throughput: 13.916666666666668 + uops: 43 +- name: REPNE OUTSW + operands: [] + latency: ~ + port_pressure: [[4, '0'], [2, '015'], [5, '0156'], [16, '06'], [10, '1'], [6, '5']] + throughput: 13.916666666666668 + uops: 43 +- name: REPE OUTSB + operands: [] + latency: ~ + port_pressure: [[4, '0'], [2, '015'], [5, '0156'], [16, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 13.916666666666668 + uops: 43 +- name: REX64 REPE OUTSB + operands: [] + latency: ~ + port_pressure: [[4, '0'], [2, '015'], [5, '0156'], [16, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 13.916666666666668 + uops: 43 +- name: REPNE OUTSB + operands: [] + latency: ~ + port_pressure: [[4, '0'], [2, '015'], [5, '0156'], [16, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 13.916666666666668 + uops: 43 +- name: REX64 REPNE OUTSB + operands: [] + latency: ~ + port_pressure: [[4, '0'], [2, '015'], [5, '0156'], [16, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 13.916666666666668 + uops: 43 +- name: REPE OUTSD + operands: [] + latency: ~ + port_pressure: [[4, '0'], [2, '015'], [4, '0156'], [17, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 14.166666666666668 + uops: 43 +- name: REX64 REPE OUTSD + operands: [] + latency: ~ + port_pressure: [[4, '0'], [2, '015'], [4, '0156'], [17, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 14.166666666666668 + uops: 43 +- name: REPNE OUTSD + operands: [] + latency: ~ + port_pressure: [[4, '0'], [2, '015'], [4, '0156'], [17, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 14.166666666666668 + uops: 43 +- name: REX64 REPNE OUTSD + operands: [] + latency: ~ + port_pressure: [[4, '0'], [2, '015'], [4, '0156'], [17, '06'], [10, '1'], [1, '15'], [5, '5']] + throughput: 14.166666666666668 + uops: 43 +- name: XLAT + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: SMSW + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0156'], [2, '06'], [1, '5']] + throughput: 1.25 + uops: 4 +- name: AND + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX AND + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: JLE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: CPUID + operands: [] + latency: ~ + port_pressure: [[5, '0156'], [2, '06'], [1, '5']] + throughput: 2.25 + uops: 53 +- name: RDTSC + operands: [] + latency: ~ + port_pressure: [[5, '0156'], [2, '06'], [1, '5']] + throughput: 2.25 + uops: 13 +- name: CDQ + operands: [] + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: INSB + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [2, '06'], [1, '23'], [1, '237'], [1, '4'], [1, '5']] + throughput: 1.5 + uops: 61 +- name: INSD + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [2, '06'], [1, '23'], [1, '237'], [1, '4'], [1, '5']] + throughput: 1.5 + uops: 61 +- name: IMUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: REX IMUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: IMUL + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: RCR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '0156'], [1, '06']] + throughput: 1.0 + uops: 3 +- name: REX RCR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '0156'], [1, '06']] + throughput: 1.0 + uops: 3 +- name: RCL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '0156'], [1, '06']] + throughput: 1.0 + uops: 3 +- name: REX RCL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '0156'], [1, '06']] + throughput: 1.0 + uops: 3 +- name: INSW + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [2, '06'], [1, '23'], [1, '237'], [1, '4'], [1, '5']] + throughput: 1.5 + uops: 61 +- name: STOSW + operands: [] + latency: 0 + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: IN + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: ~ + port_pressure: [[10, '0156'], [9, '06'], [3, '23'], [1, '5']] + throughput: 7.0 + uops: 62 +- name: IN + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[10, '0156'], [9, '06'], [3, '23'], [1, '5']] + throughput: 7.0 + uops: 61 +- name: BT + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: POP + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: 1 +- name: JRCXZ + operands: + - class: identifier + latency: ~ + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 2 +- name: SAHF + operands: [] + latency: 0 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: LMSW + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[3, '015'], [14, '06'], [1, '1'], [1, '23'], [2, '4'], [4, '5']] + throughput: 8.0 + uops: 25 +- name: REPE CMPSD + operands: [] + latency: ~ + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: OR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX OR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REPE CMPSB + operands: [] + latency: ~ + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: REX64 REPE CMPSB + operands: [] + latency: ~ + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: REPE CMPSW + operands: [] + latency: ~ + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: CLTS + operands: [] + latency: ~ + port_pressure: [[4, '06'], [2, '5']] + throughput: 2.0 + uops: 7 +- name: REPNE CMPSW + operands: [] + latency: ~ + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: ROL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: REX ROL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: VERW + operands: + - class: register + name: gpr + latency: 60 + port_pressure: [[2, '0'], [3, '06'], [4, '1'], [4, '5']] + throughput: 4.0 + uops: 13 +- name: JMP + operands: + - class: register + name: gpr + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JMP + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: ROR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: REX ROR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: SETLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SUB + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX SUB + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: NEG + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX NEG + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: SETNLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: ADD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX ADD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: CWDE + operands: [] + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: BSF + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SETZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: DEC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX DEC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: SETBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 2 +- name: REX SETBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 2 +- name: BSWAP + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '06'], [1, '15']] + throughput: 0.5 + uops: 2 +- name: UNPCKHPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: DIVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: ADDSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTPI2PS + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CMPSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ANDNPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CVTTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: ORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: DIVSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: RCPSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: SQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: SUBSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CMPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: XORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: SUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SHUFPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MINSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTSI2SS + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: SFENCE + operands: [] + latency: ~ + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: RSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: UNPCKLPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MULSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: SQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: CVTTPS2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: RSQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: MINPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTPS2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: MULPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: CVTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: ANDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MAXPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: COMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: RCPPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: MAXSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: UCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: UNPCKHPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PUNPCKHDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: CVTTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: DIVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: PCMPGTW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTPI2PD + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PACKUSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: ANDNPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSLLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: UNPCKLPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSADBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PADDUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PACKSSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMULLW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: DIVSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: PCMPEQW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPEQB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPEQD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PUNPCKLWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: ORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PXOR + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CMPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PSUBB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMAXSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSRLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PADDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CMPSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PMULHUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: MINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: ADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: POR + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CVTSD2SS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PSLLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: SQRTSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: PSLLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: CVTSI2SD + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PSLLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MULSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PANDN + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: SHUFPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: SUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SQRTPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: ANDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMULHW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMINSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PSHUFD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CVTSS2SD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: XORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: MINPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ADDSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PSRLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: SUBSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PADDSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: LFENCE + operands: [] + latency: ~ + port_pressure: [[2, '0156']] + throughput: 0.5 + uops: 2 +- name: CVTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: CVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: MULPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PSUBQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMULUDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMULUDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMADDWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PEXTRW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PAND + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CVTDQ2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PMAXUB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CVTPD2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: CVTPD2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: MFENCE + operands: [] + latency: ~ + port_pressure: [[2, '0156']] + throughput: 0.5 + uops: 3 +- name: PSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MAXPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PMINUB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PINSRW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: PSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PAVGW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PAVGB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSRAW + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: COMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PSRAD + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PACKSSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PUNPCKLBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: UCOMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTTPD2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: FCHS + operands: [] + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: ~ +- name: FUCOM + operands: [] + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: FCOMI + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '01'], [1, '1']] + throughput: 1.5 + uops: ~ +- name: FLDL2T + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FLDL2E + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FYL2X + operands: [] + latency: ~ + port_pressure: [[2, '0'], [2, '01'], [2, '0156'], [2, '06'], [3, '1']] + throughput: 4.5 + uops: ~ +- name: FCOMIP + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '01'], [1, '1']] + throughput: 1.5 + uops: ~ +- name: FADDP + operands: [] + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: FXTRACT + operands: [] + latency: ~ + port_pressure: [[1, '01'], [2, '1']] + throughput: 2.5 + uops: ~ +- name: FCOMPP + operands: [] + latency: ~ + port_pressure: [[1, '01'], [1, '1']] + throughput: 1.5 + uops: ~ +- name: FYL2XP1 + operands: [] + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: FRNDINT + operands: [] + latency: ~ + port_pressure: [[5, '0'], [2, '01'], [3, '0156'], [2, '06'], [5, '1'], [1, '5']] + throughput: 7.75 + uops: ~ +- name: FNCLEX + operands: [] + latency: ~ + port_pressure: [[4, '0156']] + throughput: 1.0 + uops: ~ +- name: FPTAN + operands: [] + latency: ~ + port_pressure: [[3, '0'], [2, '1']] + throughput: 3.0 + uops: ~ +- name: FCOS + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '0156'], [3, '06'], [5, '1'], [2, '5']] + throughput: 9.5 + uops: ~ +- name: FSCALE + operands: [] + latency: ~ + port_pressure: [[1, '0'], [3, '0156'], [1, '06'], [2, '1']] + throughput: 2.75 + uops: ~ +- name: FXAM + operands: [] + latency: ~ + port_pressure: [[2, '1']] + throughput: 2.0 + uops: ~ +- name: FFREE + operands: [] + latency: ~ + port_pressure: [[1, '01']] + throughput: 0.5 + uops: ~ +- name: FPREM1 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FNINIT + operands: [] + latency: ~ + port_pressure: [[3, '01'], [6, '0156'], [6, '5']] + throughput: 7.5 + uops: ~ +- name: FNOP + operands: [] + latency: ~ + port_pressure: [[1, '01']] + throughput: 0.5 + uops: ~ +- name: FLDPI + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FNSTSW + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '0156']] + throughput: 1.25 + uops: ~ +- name: FWAIT + operands: [] + latency: ~ + port_pressure: [[2, '0156']] + throughput: 0.5 + uops: ~ +- name: F2XM1 + operands: [] + latency: ~ + port_pressure: [[3, '0'], [3, '0156'], [3, '06'], [3, '1']] + throughput: 5.25 + uops: ~ +- name: FPREM + operands: [] + latency: ~ + port_pressure: [[1, '0'], [2, '01'], [1, '0156'], [1, '1']] + throughput: 2.25 + uops: ~ +- name: FINCSTP + operands: [] + latency: ~ + port_pressure: [[1, '01']] + throughput: 0.5 + uops: ~ +- name: FTST + operands: [] + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: FPATAN + operands: [] + latency: ~ + port_pressure: [[25, '0'], [2, '01'], [10, '0156'], [5, '06'], [10, '1'], [3, '5']] + throughput: 31.0 + uops: ~ +- name: FABS + operands: [] + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: ~ +- name: FSIN + operands: [] + latency: ~ + port_pressure: [[8, '0'], [3, '0156'], [4, '06'], [5, '1'], [2, '5']] + throughput: 10.75 + uops: ~ +- name: FLDLN2 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FXCH + operands: [] + latency: ~ + port_pressure: [[2, '0'], [2, '01'], [4, '0156'], [4, '06'], [1, '1'], [2, '5']] + throughput: 6.0 + uops: ~ +- name: FDECSTP + operands: [] + latency: ~ + port_pressure: [[2, '01']] + throughput: 1.0 + uops: ~ +- name: FLDLG2 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FLDZ + operands: [] + latency: ~ + port_pressure: [[1, '01']] + throughput: 0.5 + uops: ~ +- name: FUCOMPP + operands: [] + latency: ~ + port_pressure: [[1, '01'], [1, '1']] + throughput: 1.5 + uops: ~ +- name: FLD1 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '01']] + throughput: 1.5 + uops: ~ +- name: FSINCOS + operands: [] + latency: ~ + port_pressure: [[2, '0'], [1, '01'], [3, '1']] + throughput: 3.5 + uops: ~ +- name: FUCOMIP + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '01'], [1, '1']] + throughput: 1.5 + uops: ~ +- name: PUNPCKHDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PCMPGTW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PACKUSWB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [2, '5']] + throughput: 2.25 + uops: 3 +- name: PSUBD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSADBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PADDUSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDUSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PACKSSDW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [2, '5']] + throughput: 2.25 + uops: 3 +- name: PMULLW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PCMPEQW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPEQB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPEQD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLWD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PADDSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PXOR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PSUBB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBUSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMAXSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMULHUW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: POR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PSLLD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLW + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLQ + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBUSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PANDN + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PMULHW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMINSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSHUFW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSRLQ + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLW + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PADDSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: EMMS + operands: [] + latency: ~ + port_pressure: [[8, '01'], [21, '015'], [1, '0156'], [1, '15']] + throughput: 11.75 + uops: 31 +- name: PUNPCKHBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMADDWD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PEXTRW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PAND + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PMAXUB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHWD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMINUB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PINSRW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: PSUBSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PAVGW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PAVGB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSRAW + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PACKSSWB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [2, '5']] + throughput: 2.25 + uops: 3 +- name: PUNPCKLBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: REPE SCASQ + operands: [] + latency: ~ + port_pressure: [[11, '0156'], [5, '06'], [1, '15'], [1, '23']] + throughput: 5.25 + uops: 12 +- name: CMPSQ + operands: [] + latency: 4 + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: LODSQ + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '23']] + throughput: 0.5 + uops: 2 +- name: CDQE + operands: [] + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REPE LODSQ + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: REPNE LODSQ + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: SYSCALL + operands: [] + latency: ~ + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: ~ +- name: REPNE CMPSQ + operands: [] + latency: ~ + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: PUSHFQ + operands: [] + latency: 9 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 4 +- name: REPE STOSQ + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 65 +- name: REPNE STOSQ + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 65 +- name: SCASQ + operands: [] + latency: 1 + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: REPNE SCASQ + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 12 +- name: POPFQ + operands: [] + latency: ~ + port_pressure: [[3, '0156'], [2, '06'], [1, '1'], [1, '23']] + throughput: 1.75 + uops: 10 +- name: STOSQ + operands: [] + latency: 0 + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: CQO + operands: [] + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REPE CMPSQ + operands: [] + latency: ~ + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: POPCNT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ROUNDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: ROUNDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: PCMPGTQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PBLENDW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MPSADBW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '0'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: PHMINPOSUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: INSERTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMULLD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[2, '0']] + throughput: 2.0 + uops: 2 +- name: PCMPEQQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PACKUSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: EXTRACTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMAXSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: BLENDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PTEST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMULDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMINSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CRC32 + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: REX CRC32 + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: DPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 9 + port_pressure: [[1, '0'], [1, '1'], [1, '5']] + throughput: 1.0 + uops: 3 +- name: DPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[2, '0'], [1, '1'], [1, '5']] + throughput: 2.0 + uops: 4 +- name: PCMPISTRI + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 11 + port_pressure: [[3, '0']] + throughput: 3.0 + uops: 3 +- name: REX64 PCMPISTRI + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 11 + port_pressure: [[3, '0']] + throughput: 3.0 + uops: 3 +- name: PEXTRD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMAXUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMAXUD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: BLENDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PEXTRB + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMINUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMINUD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PINSRQ + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: PINSRD + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: PINSRB + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: BLENDVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: BLENDVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: ROUNDSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: ROUNDSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: PEXTRQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PBLENDVB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: PHSUBD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PHSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PMULHRSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMULHRSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PHSUBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PHSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PSIGNW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGNW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGND + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGND + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGNB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGNB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PHADDSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PHADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PMADDUBSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMADDUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PHSUBSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PHSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PABSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PHADDD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PHADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PALIGNR + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PALIGNR + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSHUFB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSHUFB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PABSD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PHADDW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PHADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: ADDSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ADDSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: HSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: HSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: HADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: HADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: XSETBV + operands: [] + latency: ~ + port_pressure: [[4, '0156'], [1, '06']] + throughput: 1.5 + uops: ~ +- name: XGETBV + operands: [] + latency: ~ + port_pressure: [[2, '0156']] + throughput: 0.5 + uops: ~ +- name: TZCNT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: BLSMSK + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: ANDN + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: BEXTR + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '06'], [1, '15']] + throughput: 0.5 + uops: 2 +- name: BLSI + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: BLSR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: RDTSCP + operands: [] + latency: ~ + port_pressure: [[20, '0156'], [2, '5']] + throughput: 7.0 + uops: 21 +- name: AESDEC + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: AESKEYGENASSIST + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[2, '0'], [2, '015'], [7, '5']] + throughput: 7.666666666666667 + uops: 10 +- name: AESENCLAST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: AESIMC + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: AESDECLAST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: AESENC + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MWAIT + operands: [] + latency: ~ + port_pressure: [[7, '0156'], [2, '06'], [1, '5']] + throughput: 2.75 + uops: ~ +- name: LZCNT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PCLMULQDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[2, '0'], [1, '5']] + throughput: 2.0 + uops: 3 +- name: RDRAND + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[4, '015'], [9, '06'], [1, '1'], [1, '23'], [1, '5']] + throughput: 5.833333333333333 + uops: 17 +- name: PAUSE + operands: [] + latency: ~ + port_pressure: [[4, '0156'], [1, '06']] + throughput: 1.5 + uops: 6 +- name: VPMULHUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMULUDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCPSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMULHRSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPERM2F128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VHADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 3 +- name: VHADDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 3 +- name: VPUNPCKLBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPEQW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPAVGW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPAVGB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VMULSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VANDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VANDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VANDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VANDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMULSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMAXSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPTEST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPTEST + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPACKSSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPINSRB + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPMAXUB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VADDSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPXOR + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VSQRTSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: VEXTRACTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: VUNPCKHPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCOMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPBLENDVB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VZEROALL + operands: [] + latency: ~ + port_pressure: [[16, '5']] + throughput: 16.0 + uops: 20 +- name: VCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSRAD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSHUFD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSRAW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSHUFB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VDIVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: VDIVPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 35 + port_pressure: [[2, '0'], [1, '01'], [28, [0DV]]] + throughput: 28.0 + uops: 3 +- name: VDIVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: VDIVPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 21 + port_pressure: [[2, '0'], [1, '01'], [14, [0DV]]] + throughput: 14.0 + uops: 3 +- name: VCMPSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSLLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VCMPSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSLLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VBLENDVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VBLENDVPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPSLLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPAND + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPHADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VPANDN + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VSHUFPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSUBSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: VSQRTPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 21 + port_pressure: [[2, '0'], [1, '01'], [14, [0DV]]] + throughput: 14.0 + uops: 3 +- name: VCVTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTPS2DQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPHADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VSQRTPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: VSQRTPD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 35 + port_pressure: [[2, '0'], [1, '01'], [28, [0DV]]] + throughput: 28.0 + uops: 3 +- name: VSUBSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSHUFPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMULDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VDPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 9 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 3 +- name: VDPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[2, '0'], [1, '1']] + throughput: 2.0 + uops: 4 +- name: VDPPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 14 + port_pressure: [[2, '0'], [1, '1']] + throughput: 2.0 + uops: 4 +- name: VPUNPCKHDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTPD2DQ + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VMULPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VINSERTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPALIGNR + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VMAXPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMAXPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPACKUSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMAXPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMAXPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSIGNW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSIGNB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VUNPCKHPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKLWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSIGND + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMULHW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VXORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VXORPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VROUNDSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: VROUNDSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: VPMADDUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VXORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VXORPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTF128 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VHSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 3 +- name: VHSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 3 +- name: VHSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 3 +- name: VHSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 3 +- name: VHADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 3 +- name: VHADDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 3 +- name: VCVTTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTTPS2DQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VTESTPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VTESTPD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VDIVSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: VDIVSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: VTESTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VTESTPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VMINSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPABSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPHADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSUBUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VBLENDVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VBLENDVPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VMPSADBW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '0'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VPSUBUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPGTB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VZEROUPPER + operands: [] + latency: ~ + port_pressure: [[1, '015'], [3, '0156']] + throughput: 1.0833333333333333 + uops: 4 +- name: VANDNPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VANDNPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPABSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VBLENDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VBLENDPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VBLENDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VBLENDPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRSQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRTPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 7 + port_pressure: [[2, '0'], [1, '01']] + throughput: 2.5 + uops: 3 +- name: VPEXTRB + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPEXTRD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPHSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VPEXTRQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPEXTRW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPHSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPBLENDW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPOR + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPMULLD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[2, '0']] + throughput: 2.0 + uops: 2 +- name: VUCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPCMPISTRI + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 11 + port_pressure: [[3, '0']] + throughput: 3.0 + uops: 3 +- name: VPMULLW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VUCOMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTF128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKUSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPINSRD + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPINSRQ + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPINSRW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPMAXUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSRLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSRLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMINPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMINPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTDQ2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTDQ2PS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 2 +- name: VCVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 2 +- name: VMINPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMINPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSUBB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSADBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VROUNDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: VROUNDPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: VROUNDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: VROUNDPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[2, '1']] + throughput: 2.0 + uops: 2 +- name: VPSUBSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCLMULQDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[2, '0'], [1, '5']] + throughput: 2.0 + uops: 3 +- name: VRCPPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCPPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 7 + port_pressure: [[2, '0'], [1, '01']] + throughput: 2.5 + uops: 3 +- name: VCVTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VORPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VORPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VUNPCKLPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINUD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VUNPCKLPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTTPD2DQ + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPCMPGTD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMADDWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPHMINPOSUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPABSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKHWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPHSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VCVTTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VCVTPD2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTPD2PS + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VADDSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPACKSSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VADDSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 2 +- name: VCVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 2 +- name: VPMULHUW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMULUDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLDQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMULHRSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPEQW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPAVGW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPAVGB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXSD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSRLVQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLVQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMAXSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSRLVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '0'], [1, '5']] + throughput: 2.0 + uops: 3 +- name: VPSRLVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[2, '0'], [1, '5']] + throughput: 2.0 + uops: 3 +- name: VPSRLDQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINSD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPACKSSDW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPXOR + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDVB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPSRAD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSHUFD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSRAW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSHUFB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSLLD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPAND + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPHADDW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VPANDN + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPHADDD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VPMULDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPALIGNR + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPACKUSWB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHQDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSIGNW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSIGNB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDUSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKLWD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDUSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSIGND + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPBROADCASTD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTB + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMULHW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTW + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMADDUBSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRAVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '0'], [1, '5']] + throughput: 2.0 + uops: 3 +- name: VPSRAVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[2, '0'], [1, '5']] + throughput: 2.0 + uops: 3 +- name: VPABSW + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPHADDSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VPSUBUSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VMPSADBW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '0'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VPSUBUSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPGTB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPABSB + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPHSUBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VPHSUBD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VPBLENDW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPOR + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPMULLD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 10 + port_pressure: [[2, '0']] + throughput: 2.0 + uops: 2 +- name: VPMULLW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPERM2I128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKUSDW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXUW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSRLW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLQDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSRLD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTSD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTSS + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTQ + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSUBB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSADBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSUBSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VINSERTI128 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTI128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSUBSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPBLENDD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPBLENDD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINUW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPERMPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINUD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPERMPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMADDWD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPABSD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKHWD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPHSUBSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '15'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: VPSLLVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '0'], [1, '5']] + throughput: 2.0 + uops: 3 +- name: VPSLLVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[2, '0'], [1, '5']] + throughput: 2.0 + uops: 3 +- name: VPACKSSWB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSLLVQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLVQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VFMADDSUB231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPH2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 2 +- name: VCVTPH2PS + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 2 +- name: VCVTPS2PH + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTPS2PH + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VAESDEC + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VAESDECLAST + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VAESIMC + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VAESENC + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VAESENCLAST + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VAESKEYGENASSIST + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[2, '0'], [2, '015'], [7, '5']] + throughput: 7.666666666666667 + uops: 10 +- name: SHRX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SARX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BZHI + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PDEP + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: RORX + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: MULX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0156'], [1, '06'], [1, '1']] + throughput: 1.25 + uops: 3 +- name: SHLX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: PEXT + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 diff --git a/osaca/data/ivb.yml b/osaca/data/ivb.yml new file mode 100644 index 0000000..0e030de --- /dev/null +++ b/osaca/data/ivb.yml @@ -0,0 +1,10482 @@ +osaca_version: 0.3.1.dev1 +micro_architecture: Intel Ivy Bridge +arch_code: IVB +isa: x86 +ROB_size: 168 +retired_uOps_per_cycle: 4 +scheduler_size: 54 +hidden_loads: false +load_latency: {gpr: 4.0, xmm: 4.0, ymm: 4.0} +load_throughput: +- {base: gpr, index: gpr, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: gpr, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: gpr, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: gpr, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: ~, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: ~, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: ~, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: ~, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +ports: ['0', '0DV', '1', '2', '2D', '3', '3D', '4', '5'] +port_model_scheme: | + ┌-----------------------------------------------------┐ + | 54 entry scheduler | + └-----------------------------------------------------┘ + 0 | 1 | 2 | 3 | 4 | 5 | + ▼ ▼ ▼ ▼ ▼ ▼ + ┌-------┐ ┌-------┐ ┌-----┐ ┌-----┐ ┌-----┐ ┌-------┐ + | ALU | | ALU | | LD | | LD | | ST | | ALU | + └-------┘ └-------┘ └-----┘ └-----┘ └-----┘ └-------┘ + ┌-------┐ ┌-------┐ ┌-----┐ ┌-----┐ ┌-------┐ + |AVX DIV| | Fast | | AGU | | AGU | | BRANCH| + └-------┘ | LEA | └-----┘ └-----┘ └-------┘ + ┌-------┐ └-------┘ ┌-------┐ + |AVX MUL| ┌-------┐┌-------┐ | Fast | + └-------┘ |AVX ADD||AVX FMA| | LEA | + ┌-------┐ └-------┘└-------┘ └-------┘ + | AVX |┌-------┐ ┌-------┐ ┌-------┐ + | Shift ||AVX FMA| |AVX MUL| | AVX | + └-------┘└-------┘ └-------┘ | SHUF | + └-------┘ +instruction_forms: +- name: mov + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: mov + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: mov + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: mov + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: mov + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: mov + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movq + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movapd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movapd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movapd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movaps + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movaps + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movaps + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movdqa + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqa + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqa + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movdqu + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqu + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqu + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movq + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movsd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movsd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movsd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movss + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movss + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movss + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movupd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movupd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movupd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movups + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movups + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movups + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovq + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovss + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovups + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovq + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovss + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovups + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 + +- name: SLDT + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '015'], [1, '1'], [2, '5']] + throughput: 2.3333333333333335 + uops: 5 +- name: POPFW + operands: [] + latency: ~ + port_pressure: [[3, '015'], [1, '1'], [1, '23'], [2, '5']] + throughput: 3.0 + uops: 10 +- name: CALL + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '4'], [1, '5']] + throughput: 1.0 + uops: 3 +- name: OUTSW + operands: [] + latency: ~ + port_pressure: [[12, '0'], [4, '01'], [3, '015'], [1, '05'], [11, '1'], [1, '15'], [2, '23'], [1, '4'], [23, '5']] + throughput: 25.0 + uops: 58 +- name: OUTSB + operands: [] + latency: ~ + port_pressure: [[12, '0'], [4, '01'], [4, '015'], [11, '1'], [2, '23'], [1, '4'], [24, '5']] + throughput: 25.333333333333332 + uops: 58 +- name: OUTSD + operands: [] + latency: ~ + port_pressure: [[12, '0'], [4, '01'], [4, '015'], [11, '1'], [2, '23'], [1, '4'], [24, '5']] + throughput: 25.333333333333332 + uops: 58 +- name: JNE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNLE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: WRMSR + operands: [] + latency: ~ + port_pressure: [[18, '0'], [7, '05'], [17, '1'], [13, '15'], [1, '4'], [52, '5']] + throughput: 62.0 + uops: 108 +- name: REPE SCASW + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: REPE SCASD + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: REPE SCASB + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: REX64 REPE SCASB + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: JNS + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JL + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNP + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNZ + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNB + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNO + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNL + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: CMC + operands: [] + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CMP + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CMP + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX CMP + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: LAHF + operands: [] + latency: 0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: CBW + operands: [] + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PUSHFW + operands: [] + latency: 9 + port_pressure: [[1, '05'], [1, '1'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 4 +- name: NOT + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX NOT + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: INC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX INC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CMPSW + operands: [] + latency: 4 + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: CMPSB + operands: [] + latency: 4 + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: CMPSD + operands: [] + latency: 4 + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: SETB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SETL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SETO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: BSR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SETP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: OUT + operands: + - class: register + name: gpr + - class: immediate + imd: int + latency: ~ + port_pressure: [[3, '015'], [1, '5']] + throughput: 2.0 + uops: 55 +- name: OUT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[3, '015']] + throughput: 1.0 + uops: 54 +- name: LODSB + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 3 +- name: LODSW + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 3 +- name: LODSD + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23']] + throughput: 0.5 + uops: 2 +- name: JNBE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: STD + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 3 +- name: STOSD + operands: [] + latency: 0 + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: XOR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX XOR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: SAR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SAR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: STC + operands: [] + latency: ~ + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: STI + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '1'], [3, '5']] + throughput: 3.6666666666666665 + uops: 6 +- name: STR + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '015'], [1, '1'], [2, '5']] + throughput: 2.3333333333333335 + uops: 5 +- name: STOSB + operands: [] + latency: 0 + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: REPE LODSW + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 10 +- name: REPNE LODSW + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 10 +- name: RDMSR + operands: [] + latency: ~ + port_pressure: [[2, '0'], [10, '01'], [14, '05'], [5, '1'], [6, '15'], [39, '5']] + throughput: 49.0 + uops: 76 +- name: REPE LODSB + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 10 +- name: REX64 REPE LODSB + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 10 +- name: REPNE LODSB + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 10 +- name: REX64 REPNE LODSB + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 10 +- name: REPE LODSD + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: REPNE LODSD + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: IDIV + operands: + - class: register + name: gpr + latency: 23 + port_pressure: [[2, '0'], [2, '015'], [2, '05'], [2, '1'], [2, '5'], [8, [0DV]]] + throughput: 8.0 + uops: 10 +- name: REX IDIV + operands: + - class: register + name: gpr + latency: 22 + port_pressure: [[2, '0'], [3, '015'], [2, '1'], [2, '5'], [8, [0DV]]] + throughput: 8.0 + uops: 9 +- name: REPNE CMPSB + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: REX64 REPNE CMPSB + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: REPNE CMPSD + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: SETS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SHR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SHR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SHL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SHL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: BTS + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: BTS + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: BTR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: BTR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: LOOP + operands: + - class: identifier + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 8 +- name: BTC + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: BTC + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: WBINVD + operands: [] + latency: ~ + port_pressure: [[184089, '0'], [135442, '4'], [294987, '5'], [1, [0DV]]] + throughput: 294987.0 + uops: 614518 +- name: JBE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: MUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: REX MUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PUSH + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '1'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: PUSHW + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: PUSH + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: PUSHW + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '1'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: SETNO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETNO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SETNL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETNL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: CLI + operands: [] + latency: ~ + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: CLD + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 3 +- name: SETNB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETNB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SETNZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETNZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SETNS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETNS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SETNP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETNP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: LLDT + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '01'], [1, '015'], [3, '1'], [2, '23'], [1, '4'], [6, '5']] + throughput: 6.333333333333333 + uops: 14 +- name: RET + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[5, '5']] + throughput: 5.0 + uops: 5 +- name: RET + operands: [] + latency: ~ + port_pressure: [[3, '5']] + throughput: 3.0 + uops: 3 +- name: SETNBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: REX SETNBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: REPE INSW + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [18, '5']] + throughput: 19.0 + uops: 43 +- name: REPNE INSW + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [18, '5']] + throughput: 19.0 + uops: 43 +- name: REPE INSB + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [1, '15'], [17, '5']] + throughput: 18.5 + uops: 43 +- name: REX64 REPE INSB + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [1, '15'], [17, '5']] + throughput: 18.5 + uops: 43 +- name: REPNE INSB + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [1, '15'], [17, '5']] + throughput: 18.5 + uops: 43 +- name: REX64 REPNE INSB + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [1, '15'], [17, '5']] + throughput: 18.5 + uops: 43 +- name: REPE INSD + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [1, '15'], [17, '5']] + throughput: 18.5 + uops: 43 +- name: REX64 REPE INSD + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [1, '15'], [17, '5']] + throughput: 18.5 + uops: 43 +- name: REPNE INSD + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [1, '15'], [17, '5']] + throughput: 18.5 + uops: 43 +- name: REX64 REPNE INSD + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [1, '15'], [17, '5']] + throughput: 18.5 + uops: 43 +- name: REPE STOSD + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 53 +- name: REPNE STOSD + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 53 +- name: VERR + operands: + - class: register + name: gpr + latency: 58 + port_pressure: [[4, '0'], [1, '1'], [8, '5']] + throughput: 8.0 + uops: 13 +- name: REPE STOSB + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 75 +- name: REX64 REPE STOSB + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 75 +- name: REPNE STOSB + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 75 +- name: REX64 REPNE STOSB + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 75 +- name: REPE STOSW + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 53 +- name: REPNE STOSW + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 53 +- name: CWD + operands: [] + latency: 2 + port_pressure: [[1, '015'], [1, '05']] + throughput: 0.8333333333333333 + uops: 2 +- name: TEST + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX TEST + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: TEST + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX TEST + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: JZ + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: SCASW + operands: [] + latency: 1 + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 3 +- name: JP + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JS + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JO + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: SCASD + operands: [] + latency: 1 + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 3 +- name: SCASB + operands: [] + latency: 1 + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 3 +- name: JB + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: RDPMC + operands: [] + latency: ~ + port_pressure: [[14, '01'], [9, '05'], [2, '1'], [1, '15'], [9, '5']] + throughput: 14.0 + uops: 35 +- name: ENTERW + operands: + - class: immediate + imd: int + - class: immediate + imd: int + latency: ~ + port_pressure: [[2, '01'], [4, '015'], [1, '05'], [2, '23'], [1, '4'], [2, '5']] + throughput: 3.833333333333333 + uops: 12 +- name: ENTER + operands: + - class: immediate + imd: int + - class: immediate + imd: int + latency: ~ + port_pressure: [[2, '01'], [4, '015'], [1, '05'], [2, '23'], [1, '4'], [2, '5']] + throughput: 3.833333333333333 + uops: 12 +- name: REPNE SCASB + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: REX64 REPNE SCASB + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: REPNE SCASD + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: REPNE SCASW + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: LEAVEW + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 4 +- name: LEAVE + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 3 +- name: REPE OUTSW + operands: [] + latency: ~ + port_pressure: [[7, '0'], [5, '01'], [2, '015'], [1, '05'], [10, '1'], [1, '15'], [16, '5']] + throughput: 17.666666666666668 + uops: 42 +- name: REPNE OUTSW + operands: [] + latency: ~ + port_pressure: [[7, '0'], [5, '01'], [2, '015'], [1, '05'], [10, '1'], [1, '15'], [16, '5']] + throughput: 17.666666666666668 + uops: 42 +- name: REPE OUTSB + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [11, '1'], [17, '5']] + throughput: 18.0 + uops: 42 +- name: REX64 REPE OUTSB + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [11, '1'], [17, '5']] + throughput: 18.0 + uops: 42 +- name: REPNE OUTSB + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [11, '1'], [17, '5']] + throughput: 18.0 + uops: 42 +- name: REX64 REPNE OUTSB + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [11, '1'], [17, '5']] + throughput: 18.0 + uops: 42 +- name: REPE OUTSD + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [11, '1'], [17, '5']] + throughput: 18.0 + uops: 42 +- name: REX64 REPE OUTSD + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [11, '1'], [17, '5']] + throughput: 18.0 + uops: 42 +- name: REPNE OUTSD + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [11, '1'], [17, '5']] + throughput: 18.0 + uops: 42 +- name: REX64 REPNE OUTSD + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [11, '1'], [17, '5']] + throughput: 18.0 + uops: 42 +- name: XLAT + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 3 +- name: SMSW + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '01'], [1, '015'], [2, '1'], [3, '5']] + throughput: 3.3333333333333335 + uops: 7 +- name: AND + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX AND + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: JLE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: CPUID + operands: [] + latency: ~ + port_pressure: [[13, '0'], [42, '5']] + throughput: 42.0 + uops: 55 +- name: RDTSC + operands: [] + latency: ~ + port_pressure: [[6, '01'], [4, '015'], [1, '05'], [3, '1'], [1, '15'], [6, '5']] + throughput: 8.333333333333332 + uops: 21 +- name: CDQ + operands: [] + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: INSB + operands: [] + latency: ~ + port_pressure: [[11, '0'], [2, '01'], [5, '015'], [12, '1'], [3, '23'], [1, '4'], [25, '5']] + throughput: 26.666666666666668 + uops: 60 +- name: INSD + operands: [] + latency: ~ + port_pressure: [[11, '0'], [2, '01'], [5, '015'], [12, '1'], [3, '23'], [1, '4'], [25, '5']] + throughput: 26.666666666666668 + uops: 60 +- name: IMUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: REX IMUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: IMUL + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: RCR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '015'], [2, '05']] + throughput: 1.3333333333333333 + uops: 3 +- name: REX RCR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '015'], [2, '05']] + throughput: 1.3333333333333333 + uops: 3 +- name: RCL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '015'], [2, '05']] + throughput: 1.3333333333333333 + uops: 3 +- name: REX RCL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '015'], [2, '05']] + throughput: 1.3333333333333333 + uops: 3 +- name: INSW + operands: [] + latency: ~ + port_pressure: [[11, '0'], [2, '01'], [5, '015'], [12, '1'], [3, '23'], [1, '4'], [25, '5']] + throughput: 26.666666666666668 + uops: 60 +- name: DIV + operands: + - class: register + name: gpr + latency: 23 + port_pressure: [[2, '0'], [1, '01'], [1, '015'], [2, '05'], [2, '1'], [3, '5'], [9, [0DV]]] + throughput: 9.0 + uops: 11 +- name: STOSW + operands: [] + latency: 0 + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: IN + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: ~ + port_pressure: [[14, '0'], [5, '015'], [13, '1'], [1, '23'], [28, '5']] + throughput: 29.666666666666668 + uops: 61 +- name: IN + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[14, '0'], [6, '015'], [12, '1'], [1, '23'], [27, '5']] + throughput: 29.0 + uops: 60 +- name: BT + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: BT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: POP + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: 1 +- name: JRCXZ + operands: + - class: identifier + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 2 +- name: SAHF + operands: [] + latency: 0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: LMSW + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[3, '0'], [4, '01'], [1, '015'], [1, '1'], [1, '23'], [1, '4'], [10, '5']] + throughput: 10.333333333333334 + uops: 21 +- name: REPE CMPSD + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: OR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX OR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REPE CMPSB + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: REX64 REPE CMPSB + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: REPE CMPSW + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: CLTS + operands: [] + latency: ~ + port_pressure: [[1, '05'], [5, '5']] + throughput: 5.5 + uops: 7 +- name: REPNE CMPSW + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: ROL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: REX ROL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: VERW + operands: + - class: register + name: gpr + latency: 60 + port_pressure: [[4, '0'], [1, '1'], [8, '5']] + throughput: 8.0 + uops: 13 +- name: JMP + operands: + - class: register + name: gpr + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JMP + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: ROR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: REX ROR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: SETLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SUB + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX SUB + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: NEG + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX NEG + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: SETNLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETNLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: ADD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX ADD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CWDE + operands: [] + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: BSF + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SETZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: DEC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX DEC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: SETBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: REX SETBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: BSWAP + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '05'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: UNPCKHPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: DIVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: ADDSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTPI2PS + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CMPSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ANDNPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CVTTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: ORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: DIVSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: RCPSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: SQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: SUBSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CMPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: XORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: SUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SHUFPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MINSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTSI2SS + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: SFENCE + operands: [] + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: RSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: UNPCKLPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MULSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: SQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: CVTTPS2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 2 +- name: RSQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: MINPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTPS2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 2 +- name: MULPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: CVTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: ANDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MAXPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: COMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: RCPPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: MAXSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: UCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: UNPCKHPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PUNPCKHDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: CVTTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: DIVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: PCMPGTW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTPI2PD + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PACKUSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: ANDNPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSLLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: UNPCKLPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSADBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PADDUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PACKSSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMULLW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: DIVSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: PCMPEQW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPEQB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPEQD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: ORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PXOR + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CMPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PSUBB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMAXSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSRLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CMPSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PMULHUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: MINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: ADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: POR + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CVTSD2SS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PSLLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: SQRTSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: PSLLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: CVTSI2SD + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PSLLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: MULSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PANDN + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: SHUFPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: SUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SQRTPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: ANDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMULHW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMINSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PSHUFD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTSS2SD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 2 +- name: XORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: MINPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ADDSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PSRLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: SUBSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PADDSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: CVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: MULPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMULUDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMULUDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMADDWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PEXTRW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: PAND + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CVTDQ2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PMAXUB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTPD2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: CVTPD2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: MFENCE + operands: [] + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: PSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: MAXPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PMINUB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PAVGW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PAVGB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSRAW + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: COMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: PSRAD + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PACKSSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: UCOMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: CVTTPD2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: FCHS + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FUCOM + operands: [] + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: FCOMI + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: FLDL2T + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FLDL2E + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FCOMIP + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: FADDP + operands: [] + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: FCOMPP + operands: [] + latency: ~ + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: FXAM + operands: [] + latency: ~ + port_pressure: [[2, '1']] + throughput: 2.0 + uops: ~ +- name: FFREE + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FNINIT + operands: [] + latency: ~ + port_pressure: [[3, '015'], [1, '5']] + throughput: 2.0 + uops: ~ +- name: FNOP + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FLDPI + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FNSTSW + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '015']] + throughput: 1.3333333333333333 + uops: ~ +- name: FWAIT + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FINCSTP + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FTST + operands: [] + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: FABS + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FLDLN2 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FDECSTP + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FLDLG2 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FLDZ + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FUCOMPP + operands: [] + latency: ~ + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: FLD1 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: FUCOMIP + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: PUNPCKHDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PACKUSWB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSADBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PADDUSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDUSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PACKSSDW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMULLW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PCMPEQW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPEQB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPEQD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLWD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PXOR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PSUBB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBUSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMAXSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMULHUW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: POR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PSLLD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLW + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLQ + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBUSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PANDN + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PMULHW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMINSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSHUFW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSRLQ + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLW + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PADDSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: EMMS + operands: [] + latency: ~ + port_pressure: [[1, '0'], [18, '5']] + throughput: 18.0 + uops: 31 +- name: PUNPCKHBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMADDWD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PEXTRW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: PAND + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PMAXUB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHWD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMINUB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PAVGW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PAVGB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSRAW + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PACKSSWB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PUNPCKLBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: REPE SCASQ + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: CMPSQ + operands: [] + latency: 4 + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: LODSQ + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23']] + throughput: 0.5 + uops: 2 +- name: CDQE + operands: [] + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REPE LODSQ + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: REPNE LODSQ + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: REPNE CMPSQ + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: PUSHFQ + operands: [] + latency: 9 + port_pressure: [[1, '05'], [1, '1'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 4 +- name: REPE STOSQ + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 53 +- name: REPNE STOSQ + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 53 +- name: SCASQ + operands: [] + latency: 1 + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 3 +- name: REPNE SCASQ + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: POPFQ + operands: [] + latency: ~ + port_pressure: [[3, '015'], [1, '1'], [1, '23'], [2, '5']] + throughput: 3.0 + uops: 10 +- name: STOSQ + operands: [] + latency: 0 + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: CQO + operands: [] + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REPE CMPSQ + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: POPCNT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ROUNDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ROUNDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PBLENDW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: MPSADBW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '0'], [2, '15']] + throughput: 1.0 + uops: 3 +- name: PHMINPOSUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: INSERTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMULLD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PCMPEQQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PACKUSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: EXTRACTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMAXSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: BLENDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PTEST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMULDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMINSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CRC32 + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: REX CRC32 + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: DPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 9 + port_pressure: [[1, '0'], [1, '1'], [1, '5']] + throughput: 1.0 + uops: 3 +- name: DPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 12 + port_pressure: [[1, '0'], [2, '1'], [1, '5']] + throughput: 2.0 + uops: 4 +- name: PEXTRD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: PMAXUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMAXUD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: BLENDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PEXTRB + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: PMINUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMINUD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: BLENDVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: BLENDVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: ROUNDSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ROUNDSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PEXTRQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: PBLENDVB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '15'], [1, '23']] + throughput: 1.0 + uops: 2 +- name: PHSUBD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PHSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PMULHRSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMULHRSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PHSUBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PHSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PSIGNW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGNW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGND + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGND + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGNB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGNB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PHADDSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PHADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PMADDUBSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMADDUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PHSUBSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PHSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PABSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PHADDD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PHADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PALIGNR + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PALIGNR + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSHUFB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSHUFB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PHADDW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PHADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: ADDSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ADDSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: HSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: HSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: HADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: HADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: TZCNT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: RDTSCP + operands: [] + latency: ~ + port_pressure: [[5, '0'], [1, '01'], [7, '1'], [10, '5']] + throughput: 10.0 + uops: 23 +- name: AESKEYGENASSIST + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[2, '0'], [1, '015'], [1, '15'], [7, '5']] + throughput: 7.833333333333333 + uops: 11 +- name: AESIMC + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: LZCNT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: RDRAND + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[7, '015'], [1, '05'], [2, '1'], [1, '23'], [2, '5']] + throughput: 4.833333333333334 + uops: 13 +- name: PAUSE + operands: [] + latency: ~ + port_pressure: [[3, '015'], [1, '5']] + throughput: 2.0 + uops: 7 +- name: VPMULHUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMULUDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCPSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMULHRSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPERM2F128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VHADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VHADDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VPUNPCKLBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPERMILPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPEQW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPAVGW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPAVGB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VMULSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VANDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VANDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VANDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VANDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMULSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VMULPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VMULPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VMAXSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPTEST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPTEST + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPACKSSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXUB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VADDSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPXOR + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VSQRTSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: VEXTRACTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: VUNPCKHPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCOMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VZEROALL + operands: [] + latency: ~ + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 20 +- name: VCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VPSRAD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSHUFD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSRAW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSHUFB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VDIVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: VDIVPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 35 + port_pressure: [[2, '0'], [1, '05'], [28, [0DV]]] + throughput: 28.0 + uops: 3 +- name: VDIVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: VDIVPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 21 + port_pressure: [[2, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 3 +- name: VCMPSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSLLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VCMPSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSLLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPAND + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPHADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: VPANDN + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VSHUFPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSUBSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: VSQRTPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 21 + port_pressure: [[2, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 3 +- name: VCVTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTPS2DQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPHADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: VSQRTPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: VSQRTPD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 35 + port_pressure: [[2, '0'], [1, '05'], [28, [0DV]]] + throughput: 28.0 + uops: 3 +- name: VSUBSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSHUFPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMULDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VDPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 9 + port_pressure: [[1, '0'], [1, '1'], [1, '5']] + throughput: 1.0 + uops: 3 +- name: VDPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 12 + port_pressure: [[1, '0'], [2, '1'], [1, '5']] + throughput: 2.0 + uops: 4 +- name: VDPPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 12 + port_pressure: [[1, '0'], [2, '1'], [1, '5']] + throughput: 2.0 + uops: 4 +- name: VPUNPCKHDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VCVTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTPD2DQ + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VMULPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VMULPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VINSERTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPALIGNR + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VMAXPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMAXPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPACKUSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VMAXPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMAXPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSIGNW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSIGNB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VUNPCKHPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKLWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSIGND + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMULHW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VXORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VXORPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VROUNDSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VROUNDSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPMADDUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VXORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VXORPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTF128 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VHSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VHSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VHSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VHSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VHADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VHADDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VCVTTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTTPS2DQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VTESTPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VTESTPD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VDIVSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [7, [0DV]]] + throughput: 7.0 + uops: 1 +- name: VDIVSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: VTESTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VTESTPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VMINSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPABSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPHADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: VMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSUBUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VMPSADBW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '0'], [2, '15']] + throughput: 1.0 + uops: 3 +- name: VPSUBUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPGTB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VANDNPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VANDNPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPABSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VBLENDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VBLENDPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VBLENDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VBLENDPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VRSQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRTPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 7 + port_pressure: [[2, '0'], [1, '05']] + throughput: 2.5 + uops: 3 +- name: VPEXTRB + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: VPEXTRD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: VPHSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: VPEXTRQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: VPEXTRW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: VPHSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: VADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPBLENDW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPOR + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPMULLD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VUCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VPCMPISTRI + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 11 + port_pressure: [[3, '0']] + throughput: 3.0 + uops: 3 +- name: VPMULLW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VUCOMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VEXTRACTF128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKUSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXUD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSRLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSRLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMINPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMINPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTDQ2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTDQ2PS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VCVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VMINPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMINPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSUBB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSADBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VROUNDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VROUNDPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VROUNDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VROUNDPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSUBSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCLMULQDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[2, '0'], [4, '015'], [3, '05'], [4, '1'], [2, '15'], [3, '5']] + throughput: 6.833333333333333 + uops: 18 +- name: VRCPPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCPPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 7 + port_pressure: [[2, '0'], [1, '05']] + throughput: 2.5 + uops: 3 +- name: VCVTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VORPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VORPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VUNPCKLPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINUD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VUNPCKLPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VCVTTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTTPD2DQ + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPCMPGTD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMADDWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPHMINPOSUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPABSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKHWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPHSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: VCVTTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VCVTPD2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTPD2PS + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VADDSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPACKSSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VADDSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTPH2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTPH2PS + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTPS2PH + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[1, '0'], [1, '1'], [1, '5']] + throughput: 1.0 + uops: 3 +- name: VCVTPS2PH + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 10 + port_pressure: [[1, '0'], [1, '1'], [1, '5']] + throughput: 1.0 + uops: 3 +- name: VAESIMC + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VAESKEYGENASSIST + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[2, '0'], [1, '015'], [1, '1'], [7, '5']] + throughput: 7.333333333333333 + uops: 11 + diff --git a/osaca/data/skx.yml b/osaca/data/skx.yml new file mode 100644 index 0000000..2ac698e --- /dev/null +++ b/osaca/data/skx.yml @@ -0,0 +1,36883 @@ +osaca_version: 0.3.1.dev1 +micro_architecture: Intel Skylake SP +arch_code: SKX +isa: x86 +ROB_size: 224 +retired_uOps_per_cycle: 4 +scheduler_size: 97 +hidden_loads: false +load_latency: {gpr: 4.0, xmm: 4.0, ymm: 4.0, zmm: 4.0} +load_throughput: +- {base: gpr, index: ~, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: ~, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: ~, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: ~, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: gpr, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: gpr, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: gpr, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +- {base: gpr, index: gpr, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, ['2D', '3D']]]} +ports: ['0', 0DV, '1', '2', 2D, '3', 3D, '4', '5', '6', '7'] +port_model_scheme: | + ┌------------------------------------------------------------------------┐ + | 97 entry unified scheduler | + └------------------------------------------------------------------------┘ + 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | + ▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼ + ┌-------┐ ┌-------┐ ┌-----┐ ┌-----┐ ┌-----┐ ┌-------┐ ┌--------┐ ┌-----┐ + | ALU | | ALU | | LD | | LD | | ST | | ALU | | ALU & | | AGU | + └-------┘ └-------┘ └-----┘ └-----┘ └-----┘ └-------┘ | Shift | └-----┘ + ┌-------┐ ┌-------┐ ┌-----┐ ┌-----┐ ┌-------┐ └--------┘ + | 2ND | | Fast | | AGU | | AGU | | Fast | ┌--------┐ + | BRANCH| | LEA | └-----┘ └-----┘ | LEA | | BRANCH | + └-------┘ └-------┘ └-------┘ └--------┘ + ┌-------┐ ┌-------┐ ┌-------┐ + |AVX DIV| |AVX FMA| | AVX | + └-------┘ └-------┘ | SHUF | + ┌-------┐ ┌-------┐ └-------┘ + |AVX FMA| |AVX MUL| ┌-------┐ + └-------┘ └-------┘ |AVX-512| + ┌-------┐ ┌-------┐ | FMA | + |AVX MUL| |AVX ADD| └-------┘ + └-------┘ └-------┘ ┌-------┐ + ┌-------┐ ┌-------┐ |AVX-512| + |AVX ADD| |AVX ALU| | ADD | + └-------┘ └-------┘ └-------┘ + ┌-------┐ ┌-------┐ ┌-------┐ + |AVX ALU| | AVX | |AVX-512| + └-------┘ | Shift | | MUL | + ┌-------┐ └-------┘ └-------┘ + | AVX | ┌-------┐ ┌-------┐ + | Shift | | Slow | |AVX-512| + └-------┘ | LEA | | ALU | + └-------┘ └-------┘ +instruction_forms: +- name: mov + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: mov + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: mov + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: mov + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: mov + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: mov + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movq + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movapd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movapd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movapd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movaps + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movaps + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movaps + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movdqa + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqa + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqa + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movdqu + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqu + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqu + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movq + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movsd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movsd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movsd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movss + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movss + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movss + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movupd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movupd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movupd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movups + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movups + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movups + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovq + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovss + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovups + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovq + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovss + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovups + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: zmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: zmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: zmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: register + name: zmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: zmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: zmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: zmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: zmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: zmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: register + name: zmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: zmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: zmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: SLDT + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0156'], [2, '06'], [1, '1']] + throughput: 1.25 + uops: 6 +- name: POPFW + operands: [] + latency: ~ + port_pressure: [[3, '0156'], [2, '06'], [1, '1'], [1, '23']] + throughput: 1.75 + uops: 7 +- name: CALL + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: OUTSW + operands: [] + latency: ~ + port_pressure: [[8, '0'], [1, '01'], [4, '0156'], [1, '05'], [25, '06'], [15, '1'], [3, '15'], [1, '23'], [1, '237'], [ + 1, '4'], [8, '5']] + throughput: 22.5 + uops: 69 +- name: OUTSB + operands: [] + latency: ~ + port_pressure: [[8, '0'], [1, '01'], [5, '0156'], [1, '05'], [24, '06'], [15, '1'], [3, '15'], [1, '23'], [1, '237'], [ + 1, '4'], [8, '5']] + throughput: 22.25 + uops: 68 +- name: OUTSD + operands: [] + latency: ~ + port_pressure: [[8, '0'], [1, '01'], [4, '0156'], [1, '05'], [25, '06'], [15, '1'], [3, '15'], [1, '23'], [1, '237'], [ + 1, '4'], [8, '5']] + throughput: 22.5 + uops: 68 +- name: JNE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNLE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: WRMSR + operands: [] + latency: ~ + port_pressure: [[13, '0'], [7, '05'], [64, '06'], [12, '1'], [18, '15'], [1, '4'], [10, '5']] + throughput: 48.5 + uops: 125 +- name: REPE SCASW + operands: [] + latency: ~ + port_pressure: [[11, '0156'], [5, '06'], [1, '15'], [1, '23']] + throughput: 5.25 + uops: 18 +- name: REPE SCASD + operands: [] + latency: ~ + port_pressure: [[11, '0156'], [5, '06'], [1, '15'], [1, '23']] + throughput: 5.25 + uops: 18 +- name: REPE SCASB + operands: [] + latency: ~ + port_pressure: [[11, '0156'], [5, '06'], [1, '15'], [1, '23']] + throughput: 5.25 + uops: 18 +- name: REX64 REPE SCASB + operands: [] + latency: ~ + port_pressure: [[11, '0156'], [5, '06'], [1, '15'], [1, '23']] + throughput: 5.25 + uops: 18 +- name: JNS + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JL + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNP + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNZ + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNB + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNO + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: LAR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 58 + port_pressure: [[2, '0156'], [1, '06'], [1, '1']] + throughput: 1.5 + uops: 24 +- name: JNL + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: CMC + operands: [] + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: CMP + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: CMP + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX CMP + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: LSL + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 56 + port_pressure: [[1, '0'], [2, '015'], [2, '0156'], [6, '06'], [3, '1'], [2, '23']] + throughput: 5.166666666666666 + uops: 16 +- name: LAHF + operands: [] + latency: 0 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: CBW + operands: [] + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: PUSHFW + operands: [] + latency: 7 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 4 +- name: NOT + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX NOT + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: NOP + operands: [] + latency: ~ + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 0 +- name: INC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX INC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: CMPSW + operands: [] + latency: 4 + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: CMPSB + operands: [] + latency: 4 + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: CMPSD + operands: [] + latency: 4 + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: SETB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SETL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SETO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BSR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SETP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: OUT + operands: + - class: register + name: gpr + - class: immediate + imd: int + latency: ~ + port_pressure: [[9, '0156'], [9, '06'], [2, '23'], [1, '237'], [1, '4'], [1, '5']] + throughput: 6.75 + uops: 66 +- name: OUT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[9, '0156'], [9, '06'], [2, '23'], [1, '237'], [1, '4'], [1, '5']] + throughput: 6.75 + uops: 64 +- name: SBB + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SBB + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 1 +- name: LODSB + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: LODSW + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: LODSD + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '23']] + throughput: 0.5 + uops: 2 +- name: JNBE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: STD + operands: [] + latency: ~ + port_pressure: [[5, '0156'], [1, '06']] + throughput: 1.75 + uops: 2 +- name: STOSD + operands: [] + latency: 0 + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: XOR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX XOR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: SAR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SAR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: STC + operands: [] + latency: ~ + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: STI + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [4, '06'], [1, '1']] + throughput: 2.25 + uops: 6 +- name: STR + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[2, '06'], [1, '1']] + throughput: 1.0 + uops: 6 +- name: STOSB + operands: [] + latency: 0 + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: REPE LODSW + operands: [] + latency: ~ + port_pressure: [[7, '015'], [9, '06'], [1, '1'], [3, '23']] + throughput: 6.833333333333334 + uops: 20 +- name: REPNE LODSW + operands: [] + latency: ~ + port_pressure: [[7, '015'], [9, '06'], [1, '1'], [3, '23']] + throughput: 6.833333333333334 + uops: 20 +- name: RDMSR + operands: [] + latency: ~ + port_pressure: [[1, '0'], [8, '01'], [17, '05'], [36, '06'], [6, '1'], [11, '15'], [5, '5']] + throughput: 31.5 + uops: 84 +- name: REPE LODSB + operands: [] + latency: ~ + port_pressure: [[8, '015'], [9, '06'], [1, '1'], [2, '23']] + throughput: 7.166666666666666 + uops: 20 +- name: REX64 REPE LODSB + operands: [] + latency: ~ + port_pressure: [[8, '015'], [9, '06'], [1, '1'], [2, '23']] + throughput: 7.166666666666666 + uops: 20 +- name: REPNE LODSB + operands: [] + latency: ~ + port_pressure: [[8, '015'], [9, '06'], [1, '1'], [2, '23']] + throughput: 7.166666666666666 + uops: 20 +- name: REX64 REPNE LODSB + operands: [] + latency: ~ + port_pressure: [[8, '015'], [9, '06'], [1, '1'], [2, '23']] + throughput: 7.166666666666666 + uops: 20 +- name: REPE LODSD + operands: [] + latency: ~ + port_pressure: [[7, '015'], [9, '06'], [1, '1'], [3, '23']] + throughput: 6.833333333333334 + uops: 20 +- name: REPNE LODSD + operands: [] + latency: ~ + port_pressure: [[7, '015'], [9, '06'], [1, '1'], [3, '23']] + throughput: 6.833333333333334 + uops: 20 +- name: REPNE CMPSB + operands: [] + latency: ~ + port_pressure: [[7, '015'], [11, '06'], [1, '1'], [3, '23'], [1, '5']] + throughput: 7.833333333333334 + uops: 23 +- name: REX64 REPNE CMPSB + operands: [] + latency: ~ + port_pressure: [[7, '015'], [11, '06'], [1, '1'], [3, '23'], [1, '5']] + throughput: 7.833333333333334 + uops: 23 +- name: REPNE CMPSD + operands: [] + latency: ~ + port_pressure: [[7, '015'], [11, '06'], [1, '1'], [3, '23'], [1, '5']] + throughput: 7.833333333333334 + uops: 23 +- name: SETS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SHR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SHR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SHL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SHL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BTS + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BTS + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BTR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BTR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: LOOP + operands: + - class: identifier + latency: 2 + port_pressure: [[2, '0156'], [4, '06'], [1, '15']] + throughput: 2.5 + uops: 8 +- name: BTC + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BTC + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: WBINVD + operands: [] + latency: ~ + port_pressure: [[372439, '0'], [837649, '06'], [472609, '1'], [345702, '23'], [174727, '237'], [517818, '4'], [499317, '5'], + [3, [0DV]]] + throughput: 791263.5 + uops: 3221652 +- name: JBE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: MUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: REX MUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PUSH + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '1'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: PUSHW + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: PUSH + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: PUSHW + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '1'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: SETNO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SETNL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: CLI + operands: [] + latency: ~ + port_pressure: [[2, '06'], [1, '1']] + throughput: 1.0 + uops: 3 +- name: CLD + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '06']] + throughput: 1.0 + uops: 2 +- name: SETNB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: CLC + operands: [] + latency: ~ + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 0 +- name: SETNZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SETNS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SETNP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: LLDT + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '015'], [7, '06'], [3, '1'], [1, '23'], [1, '237'], [1, '4']] + throughput: 3.8333333333333335 + uops: 14 +- name: RET + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: 11 +- name: RET + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '0156'], [2, '06'], [1, '1'], [1, '23'], [2, '237']] + throughput: 1.5833333333333333 + uops: 8 +- name: SETNBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: REX SETNBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: REPE INSW + operands: [] + latency: ~ + port_pressure: [[5, '0'], [1, '01'], [2, '015'], [6, '0156'], [2, '05'], [19, '06'], [12, '1'], [6, '5']] + throughput: 18.166666666666668 + uops: 53 +- name: REPNE INSW + operands: [] + latency: ~ + port_pressure: [[5, '0'], [1, '01'], [2, '015'], [6, '0156'], [2, '05'], [19, '06'], [12, '1'], [6, '5']] + throughput: 18.166666666666668 + uops: 53 +- name: REPE INSB + operands: [] + latency: ~ + port_pressure: [[5, '0'], [1, '01'], [2, '015'], [6, '0156'], [1, '05'], [19, '06'], [12, '1'], [7, '5']] + throughput: 17.666666666666668 + uops: 53 +- name: REX64 REPE INSB + operands: [] + latency: ~ + port_pressure: [[5, '0'], [1, '01'], [2, '015'], [6, '0156'], [1, '05'], [19, '06'], [12, '1'], [7, '5']] + throughput: 17.666666666666668 + uops: 53 +- name: REPNE INSB + operands: [] + latency: ~ + port_pressure: [[5, '0'], [1, '01'], [2, '015'], [6, '0156'], [1, '05'], [19, '06'], [12, '1'], [7, '5']] + throughput: 17.666666666666668 + uops: 53 +- name: REX64 REPNE INSB + operands: [] + latency: ~ + port_pressure: [[5, '0'], [1, '01'], [2, '015'], [6, '0156'], [1, '05'], [19, '06'], [12, '1'], [7, '5']] + throughput: 17.666666666666668 + uops: 53 +- name: REPE INSD + operands: [] + latency: ~ + port_pressure: [[5, '0'], [2, '01'], [1, '015'], [6, '0156'], [1, '05'], [19, '06'], [12, '1'], [7, '5']] + throughput: 17.833333333333332 + uops: 53 +- name: REX64 REPE INSD + operands: [] + latency: ~ + port_pressure: [[5, '0'], [2, '01'], [1, '015'], [6, '0156'], [1, '05'], [19, '06'], [12, '1'], [7, '5']] + throughput: 17.833333333333332 + uops: 53 +- name: REPNE INSD + operands: [] + latency: ~ + port_pressure: [[5, '0'], [2, '01'], [1, '015'], [6, '0156'], [1, '05'], [19, '06'], [12, '1'], [7, '5']] + throughput: 17.833333333333332 + uops: 53 +- name: REX64 REPNE INSD + operands: [] + latency: ~ + port_pressure: [[5, '0'], [2, '01'], [1, '015'], [6, '0156'], [1, '05'], [19, '06'], [12, '1'], [7, '5']] + throughput: 17.833333333333332 + uops: 53 +- name: REPE STOSD + operands: [] + latency: ~ + port_pressure: [[4, '01'], [12, '015'], [1, '05'], [25, '06'], [3, '1'], [2, '15'], [10, '23'], [8, '4'], [9, '5']] + throughput: 19.0 + uops: 74 +- name: REPNE STOSD + operands: [] + latency: ~ + port_pressure: [[4, '01'], [12, '015'], [1, '05'], [25, '06'], [3, '1'], [2, '15'], [10, '23'], [8, '4'], [9, '5']] + throughput: 19.0 + uops: 74 +- name: VERR + operands: + - class: register + name: gpr + latency: 62 + port_pressure: [[2, '0'], [8, '06'], [4, '1'], [4, '23'], [4, '5']] + throughput: 6.0 + uops: 22 +- name: REPE STOSB + operands: [] + latency: ~ + port_pressure: [[4, '01'], [11, '015'], [2, '05'], [25, '06'], [3, '1'], [2, '15'], [10, '23'], [8, '4'], [9, '5']] + throughput: 19.166666666666664 + uops: 74 +- name: REX64 REPE STOSB + operands: [] + latency: ~ + port_pressure: [[4, '01'], [11, '015'], [2, '05'], [25, '06'], [3, '1'], [2, '15'], [10, '23'], [8, '4'], [9, '5']] + throughput: 19.166666666666664 + uops: 74 +- name: REPNE STOSB + operands: [] + latency: ~ + port_pressure: [[4, '01'], [11, '015'], [2, '05'], [25, '06'], [3, '1'], [2, '15'], [10, '23'], [8, '4'], [9, '5']] + throughput: 19.166666666666664 + uops: 74 +- name: REX64 REPNE STOSB + operands: [] + latency: ~ + port_pressure: [[4, '01'], [11, '015'], [2, '05'], [25, '06'], [3, '1'], [2, '15'], [10, '23'], [8, '4'], [9, '5']] + throughput: 19.166666666666664 + uops: 74 +- name: REPE STOSW + operands: [] + latency: ~ + port_pressure: [[4, '01'], [11, '015'], [2, '05'], [25, '06'], [3, '1'], [2, '15'], [10, '23'], [8, '4'], [9, '5']] + throughput: 19.166666666666664 + uops: 74 +- name: REPNE STOSW + operands: [] + latency: ~ + port_pressure: [[4, '01'], [11, '015'], [2, '05'], [25, '06'], [3, '1'], [2, '15'], [10, '23'], [8, '4'], [9, '5']] + throughput: 19.166666666666664 + uops: 74 +- name: CWD + operands: [] + latency: 2 + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 2 +- name: TEST + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX TEST + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: TEST + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX TEST + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: JZ + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: SCASW + operands: [] + latency: 1 + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: JP + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JS + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JO + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: SCASD + operands: [] + latency: 1 + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: SCASB + operands: [] + latency: 1 + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: JB + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: RDPMC + operands: [] + latency: ~ + port_pressure: [[10, '015'], [2, '05'], [18, '06'], [1, '1'], [2, '5']] + throughput: 13.333333333333334 + uops: 33 +- name: RETFW + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: RETF + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: RETFQ + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: RETFW + operands: [] + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: RETF + operands: [] + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: RETFQ + operands: [] + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: ~ +- name: ENTERW + operands: + - class: immediate + imd: int + - class: immediate + imd: int + latency: ~ + port_pressure: [[3, '0156'], [1, '06'], [1, '1'], [1, '237'], [1, '4']] + throughput: 1.75 + uops: 12 +- name: ENTER + operands: + - class: immediate + imd: int + - class: immediate + imd: int + latency: ~ + port_pressure: [[3, '0156'], [1, '06'], [1, '1'], [1, '237'], [1, '4']] + throughput: 1.75 + uops: 12 +- name: REPNE SCASB + operands: [] + latency: ~ + port_pressure: [[19, '0156'], [9, '06'], [1, '15'], [3, '23']] + throughput: 9.25 + uops: 18 +- name: REX64 REPNE SCASB + operands: [] + latency: ~ + port_pressure: [[19, '0156'], [9, '06'], [1, '15'], [3, '23']] + throughput: 9.25 + uops: 18 +- name: REPNE SCASD + operands: [] + latency: ~ + port_pressure: [[5, '015'], [1, '0156'], [10, '06'], [1, '1'], [1, '5']] + throughput: 6.916666666666667 + uops: 18 +- name: REPNE SCASW + operands: [] + latency: ~ + port_pressure: [[5, '015'], [1, '0156'], [10, '06'], [1, '1'], [1, '5']] + throughput: 6.916666666666667 + uops: 18 +- name: LEAVEW + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '23']] + throughput: 0.5 + uops: 4 +- name: LEAVE + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: REPE OUTSW + operands: [] + latency: ~ + port_pressure: [[6, '0'], [1, '01'], [1, '015'], [5, '0156'], [19, '06'], [11, '1'], [2, '15'], [7, '5']] + throughput: 17.583333333333332 + uops: 52 +- name: REPNE OUTSW + operands: [] + latency: ~ + port_pressure: [[6, '0'], [1, '01'], [1, '015'], [5, '0156'], [19, '06'], [11, '1'], [2, '15'], [7, '5']] + throughput: 17.583333333333332 + uops: 52 +- name: REPE OUTSB + operands: [] + latency: ~ + port_pressure: [[5, '0'], [1, '01'], [1, '015'], [4, '0156'], [1, '05'], [20, '06'], [12, '1'], [1, '15'], [7, '5']] + throughput: 17.333333333333332 + uops: 52 +- name: REX64 REPE OUTSB + operands: [] + latency: ~ + port_pressure: [[5, '0'], [1, '01'], [1, '015'], [4, '0156'], [1, '05'], [20, '06'], [12, '1'], [1, '15'], [7, '5']] + throughput: 17.333333333333332 + uops: 52 +- name: REPNE OUTSB + operands: [] + latency: ~ + port_pressure: [[5, '0'], [1, '01'], [1, '015'], [4, '0156'], [1, '05'], [20, '06'], [12, '1'], [1, '15'], [7, '5']] + throughput: 17.333333333333332 + uops: 52 +- name: REX64 REPNE OUTSB + operands: [] + latency: ~ + port_pressure: [[5, '0'], [1, '01'], [1, '015'], [4, '0156'], [1, '05'], [20, '06'], [12, '1'], [1, '15'], [7, '5']] + throughput: 17.333333333333332 + uops: 52 +- name: REPE OUTSD + operands: [] + latency: ~ + port_pressure: [[6, '0'], [2, '015'], [5, '0156'], [19, '06'], [12, '1'], [1, '15'], [7, '5']] + throughput: 17.416666666666668 + uops: 52 +- name: REX64 REPE OUTSD + operands: [] + latency: ~ + port_pressure: [[6, '0'], [2, '015'], [5, '0156'], [19, '06'], [12, '1'], [1, '15'], [7, '5']] + throughput: 17.416666666666668 + uops: 52 +- name: REPNE OUTSD + operands: [] + latency: ~ + port_pressure: [[6, '0'], [2, '015'], [5, '0156'], [19, '06'], [12, '1'], [1, '15'], [7, '5']] + throughput: 17.416666666666668 + uops: 52 +- name: REX64 REPNE OUTSD + operands: [] + latency: ~ + port_pressure: [[6, '0'], [2, '015'], [5, '0156'], [19, '06'], [12, '1'], [1, '15'], [7, '5']] + throughput: 17.416666666666668 + uops: 52 +- name: XLAT + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: SMSW + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0156'], [2, '06'], [1, '5']] + throughput: 1.25 + uops: 4 +- name: AND + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX AND + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: JLE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: CPUID + operands: [] + latency: ~ + port_pressure: [[5, '0156'], [2, '06'], [1, '5']] + throughput: 2.25 + uops: 165 +- name: RDTSC + operands: [] + latency: ~ + port_pressure: [[5, '0156'], [2, '06'], [1, '5']] + throughput: 2.25 + uops: 18 +- name: CDQ + operands: [] + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: INSB + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [2, '06'], [1, '23'], [1, '237'], [1, '4'], [1, '5']] + throughput: 1.5 + uops: 69 +- name: INSD + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [2, '06'], [1, '23'], [1, '237'], [1, '4'], [1, '5']] + throughput: 1.5 + uops: 69 +- name: IMUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: REX IMUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: IMUL + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: RCR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '0156'], [1, '06']] + throughput: 1.0 + uops: 3 +- name: REX RCR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '0156'], [1, '06']] + throughput: 1.0 + uops: 3 +- name: RCL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '0156'], [1, '06']] + throughput: 1.0 + uops: 3 +- name: REX RCL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '0156'], [1, '06']] + throughput: 1.0 + uops: 3 +- name: INSW + operands: [] + latency: ~ + port_pressure: [[2, '0156'], [2, '06'], [1, '23'], [1, '237'], [1, '4'], [1, '5']] + throughput: 1.5 + uops: 69 +- name: STOSW + operands: [] + latency: 0 + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: IN + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: ~ + port_pressure: [[10, '0156'], [9, '06'], [3, '23'], [1, '5']] + throughput: 7.0 + uops: 71 +- name: IN + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[10, '0156'], [9, '06'], [3, '23'], [1, '5']] + throughput: 7.0 + uops: 70 +- name: BT + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: POP + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: 1 +- name: JRCXZ + operands: + - class: identifier + latency: ~ + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 2 +- name: SAHF + operands: [] + latency: 0 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: LMSW + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[3, '015'], [2, '0156'], [10, '06'], [1, '1'], [1, '23'], [1, '237'], [2, '4'], [4, '5']] + throughput: 6.5 + uops: 24 +- name: REPE CMPSD + operands: [] + latency: ~ + port_pressure: [[7, '015'], [11, '06'], [1, '1'], [3, '23'], [1, '5']] + throughput: 7.833333333333334 + uops: 23 +- name: OR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX OR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REPE CMPSB + operands: [] + latency: ~ + port_pressure: [[7, '015'], [11, '06'], [1, '1'], [3, '23'], [1, '5']] + throughput: 7.833333333333334 + uops: 23 +- name: REX64 REPE CMPSB + operands: [] + latency: ~ + port_pressure: [[7, '015'], [11, '06'], [1, '1'], [3, '23'], [1, '5']] + throughput: 7.833333333333334 + uops: 23 +- name: REPE CMPSW + operands: [] + latency: ~ + port_pressure: [[7, '015'], [1, '0156'], [10, '06'], [1, '1'], [2, '23'], [1, '5']] + throughput: 7.583333333333334 + uops: 22 +- name: CLTS + operands: [] + latency: ~ + port_pressure: [[4, '06'], [2, '5']] + throughput: 2.0 + uops: 6 +- name: REPNE CMPSW + operands: [] + latency: ~ + port_pressure: [[7, '015'], [10, '06'], [1, '1'], [2, '23'], [1, '5']] + throughput: 7.333333333333334 + uops: 22 +- name: ROL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: REX ROL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: VERW + operands: + - class: register + name: gpr + latency: 65 + port_pressure: [[3, '0'], [6, '06'], [4, '1'], [4, '23'], [3, '5']] + throughput: 6.0 + uops: 20 +- name: JMP + operands: + - class: register + name: gpr + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JMP + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: ROR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: REX ROR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: SETLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SUB + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX SUB + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: NEG + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX NEG + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: SETNLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETNLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: ADD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX ADD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: ADC + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX ADC + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156'], [1, '06']] + throughput: 0.75 + uops: 1 +- name: CWDE + operands: [] + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: BSF + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SETZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REX SETZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: DEC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REX DEC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: SETBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: REX SETBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '06']] + throughput: 1.0 + uops: 2 +- name: BSWAP + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '06'], [1, '15']] + throughput: 0.5 + uops: 2 +- name: UNPCKHPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: DIVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 12 + port_pressure: [[1, '0'], [5, [0DV]]] + throughput: 5.0 + uops: 1 +- name: ADDSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CVTPI2PS + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 7 + port_pressure: [[2, '0']] + throughput: 2.0 + uops: 2 +- name: CMPSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: ANDNPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CVTTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, '0'], [1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 3 +- name: ORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: DIVSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 12 + port_pressure: [[1, '0'], [5, [0DV]]] + throughput: 5.0 + uops: 1 +- name: RCPSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: SQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [3, [0DV]]] + throughput: 3.0 + uops: 1 +- name: SUBSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CMPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: XORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: SUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: SHUFPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MINSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: ADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CVTSI2SS + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 8 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: SFENCE + operands: [] + latency: ~ + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: RSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: UNPCKLPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MULSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: SQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [3, [0DV]]] + throughput: 3.0 + uops: 1 +- name: CVTTPS2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 9 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: RSQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: MINPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CVTPS2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 9 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: MULPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CVTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, '0'], [1, '015']] + throughput: 1.3333333333333333 + uops: 3 +- name: ANDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: MAXPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: COMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: RCPPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: MAXSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: UCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: UNPCKHPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PUNPCKHDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: CVTTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: DIVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 15 + port_pressure: [[1, '0'], [8, [0DV]]] + throughput: 8.0 + uops: 1 +- name: PCMPGTW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PCMPGTB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PCMPGTD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: CVTPI2PD + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PACKUSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: ANDNPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PSLLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: UNPCKLPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSADBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PADDUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PADDUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: CVTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PACKSSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMULLW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: DIVSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 15 + port_pressure: [[1, '0'], [8, [0DV]]] + throughput: 8.0 + uops: 1 +- name: PCMPEQW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PCMPEQB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PCMPEQD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PUNPCKLWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: ORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PXOR + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CMPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PSUBB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PSUBUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PMAXSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: CVTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: PADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PADDB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PSRLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PADDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PADDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PUNPCKHQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CMPSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PMULHUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: MINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CVTTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 7 + port_pressure: [[1, '0'], [1, '015']] + throughput: 1.3333333333333333 + uops: 2 +- name: ADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: POR + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CVTSD2SS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: PSLLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: SQRTSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 19 + port_pressure: [[1, '0'], [6, [0DV]]] + throughput: 6.0 + uops: 1 +- name: PSLLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: CVTSI2SD + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: PSLLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PSUBUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MULSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PANDN + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: SHUFPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: SUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: SQRTPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 19 + port_pressure: [[1, '0'], [6, [0DV]]] + throughput: 6.0 + uops: 1 +- name: ANDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PMULHW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PMINSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: CVTTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: PSHUFD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CVTSS2SD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: XORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: MAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: MINPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: ADDSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PSRLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PSRLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PSRLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: SUBSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PADDSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: LFENCE + operands: [] + latency: ~ + port_pressure: [[2, '0156']] + throughput: 0.5 + uops: 0 +- name: CVTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 7 + port_pressure: [[1, '0'], [1, '015']] + throughput: 1.3333333333333333 + uops: 2 +- name: CVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: MULPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PSUBQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PSUBQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PUNPCKHBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMULUDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMULUDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PMADDWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PEXTRW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PAND + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CVTDQ2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PMAXUB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CVTPD2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: CVTPD2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: MFENCE + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: PSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MAXPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PMINUB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PAVGW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PSUBSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PAVGB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PSRAW + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: COMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAD + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PACKSSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PUNPCKLBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: UCOMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: CVTTPD2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: PSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: FCHS + operands: [] + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: ~ +- name: FUCOM + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FLDL2T + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: FLDL2E + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: FYL2X + operands: [] + latency: ~ + port_pressure: [[2, '0'], [2, '0156'], [2, '05'], [2, '06'], [3, '5']] + throughput: 4.5 + uops: ~ +- name: FADDP + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FXTRACT + operands: [] + latency: ~ + port_pressure: [[1, '05'], [2, '5']] + throughput: 2.5 + uops: ~ +- name: FCOMPP + operands: [] + latency: ~ + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: ~ +- name: FYL2XP1 + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FRNDINT + operands: [] + latency: ~ + port_pressure: [[5, '0'], [3, '0156'], [2, '05'], [2, '06'], [6, '5']] + throughput: 7.75 + uops: ~ +- name: FNCLEX + operands: [] + latency: ~ + port_pressure: [[4, '0156']] + throughput: 1.0 + uops: ~ +- name: FPTAN + operands: [] + latency: ~ + port_pressure: [[4, '0'], [1, '5']] + throughput: 4.0 + uops: ~ +- name: FCOS + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '0156'], [3, '06'], [7, '5']] + throughput: 9.5 + uops: ~ +- name: FSCALE + operands: [] + latency: ~ + port_pressure: [[1, '0'], [3, '0156'], [1, '06'], [2, '5']] + throughput: 2.75 + uops: ~ +- name: FXAM + operands: [] + latency: ~ + port_pressure: [[2, '5']] + throughput: 2.0 + uops: ~ +- name: FPREM1 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: FNINIT + operands: [] + latency: ~ + port_pressure: [[6, '0156'], [3, '05'], [6, '5']] + throughput: 9.0 + uops: ~ +- name: FNOP + operands: [] + latency: ~ + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: FLDPI + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: FNSTSW + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '0156']] + throughput: 1.25 + uops: ~ +- name: FWAIT + operands: [] + latency: ~ + port_pressure: [[2, '0156']] + throughput: 0.5 + uops: ~ +- name: F2XM1 + operands: [] + latency: ~ + port_pressure: [[3, '0'], [3, '0156'], [3, '06'], [3, '5']] + throughput: 5.25 + uops: ~ +- name: FPREM + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '0156'], [2, '05'], [1, '5']] + throughput: 2.25 + uops: ~ +- name: FINCSTP + operands: [] + latency: ~ + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: FTST + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FPATAN + operands: [] + latency: ~ + port_pressure: [[26, '0'], [10, '0156'], [2, '05'], [5, '06'], [12, '5']] + throughput: 32.0 + uops: ~ +- name: FABS + operands: [] + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: ~ +- name: FSIN + operands: [] + latency: ~ + port_pressure: [[8, '0'], [3, '0156'], [4, '06'], [7, '5']] + throughput: 10.75 + uops: ~ +- name: FLDLN2 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: FXCH + operands: [] + latency: ~ + port_pressure: [[2, '0'], [4, '0156'], [2, '05'], [4, '06'], [1, '1'], [2, '5']] + throughput: 6.0 + uops: ~ +- name: FDECSTP + operands: [] + latency: ~ + port_pressure: [[2, '05']] + throughput: 1.0 + uops: ~ +- name: FLDLG2 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: FLDZ + operands: [] + latency: ~ + port_pressure: [[1, '05']] + throughput: 0.5 + uops: ~ +- name: FUCOMPP + operands: [] + latency: ~ + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: ~ +- name: FLD1 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '05']] + throughput: 1.5 + uops: ~ +- name: FSINCOS + operands: [] + latency: ~ + port_pressure: [[2, '0'], [1, '05'], [3, '5']] + throughput: 3.5 + uops: ~ +- name: PUNPCKHDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PCMPGTW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PCMPGTB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PCMPGTD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PACKUSWB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [2, '5']] + throughput: 2.25 + uops: 2 +- name: PSUBD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PSADBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PADDUSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PADDUSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PACKSSDW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [2, '5']] + throughput: 2.25 + uops: 2 +- name: PMULLW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PCMPEQW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PCMPEQB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PCMPEQD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PUNPCKLWD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PADDSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PXOR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PSUBB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PSUBUSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PADDW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PMAXSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PADDD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PADDB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PMULHUW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: POR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PSLLD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLW + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLQ + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBUSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PUNPCKLDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PANDN + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PMULHW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMINSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSHUFW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSRLQ + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLW + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PADDSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: EMMS + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [9, '05']] + throughput: 4.75 + uops: 10 +- name: PUNPCKHBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMADDWD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PEXTRW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PAND + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PMAXUB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PUNPCKHWD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMINUB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PAVGW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PAVGB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAW + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PACKSSWB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0156'], [2, '5']] + throughput: 2.25 + uops: 2 +- name: PUNPCKLBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: REPE SCASQ + operands: [] + latency: ~ + port_pressure: [[11, '0156'], [5, '06'], [1, '15'], [1, '23']] + throughput: 5.25 + uops: 18 +- name: CMPSQ + operands: [] + latency: 4 + port_pressure: [[3, '0156'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: LODSQ + operands: [] + latency: ~ + port_pressure: [[1, '0156'], [1, '23']] + throughput: 0.5 + uops: 2 +- name: CDQE + operands: [] + latency: 1 + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: 1 +- name: REPE LODSQ + operands: [] + latency: ~ + port_pressure: [[7, '015'], [9, '06'], [1, '1'], [3, '23']] + throughput: 6.833333333333334 + uops: 20 +- name: REPNE LODSQ + operands: [] + latency: ~ + port_pressure: [[7, '015'], [9, '06'], [1, '1'], [3, '23']] + throughput: 6.833333333333334 + uops: 20 +- name: SYSCALL + operands: [] + latency: ~ + port_pressure: [[1, '0156']] + throughput: 0.25 + uops: ~ +- name: REPNE CMPSQ + operands: [] + latency: ~ + port_pressure: [[7, '015'], [1, '0156'], [10, '06'], [1, '1'], [2, '23'], [1, '5']] + throughput: 7.583333333333334 + uops: 22 +- name: PUSHFQ + operands: [] + latency: 7 + port_pressure: [[1, '237'], [1, '4']] + throughput: 1.0 + uops: 4 +- name: REPE STOSQ + operands: [] + latency: ~ + port_pressure: [[2, '01'], [13, '015'], [2, '05'], [25, '06'], [3, '1'], [2, '15'], [10, '23'], [8, '4'], [9, '5']] + throughput: 18.833333333333332 + uops: 74 +- name: REPNE STOSQ + operands: [] + latency: ~ + port_pressure: [[2, '01'], [13, '015'], [2, '05'], [25, '06'], [3, '1'], [2, '15'], [10, '23'], [8, '4'], [9, '5']] + throughput: 18.833333333333332 + uops: 74 +- name: SCASQ + operands: [] + latency: 1 + port_pressure: [[2, '0156'], [1, '23']] + throughput: 0.5 + uops: 3 +- name: REPNE SCASQ + operands: [] + latency: ~ + port_pressure: [[5, '015'], [1, '0156'], [10, '06'], [1, '1'], [1, '5']] + throughput: 6.916666666666667 + uops: 18 +- name: POPFQ + operands: [] + latency: ~ + port_pressure: [[3, '0156'], [2, '06'], [1, '1'], [1, '23']] + throughput: 1.75 + uops: 7 +- name: STOSQ + operands: [] + latency: 0 + port_pressure: [[1, '0156'], [1, '237'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: CQO + operands: [] + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: REPE CMPSQ + operands: [] + latency: ~ + port_pressure: [[7, '015'], [10, '06'], [1, '1'], [2, '23'], [1, '5']] + throughput: 7.333333333333334 + uops: 22 +- name: POPCNT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ROUNDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 2 +- name: ROUNDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 2 +- name: PCMPGTQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PBLENDW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PHMINPOSUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: INSERTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMULLD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 2 +- name: PCMPEQQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PACKUSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: EXTRACTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMAXSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: BLENDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PTEST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMULDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PMINSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: CRC32 + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: REX CRC32 + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: DPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 9 + port_pressure: [[2, '015'], [1, '5']] + throughput: 1.6666666666666665 + uops: 3 +- name: DPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[3, '015'], [1, '5']] + throughput: 2.0 + uops: 4 +- name: PEXTRD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMAXUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PMAXUD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: BLENDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PEXTRB + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMINUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PMINUD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: BLENDVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 1 +- name: BLENDVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 1 +- name: ROUNDSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 2 +- name: ROUNDSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 2 +- name: PEXTRQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PBLENDVB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 1 +- name: PHSUBD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '05'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PHSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: PMULHRSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMULHRSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PHSUBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '05'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PHSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: PSIGNW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PSIGNW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PSIGND + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PSIGND + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PSIGNB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PSIGNB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PHADDSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: PHADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: PMADDUBSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMADDUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PHSUBSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '0'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: PHSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: PABSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PABSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PHADDD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '05'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PHADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: PALIGNR + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PALIGNR + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSHUFB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PABSD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PABSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PABSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PABSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: PHADDW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '05'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: PHADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: ADDSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: ADDSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: HSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: HSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: HADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: HADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: XSETBV + operands: [] + latency: ~ + port_pressure: [[4, '0156'], [1, '06']] + throughput: 1.5 + uops: ~ +- name: XGETBV + operands: [] + latency: ~ + port_pressure: [[2, '0156']] + throughput: 0.5 + uops: ~ +- name: TZCNT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: BLSMSK + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: ANDN + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: BEXTR + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '06'], [1, '15']] + throughput: 0.5 + uops: 2 +- name: BLSI + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: BLSR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: RDTSCP + operands: [] + latency: ~ + port_pressure: [[20, '0156'], [2, '5']] + throughput: 7.0 + uops: 20 +- name: AESKEYGENASSIST + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 12 + port_pressure: [[3, '0'], [2, '015'], [6, '5']] + throughput: 6.666666666666667 + uops: 13 +- name: AESIMC + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '0']] + throughput: 2.0 + uops: 2 +- name: STAC + operands: [] + latency: ~ + port_pressure: [[1, '06']] + throughput: 0.5 + uops: ~ +- name: CLAC + operands: [] + latency: ~ + port_pressure: [[1, '06']] + throughput: 0.5 + uops: ~ +- name: ADOX + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: ADCX + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: MWAIT + operands: [] + latency: ~ + port_pressure: [[7, '0156'], [2, '06'], [1, '5']] + throughput: 2.75 + uops: ~ +- name: RDSEED + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[3, '015'], [1, '0156'], [9, '06'], [2, '1'], [1, '23']] + throughput: 5.75 + uops: 16 +- name: LZCNT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PCLMULQDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: RDRAND + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[3, '015'], [1, '0156'], [9, '06'], [2, '1'], [1, '23']] + throughput: 5.75 + uops: 16 +- name: PAUSE + operands: [] + latency: ~ + port_pressure: [[3, '0156'], [1, '06']] + throughput: 1.25 + uops: 1 +- name: VPMULHUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULUDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRCPSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMULHRSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPERM2F128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VHADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 3 +- name: VHADDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 3 +- name: VPUNPCKLBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPEQW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPAVGW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPAVGB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VANDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPMAXSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VANDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VMULSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMAXSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPTEST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPTEST + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPACKSSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPXOR + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VSQRTSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 19 + port_pressure: [[1, '0'], [6, [0DV]]] + throughput: 6.0 + uops: 1 +- name: VEXTRACTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [3, [0DV]]] + throughput: 3.0 + uops: 1 +- name: VUNPCKHPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCOMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VZEROALL + operands: [] + latency: ~ + port_pressure: [[16, '0156']] + throughput: 4.0 + uops: 10 +- name: VCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRAD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSHUFD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSRAW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSHUFB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VDIVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 15 + port_pressure: [[1, '0'], [4, [0DV]]] + throughput: 4.0 + uops: 1 +- name: VDIVPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 15 + port_pressure: [[1, '0'], [8, [0DV]]] + throughput: 8.0 + uops: 1 +- name: VDIVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 12 + port_pressure: [[1, '0'], [3, [0DV]]] + throughput: 3.0 + uops: 1 +- name: VDIVPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 12 + port_pressure: [[1, '0'], [5, [0DV]]] + throughput: 5.0 + uops: 1 +- name: VCMPSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSLLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCMPSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPAND + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPHADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: VPANDN + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VSHUFPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSUBSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0'], [3, [0DV]]] + throughput: 3.0 + uops: 1 +- name: VSQRTPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 13 + port_pressure: [[1, '0'], [6, [0DV]]] + throughput: 6.0 + uops: 1 +- name: VCVTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPS2DQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPHADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: VSQRTPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 19 + port_pressure: [[1, '0'], [6, [0DV]]] + throughput: 6.0 + uops: 1 +- name: VSQRTPD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 19 + port_pressure: [[1, '0'], [12, [0DV]]] + throughput: 12.0 + uops: 1 +- name: VSUBSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSHUFPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMULDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VDPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 9 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 3 +- name: VDPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[3, '01']] + throughput: 1.5 + uops: 4 +- name: VDPPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 13 + port_pressure: [[3, '01']] + throughput: 1.5 + uops: 4 +- name: VPUNPCKHDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTPD2DQ + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, '0'], [1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 3 +- name: VMULPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VINSERTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPALIGNR + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMAXPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMAXPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPACKUSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMAXPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMAXPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKHQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSIGNW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSIGNB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VUNPCKHPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKLWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSIGND + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULHW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VXORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VXORPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VROUNDSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VROUNDSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VPMADDUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VXORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VXORPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VINSERTF128 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VHSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 3 +- name: VHSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 3 +- name: VHSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 3 +- name: VHSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 3 +- name: VHADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 3 +- name: VHADDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 3 +- name: VCVTTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPS2DQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VTESTPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VTESTPD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VDIVSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 12 + port_pressure: [[1, '0'], [3, [0DV]]] + throughput: 3.0 + uops: 1 +- name: VDIVSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 15 + port_pressure: [[1, '0'], [4, [0DV]]] + throughput: 4.0 + uops: 1 +- name: VTESTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VTESTPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, '0'], [1, '015']] + throughput: 1.3333333333333333 + uops: 3 +- name: VMINSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPABSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPHADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCMPGTB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VZEROUPPER + operands: [] + latency: ~ + port_pressure: [[1, '015'], [3, '0156']] + throughput: 1.0833333333333333 + uops: 0 +- name: VANDNPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDNPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPABSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VBLENDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VBLENDPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VBLENDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VBLENDPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VRSQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRTPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPEXTRB + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPEXTRD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPHSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: VPEXTRQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPEXTRW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPHSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: VADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPBLENDW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPOR + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULLD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VUCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMULLW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VUCOMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTF128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKUSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKLQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSRLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPERMILPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMINPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMINPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTDQ2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTDQ2PS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKLDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VMINPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMINPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSADBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VROUNDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VROUNDPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VROUNDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VROUNDPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VPSUBSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCLMULQDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VRCPPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCPPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VCVTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 7 + port_pressure: [[1, '0'], [1, '015']] + throughput: 1.3333333333333333 + uops: 2 +- name: VORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VORPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VORPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPMINUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VUNPCKLPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINUD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VUNPCKLPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTTPD2DQ + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VPCMPGTD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMADDWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCMPGTQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPHMINPOSUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPABSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKHWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPHSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VCVTTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 7 + port_pressure: [[1, '0'], [1, '015']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTPD2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTPD2PS + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VADDSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPACKSSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VADDSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VCVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VPMULHUW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULUDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLDQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMULHRSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKLBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPEQW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPAVGW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPAVGB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLVQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLVQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLDQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINSD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPACKSSDW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPXOR + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSRAD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSHUFD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSRAW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSHUFB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSLLD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPAND + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPHADDW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: VPANDN + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPHADDD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: VPMULDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKHDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPALIGNR + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPACKUSWB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHQDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSIGNW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSIGNB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDUSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKLWD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDUSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSIGND + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPBROADCASTD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTB + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMULHW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPBROADCASTW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTW + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMADDUBSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPABSW + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPHADDSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VPSUBUSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBUSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCMPGTB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPABSB + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPHSUBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: VPHSUBD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: VPBLENDW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPOR + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPMULLD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 10 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VPMULLW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPERM2I128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKUSDW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXUW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKLQDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSRLD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VBROADCASTSD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTSS + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTQ + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSUBB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSADBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSUBSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VINSERTI128 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTI128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSUBSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPBLENDD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPMINUW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPERMPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINUD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPERMPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMADDWD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCMPGTQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPABSD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKHWD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPHSUBSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VPSLLVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPACKSSWB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSLLVQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLVQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: KXNORQ + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KXNORW + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KXNORB + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KXNORD + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KXORQ + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KUNPCKDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: KORD + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KORQ + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KSHIFTRQ + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: KORTESTW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KORTESTQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KORTESTD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KORTESTB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KANDNB + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KADDW + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KADDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KANDB + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KANDND + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KANDW + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KADDD + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KANDNQ + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KANDNW + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KANDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KADDB + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KTESTW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KTESTQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KNOTQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KNOTW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KNOTB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KNOTD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KUNPCKWD + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: KUNPCKBW + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: KTESTB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KSHIFTLQ + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: KXORB + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KANDD + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KXORW + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KTESTD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KSHIFTRW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: KSHIFTRB + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: KSHIFTRD + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: KORB + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KXORD + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: KSHIFTLD + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: KSHIFTLB + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: KSHIFTLW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: KORW + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VCVTPH2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VCVTPH2PS + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VCVTPS2PH + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTPS2PH + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VAESDEC + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VAESDECLAST + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VAESIMC + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '0']] + throughput: 2.0 + uops: 2 +- name: VAESENC + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VAESENCLAST + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VAESKEYGENASSIST + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 12 + port_pressure: [[3, '0'], [2, '015'], [6, '5']] + throughput: 6.666666666666667 + uops: 13 +- name: SHRX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: SARX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: BZHI + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PDEP + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: RORX + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: MULX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0156'], [1, '06'], [1, '1']] + throughput: 1.25 + uops: 3 +- name: SHLX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '06']] + throughput: 0.5 + uops: 1 +- name: PEXT + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VFPCLASSSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VFPCLASSSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTNMW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTNMW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTNMW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPMULHUW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULHUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMULHUW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULHUW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULHUW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPMULHUW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 8 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VRSQRT14SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRT14SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPROLVD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPROLVD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPROLVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPROLVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPROLVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPROLVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADDSUB231PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADDSUB231PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRSQRT14SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRT14SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VFMADDSUB231PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADDSUB231PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADDSUB231PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPTESTNMQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTNMQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTNMQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPROLVQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPROLVQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPROLVQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPROLVQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPROLVQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPROLVQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VREDUCEPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VREDUCEPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VREDUCEPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VREDUCEPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VREDUCEPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VREDUCEPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPMULUDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPMULUDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMULUDQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULUDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMULUDQ' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULUDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPROLQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPROLQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPROLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPROLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPROLQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPROLQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSLLDQ' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSLLDQ' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSLLDQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTERNLOGQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPTERNLOGQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPTERNLOGQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPTERNLOGQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPTERNLOGQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPTERNLOGQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VRANGESD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRANGESD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPS2UQQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VCVTPS2UQQ + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VCVTPS2UQQ + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VPTERNLOGD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPTERNLOGD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPTERNLOGD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPTERNLOGD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPTERNLOGD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPTERNLOGD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VRANGESS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRANGESS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMULHRSW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULHRSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMULHRSW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULHRSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULHRSW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPMULHRSW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 8 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUBADD231PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUBADD231PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUB132PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUB132PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUB132PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUB132PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VINSERTF64X2 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTF64X2 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTF64X2 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTF64X2 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPUNPCKLBW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPUNPCKLBW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLBW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLBW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTF64X4 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTF64X4 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTTPD2UQQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPD2UQQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPD2UQQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPD2UQQ + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPD2UQQ + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VCVTTPD2UQQ + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VINSERTI32X4 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTI32X4 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTI32X4 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTI32X4 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPERMD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPLZCNTD + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPLZCNTD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPLZCNTD + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPLZCNTD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPLZCNTD + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPH2PS + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: '{evex} VCVTPH2PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: '{evex} VCVTPH2PS' + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VPERMQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPERMQ' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPERMQ' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPERMW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPERMW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPLZCNTQ + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPLZCNTQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPLZCNTQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPLZCNTQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPLZCNTQ + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPS2QQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VCVTTPS2QQ + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VCVTTPS2QQ + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VEXTRACTF64X4 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTF64X4 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VFNMADD213SS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPERMILPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPERMILPS' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPERMILPS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPERMILPS' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPERMILPS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VFNMADD213SD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMSUB213SD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VMAXSS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMAXSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSCALEFPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VSCALEFPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VSCALEFPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSCALEFPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSCALEFPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSCALEFPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPCMPEQQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPCMPEQQ' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPAVGW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPAVGW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPAVGW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPAVGW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPAVGW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPAVGW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPCMPEQD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPCMPEQD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPCMPEQD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSCALEFPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VSCALEFPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VSCALEFPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSCALEFPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSCALEFPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSCALEFPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPCMPEQB' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPCMPEQB' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPEQB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPEXTRW' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPBLENDMQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPBLENDMQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPBLENDMQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDMQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDMQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDMQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPMAXSD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMAXSD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPMAXSD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMAXSD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLVQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLVQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSRLVQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLVQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSRLVQ' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLVQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMAXSB' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMAXSB' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMAXSB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLVW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLVW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLVW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLVW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLVW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLVW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPBLENDMW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDMW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDMW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDMW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDMW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPBLENDMW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VMULSS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VANDPD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VANDPD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VANDPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMAXSW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMAXSW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMAXSW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPBLENDMB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDMB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDMB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDMB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDMB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPBLENDMB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPBLENDMD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPBLENDMD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPBLENDMD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDMD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDMD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPBLENDMD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSRLVD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLVD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSRLVD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSRLVD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXSQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXSQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXSQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXSQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXSQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXSQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VANDPS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VANDPS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VANDPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VMULSD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VMULPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VMULPS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VMULPS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSRLDQ' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSRLDQ' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSRLDQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VGETMANTSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETMANTSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPD2UDQ + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VCVTTPD2UDQ + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VCVTTPD2UDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTTPD2UDQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTTPD2UDQ + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTTPD2UDQ + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: '{evex} VPSHUFHW' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSHUFHW' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VGETMANTSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETMANTSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPANDND + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPANDND + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPANDND + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDND + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDND + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDND + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPCONFLICTQ + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 17 + port_pressure: [[7, '0'], [5, '05'], [9, '5']] + throughput: 11.5 + uops: 22 +- name: VPCONFLICTQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: VPCONFLICTQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 13 + port_pressure: [[5, '01'], [4, '015'], [5, '5']] + throughput: 6.333333333333333 + uops: 15 +- name: '{evex} VORPD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VORPD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VORPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VORPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VORPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPCONFLICTD + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 26 + port_pressure: [[11, '0'], [7, '05'], [17, '5']] + throughput: 20.5 + uops: 37 +- name: VPCONFLICTD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 11 + port_pressure: [[5, '01'], [4, '015'], [5, '5']] + throughput: 6.333333333333333 + uops: 15 +- name: VPCONFLICTD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 16 + port_pressure: [[7, '01'], [5, '015'], [9, '5']] + throughput: 10.666666666666666 + uops: 22 +- name: VPANDNQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPANDNQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPANDNQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDNQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDNQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDNQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VMAXSD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMINSD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPMINSD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMINSD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMINSB' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMINSB' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMINSB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VFMSUB213PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUB213PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUB213PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPS2QQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VCVTPS2QQ + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VCVTPS2QQ + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: '{evex} VPMINSW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMINSW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINSW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMINSW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMINSQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINSQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINSQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINSQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINSQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINSQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTI32X2 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTI32X2 + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTI32X2 + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTI32X2 + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTI32X2 + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTI32X2 + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VFMSUB213PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUB213PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUB213PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPACKSSDW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKSSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPACKSSDW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKSSDW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKSSDW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKSSDW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTPD2UDQ + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VCVTPD2UDQ + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VCVTPD2UDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTPD2UDQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTPD2UDQ + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTPD2UDQ + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VFPCLASSPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VFPCLASSPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VFPCLASSPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VFPCLASSPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VFPCLASSPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VFPCLASSPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VSQRTSD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 19 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VSQRTSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 14 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VORPS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VORPS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VORPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VORPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VORPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VEXTRACTPS' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VSHUFF32X4 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFF32X4 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFF32X4 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFF32X4 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VSQRTSS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VUNPCKHPD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VUNPCKHPD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VCOMISD' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VCOMISS' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRAD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRAD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSRAD' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSRAD' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSHUFD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSHUFD' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSHUFD' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSRAW' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSRAW' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAW + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRAW + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSHUFB' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSHUFB' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPCMPGTB' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPCMPGTB' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VDIVPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 18 + port_pressure: [[2, '0'], [1, '05'], [10, [0DV]]] + throughput: 10.0 + uops: 3 +- name: VDIVPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 18 + port_pressure: [[2, '0'], [1, '05'], [10, [0DV]]] + throughput: 10.0 + uops: 3 +- name: '{evex} VDIVPS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 12 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VDIVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 12 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VDIVPS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 12 + port_pressure: [[1, '0'], [5, [0DV]]] + throughput: 5.0 + uops: 1 +- name: VDIVPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 12 + port_pressure: [[1, '0'], [5, [0DV]]] + throughput: 5.0 + uops: 1 +- name: '{evex} VCMPSS' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSHUFLW' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSHUFLW' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VFMSUB132SS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUBADD213PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUBADD213PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VCMPSD' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSLLQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSLLQ' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSLLQ' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUBADD213PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUBADD213PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSLLW' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSLLW' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLW + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLW + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VFMSUB132SD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB132SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPERMI2PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VFMSUB231SD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSHUFPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VSHUFPD' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VSHUFPD' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VSUBSD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSQRTPS + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 20 + port_pressure: [[2, '0'], [1, '05'], [12, [0DV]]] + throughput: 12.0 + uops: 3 +- name: VSQRTPS + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 20 + port_pressure: [[2, '0'], [1, '05'], [12, [0DV]]] + throughput: 12.0 + uops: 3 +- name: '{evex} VSQRTPS' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VSQRTPS + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VSQRTPS' + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 13 + port_pressure: [[1, '0'], [6, [0DV]]] + throughput: 6.0 + uops: 1 +- name: VSQRTPS + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 13 + port_pressure: [[1, '0'], [6, [0DV]]] + throughput: 6.0 + uops: 1 +- name: VPANDD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPANDD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPANDD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VCVTPS2DQ + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VCVTPS2DQ + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VCVTPS2DQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VCVTPS2DQ' + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPS2DQ + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPERMI2PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPANDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPANDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPANDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPANDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VSQRTPD + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 32 + port_pressure: [[2, '0'], [1, '05'], [24, [0DV]]] + throughput: 24.0 + uops: 3 +- name: VSQRTPD + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 24 + port_pressure: [[2, '0'], [1, '05'], [24, [0DV]]] + throughput: 24.0 + uops: 3 +- name: '{evex} VSQRTPD' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 19 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VSQRTPD + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 14 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VSQRTPD' + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 19 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VSQRTPD + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 14 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VSUBSS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSHUFPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VSHUFPS' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VSHUFPS' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VFNMADD213PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMADD213PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMADD213PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUB231PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUB231PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VDBPSADBW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VDBPSADBW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VDBPSADBW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VDBPSADBW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VDBPSADBW + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VDBPSADBW + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPROLD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPROLD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPROLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPROLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPROLD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPROLD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VEXPANDPD + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VEXPANDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VEXPANDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VFMSUB231PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUB231PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUB231PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMADD213PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMADD213PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VEXPANDPS + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VEXPANDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VEXPANDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPMULDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPMULDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMULDQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMULDQ' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKHDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPUNPCKHDQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPUNPCKHDQ' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTPD2DQ + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VCVTPD2DQ + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: '{evex} VCVTPD2DQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: '{evex} VCVTPD2DQ' + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTPD2DQ + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: '{evex} VCVTTSS2SI' + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, '0'], [1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 3 +- name: VCVTQQ2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTQQ2PD + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTQQ2PD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTQQ2PD + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTQQ2PD + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VCVTQQ2PD + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUB231SS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB231SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADD231SS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTQQ2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTQQ2PS + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTQQ2PS + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTQQ2PS + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTQQ2PS + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VCVTQQ2PS + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VMULPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VMULPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VMULPD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VMULPD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMULPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADD231SD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCOMPRESSD + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPCOMPRESSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPCOMPRESSD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VCVTTPS2UDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VCVTTPS2UDQ + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VCVTTPS2UDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPS2UDQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPS2UDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPS2UDQ + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCOMPRESSQ + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPCOMPRESSQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPCOMPRESSQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: '{evex} VPADDSW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPADDSW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDSW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPADDSW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VGETMANTPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VGETMANTPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VGETMANTPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETMANTPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETMANTPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETMANTPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VINSERTPS' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPALIGNR' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPALIGNR + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPALIGNR' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPALIGNR + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPALIGNR + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPALIGNR + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPADDSB' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPADDSB' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDSB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPADDSB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VGETMANTPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VGETMANTPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VGETMANTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETMANTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETMANTPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETMANTPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMAXPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VMAXPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VMAXPD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMAXPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VMAXPD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMAXPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPACKUSWB' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKUSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPACKUSWB' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKUSWB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKUSWB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKUSWB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMAXPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VMAXPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VMAXPS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMAXPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VMAXPS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMAXPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKHQDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHQDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPUNPCKHQDQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPUNPCKHQDQ' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHQDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPABSW' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPABSW + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPABSW' + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPABSW + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPABSW + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPABSW + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPABSQ + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPABSQ + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPABSQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPABSQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPABSQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPABSQ + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUB213SD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRCP14SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCP14SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VFMSUB213SS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUB213SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VEXTRACTF32X4 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTF32X4 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTF32X4 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTF32X4 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPABSB' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPABSB + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPABSB' + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPABSB + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPABSB + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPABSB + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCP14SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCP14SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTF32X8 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTF32X8 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPUW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPUW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPUW + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTSD2USI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 7 + port_pressure: [[1, '0'], [1, '015']] + throughput: 1.3333333333333333 + uops: 2 +- name: '{evex} VPADDUSW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPADDUSW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDUSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDUSW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPADDUSW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPADDUSB' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPADDUSB' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDUSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDUSB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPADDUSB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VUNPCKHPS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VUNPCKHPS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTD + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTD + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTD + operands: + - class: register + name: gpr + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPBROADCASTD' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTD + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPBROADCASTD' + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPBROADCASTD' + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTD + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPBROADCASTD' + operands: + - class: register + name: gpr + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VFMADD231PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADD231PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADD231PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSHUFI32X4 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFI32X4 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFI32X4 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFI32X4 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPMULHW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULHW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMULHW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULHW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULHW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPMULHW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 8 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VXORPD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VXORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VXORPD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VXORPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VXORPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VXORPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPERMILPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPERMILPD' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPERMILPD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPERMILPD' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPERMILPD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTQ + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTQ + operands: + - class: register + name: gpr + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPBROADCASTQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPBROADCASTQ' + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPBROADCASTQ' + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPBROADCASTQ' + operands: + - class: register + name: gpr + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPMADDUBSW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMADDUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMADDUBSW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMADDUBSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMADDUBSW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPMADDUBSW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 8 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VRNDSCALEPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 8 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: VRNDSCALEPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 8 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: VRNDSCALEPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VRNDSCALEPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VRNDSCALEPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VRNDSCALEPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: '{evex} VXORPS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VXORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VXORPS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VXORPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VXORPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VXORPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VRNDSCALESS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VRNDSCALESS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: '{evex} VFMADD132SD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VANDNPS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDNPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VANDNPS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDNPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDNPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VANDNPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPSRAVQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRAVQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRAVQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAVQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAVQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAVQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAVW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAVW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAVW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAVW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAVW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRAVW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VINSERTI32X8 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTI32X8 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VFMADD132SS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTUQQ2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTUQQ2PD + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTUQQ2PD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTUQQ2PD + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTUQQ2PD + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VRNDSCALESD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VRNDSCALESD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VPSRAVD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRAVD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSRAVD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSRAVD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPS2DQ + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VCVTTPS2DQ + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VCVTTPS2DQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VCVTTPS2DQ' + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPS2DQ + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VDIVSS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 12 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VDIVSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 12 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VFNMADD231SS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VDIVSD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 15 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VDIVSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 14 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VCVTUQQ2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTUQQ2PS + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTUQQ2PS + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTUQQ2PS + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTUQQ2PS + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VCVTUQQ2PS + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: '{evex} VFNMADD231SD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETEXPSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETEXPSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VCMPPS' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VCMPPS' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VCMPPD' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VCMPPD' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSUBPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VSUBPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VSUBPD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VSUBPD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VANDNPD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VANDNPD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VCVTSS2SI' + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, '0'], [1, '015']] + throughput: 1.3333333333333333 + uops: 3 +- name: '{evex} VMINSS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMINSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFIXUPIMMPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFIXUPIMMPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFIXUPIMMPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFIXUPIMMPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFIXUPIMMPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFIXUPIMMPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VSUBPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VSUBPS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VSUBPS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFIXUPIMMPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFIXUPIMMPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFIXUPIMMPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFIXUPIMMPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFIXUPIMMPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFIXUPIMMPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VBROADCASTF32X2 + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTF32X2 + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTF32X2 + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTF32X2 + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VMINSD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCMPW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPW + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSUBUSB' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSUBUSB' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBUSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBUSB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSUBUSB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPCMPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPB + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPB + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPB + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSUBUSW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSUBUSW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBUSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBUSW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSUBUSW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VFNMSUB132PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMSUB132PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMSUB132PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSHUFI64X2 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFI64X2 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFI64X2 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFI64X2 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VRNDSCALEPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 8 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: VRNDSCALEPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 8 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: VRNDSCALEPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VRNDSCALEPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VRNDSCALEPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VRNDSCALEPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 8 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VGETEXPPS + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VGETEXPPS + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VGETEXPPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETEXPPS + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETEXPPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETEXPPS + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADD132PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADD132PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADD132PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADD132PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETEXPPD + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VGETEXPPD + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VGETEXPPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETEXPPD + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETEXPPD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETEXPPD + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPABSD + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPABSD + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPABSD' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPABSD + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPABSD' + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPABSD + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPADDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPADDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPADDQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VPADDQ' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPCMPUQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPUQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPUQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPADDW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VPADDW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPADDW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPEXPANDD + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPEXPANDD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPEXPANDD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPCMPUB + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPUB + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPUB + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPADDB' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VPADDB' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPADDB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPCMPUD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPUD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPUD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPADDD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPADDD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VPADDD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPADDD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPEXPANDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPEXPANDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VPEXPANDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VCVTTSD2USI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 7 + port_pressure: [[1, '0'], [1, '015']] + throughput: 1.3333333333333333 + uops: 2 +- name: VSHUFF64X2 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFF64X2 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFF64X2 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFF64X2 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTMB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTMB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTMB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPRORQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPRORQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPRORQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPRORQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPRORQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPRORQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMSUB132PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMSUB132PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPRORD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPRORD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPRORD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPRORD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPRORD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPRORD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPEXTRB' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: '{evex} VPEXTRD' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: '{evex} VPEXTRQ' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTPD2QQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPD2QQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPD2QQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPD2QQ + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPD2QQ + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VCVTPD2QQ + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VRCP14PD + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[2, '0'], [1, '05']] + throughput: 2.5 + uops: 3 +- name: VRCP14PD + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 6 + port_pressure: [[2, '0'], [1, '05']] + throughput: 2.5 + uops: 3 +- name: VRCP14PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCP14PD + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCP14PD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCP14PD + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VADDPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VADDPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VADDPD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VADDPD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMSUB132SD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRCP14PS + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[2, '0'], [1, '05']] + throughput: 2.5 + uops: 3 +- name: VRCP14PS + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 6 + port_pressure: [[2, '0'], [1, '05']] + throughput: 2.5 + uops: 3 +- name: VRCP14PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCP14PS + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCP14PS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCP14PS + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VFNMSUB132SS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB132SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VADDPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VADDPS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VADDPS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRAQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRAQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRAQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPTESTMW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTMW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTMW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMULLD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 11 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: '{evex} VPMULLD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: '{evex} VPMULLD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 10 + port_pressure: [[2, '01']] + throughput: 1.0 + uops: 2 +- name: VFNMSUB231PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMSUB231PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMSUB231PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VUCOMISS' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPTESTNMD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTNMD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTNMD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTNMB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTNMB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTNMB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMULLQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 15 + port_pressure: [[3, '015']] + throughput: 1.0 + uops: 3 +- name: VPMULLQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 15 + port_pressure: [[3, '015']] + throughput: 1.0 + uops: 3 +- name: VPMULLQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 15 + port_pressure: [[3, '015']] + throughput: 1.0 + uops: 3 +- name: VPMULLQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 15 + port_pressure: [[3, '015']] + throughput: 1.0 + uops: 3 +- name: '{evex} VPMULLW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULLW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMULLW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULLW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMULLW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPMULLW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 8 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VEXTRACTF64X2 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTF64X2 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTF64X2 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTF64X2 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VUCOMISD' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VFNMSUB231PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMSUB231PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMSUB231PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCOMPRESSPD + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VCOMPRESSPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VCOMPRESSPD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: '{evex} VPUNPCKLWD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPUNPCKLWD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLWD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLWD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLWD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VFNMSUB213SS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCOMPRESSPS + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VCOMPRESSPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VCOMPRESSPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VINSERTI64X2 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTI64X2 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTI64X2 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTI64X2 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTI64X4 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTI64X4 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VALIGNQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VALIGNQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VALIGNQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VALIGNQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VALIGNQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VALIGNQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VREDUCESD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VREDUCESD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VALIGND + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VALIGND + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VALIGND + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VALIGND + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VALIGND + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VALIGND + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VREDUCESS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VREDUCESS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPERMI2W + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: VPERMI2W + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '015'], [2, '5']] + throughput: 2.3333333333333335 + uops: 3 +- name: VPERMI2W + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, '05'], [2, '5']] + throughput: 2.5 + uops: 3 +- name: '{evex} VFMADD213SD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPACKUSDW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKUSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPACKUSDW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKUSDW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKUSDW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKUSDW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMAXUD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPMAXUD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXUD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMAXUD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXUD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPERMI2Q + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2Q + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2Q + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2Q + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2Q + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2Q + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXUQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2D + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2D + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2D + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2D + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2D + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMI2D + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VFMADD213SS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMAXUW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMAXUW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXUW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXUW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMAXUW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VDIVPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 24 + port_pressure: [[2, '0'], [1, '05'], [16, [0DV]]] + throughput: 16.0 + uops: 3 +- name: VDIVPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 23 + port_pressure: [[2, '0'], [1, '05'], [16, [0DV]]] + throughput: 16.0 + uops: 3 +- name: '{evex} VDIVPD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 15 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VDIVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 14 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VDIVPD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 15 + port_pressure: [[1, '0'], [8, [0DV]]] + throughput: 8.0 + uops: 1 +- name: VDIVPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 14 + port_pressure: [[1, '0'], [8, [0DV]]] + throughput: 8.0 + uops: 1 +- name: '{evex} VPSRLW' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSRLW' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLW + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLW + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLW + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLQ + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSRLQ' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSRLQ' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLQ + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPBROADCASTB' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTB + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPBROADCASTB' + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPBROADCASTB' + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTB + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPBROADCASTB' + operands: + - class: register + name: gpr + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTB + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTB + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTB + operands: + - class: register + name: gpr + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLQDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLQDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPUNPCKLQDQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPUNPCKLQDQ' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLQDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VFNMADD132SD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSRLD' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSRLD' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSRLD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMADD132SS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFIXUPIMMSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFIXUPIMMSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTUDQ2PS + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VCVTUDQ2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTUDQ2PS + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTUDQ2PS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTUDQ2PS + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VBROADCASTSD + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTSD + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VBROADCASTSD' + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTSD + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPCMPEQW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPCMPEQW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPEQW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VFIXUPIMMSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFIXUPIMMSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPS2UQQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VCVTTPS2UQQ + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VCVTTPS2UQQ + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VBROADCASTSS + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTSS + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VBROADCASTSS' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTSS + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VBROADCASTSS' + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VBROADCASTSS + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTUDQ2PD + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VCVTUDQ2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VCVTUDQ2PD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VMINPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VMINPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VMINPD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMINPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VMINPD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMINPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTDQ2PS + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VCVTDQ2PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTDQ2PS + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VCVTDQ2PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTDQ2PS + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPRORVQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPRORVQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPRORVQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPRORVQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPRORVQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPRORVQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPTESTMD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTMD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTMD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VFNMSUB213PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMSUB213PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMSUB213PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPBROADCASTW' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTW + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPBROADCASTW' + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPBROADCASTW' + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTW + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPBROADCASTW' + operands: + - class: register + name: gpr + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTW + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTW + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPBROADCASTW + operands: + - class: register + name: gpr + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPUNPCKLDQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPUNPCKLDQ' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTMQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTMQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPTESTMQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTDQ2PD + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: '{evex} VCVTDQ2PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: '{evex} VCVTDQ2PD' + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: VPRORVD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPRORVD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPRORVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPRORVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPRORVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPRORVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMINPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VMINPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VMINPS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMINPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VMINPS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VMINPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADD231PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADD231PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMSUB213PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMSUB213PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSUBB' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VPSUBB' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPSUBB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPBROADCASTMW2D + operands: + - class: register + name: gpr + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPBROADCASTMW2D + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPBROADCASTMW2D + operands: + - class: register + name: gpr + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPSUBD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPSUBD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSUBD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VPSUBD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPSUBQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSUBQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VPSUBQ' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VPSUBW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VPSUBW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPSUBW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPSUBW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUBADD132PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUBADD132PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSADBW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSADBW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSADBW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTSS2USI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, '0'], [1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 3 +- name: VFMSUBADD132PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUBADD132PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUBADD132PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPBROADCASTMB2Q + operands: + - class: register + name: gpr + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPBROADCASTMB2Q + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPBROADCASTMB2Q + operands: + - class: register + name: gpr + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPXORQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPXORQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPXORQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPXORQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPXORQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPXORQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VEXTRACTI64X4 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTI64X4 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTF32X8 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTF32X8 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTI64X2 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTI64X2 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTI64X2 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTI64X2 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTF32X4 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTF32X4 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTF32X4 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTF32X4 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPSLLD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSLLD' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSLLD' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VEXTRACTI32X4 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTI32X4 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTI32X4 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTI32X4 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPXORD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPXORD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPXORD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPXORD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPXORD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPXORD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPERMT2PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTI32X8 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VEXTRACTI32X8 + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VRANGEPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRANGEPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRANGEPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRANGEPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRANGEPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VRANGEPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VREDUCEPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VREDUCEPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VREDUCEPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VREDUCEPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VREDUCEPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VREDUCEPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPAVGB' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPAVGB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPAVGB' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPAVGB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPAVGB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPAVGB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRANGEPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRANGEPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRANGEPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRANGEPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRANGEPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VRANGEPS + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VCVTSD2SI' + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 7 + port_pressure: [[1, '0'], [1, '015']] + throughput: 1.3333333333333333 + uops: 2 +- name: VFNMADD231PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMADD231PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMADD231PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTSS2USI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, '0'], [1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 3 +- name: VFMSUBADD231PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUBADD231PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMSUBADD231PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMSUBADD231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMADD231PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMADD231PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD231PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPD2UQQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPD2UQQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPD2UQQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPD2UQQ + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPD2UQQ + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VCVTPD2UQQ + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSUBSB' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSUBSB' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBSB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBSB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSUBSB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VFNMSUB231SS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231SS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPERMT2D + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2D + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2D + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2D + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2D + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2D + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VRSQRT14PD + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: ~ + port_pressure: [[2, '0'], [1, '05']] + throughput: 2.5 + uops: 3 +- name: VRSQRT14PD + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: ~ + port_pressure: [[2, '0'], [1, '05']] + throughput: 2.5 + uops: 3 +- name: VRSQRT14PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRT14PD + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRT14PD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRT14PD + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VFNMSUB231SD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMSUB231SD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VRSQRT14PS + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: ~ + port_pressure: [[2, '0'], [1, '05']] + throughput: 2.5 + uops: 3 +- name: VRSQRT14PS + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: ~ + port_pressure: [[2, '0'], [1, '05']] + throughput: 2.5 + uops: 3 +- name: VRSQRT14PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRT14PS + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRT14PS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRT14PS + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: ~ + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VCVTPS2UDQ + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VCVTPS2UDQ + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VCVTPS2UDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPS2UDQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPS2UDQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPS2UDQ + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPERMT2Q + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2Q + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2Q + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2Q + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2Q + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2Q + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPMINUW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMINUW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINUW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINUW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMINUW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPERMPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPERMPS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VUNPCKLPS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VUNPCKLPS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPMINUB' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINUB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMINUB' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINUB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINUB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMINUB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMINUD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMINUD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPMINUD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINUD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMINUD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMINUD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VUNPCKLPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VUNPCKLPD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VUNPCKLPD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMPD + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPERMPD' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPERMPD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSCALEFSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSCALEFSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADDSUB213PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADDSUB213PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETEXPSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VGETEXPSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VBLENDMPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VBLENDMPS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VBLENDMPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VBLENDMPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VBLENDMPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VBLENDMPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VFMADDSUB213PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADDSUB213PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADDSUB213PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSCALEFSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VSCALEFSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VBLENDMPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VBLENDMPD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VBLENDMPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VBLENDMPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VBLENDMPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VBLENDMPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VPUNPCKHBW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPUNPCKHBW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHBW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHBW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHBW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMT2PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCVTTPD2QQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPD2QQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPD2QQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPD2QQ + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTTPD2QQ + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VCVTTPD2QQ + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VCVTTPD2DQ + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VCVTTPD2DQ + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: '{evex} VCVTTPD2DQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: '{evex} VCVTTPD2DQ' + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTTPD2DQ + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VFMADD213PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADD213PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADD213PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPCMPGTD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPCMPGTD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPCMPGTD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPMADDWD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMADDWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMADDWD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMADDWD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMADDWD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPMADDWD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPCMPGTQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPCMPGTQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPCMPGTQ' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VFMADD213PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADD213PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADD213PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADD213PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPCMPGTW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPCMPGTW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSUBSW' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSUBSW' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBSW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSUBSW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSUBSW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPMAXUB' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXUB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPMAXUB' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXUB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPMAXUB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMAXUB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VFMADDSUB132PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADDSUB132PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADDSUB132PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADDSUB132PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFMADDSUB132PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFMADDSUB132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMADD132PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMADD132PD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPUNPCKHWD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPUNPCKHWD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHWD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHWD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHWD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPORD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPORD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPORD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPORD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPORD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPORD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VFNMADD132PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PS + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMADD132PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VFNMADD132PS' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VFNMADD132PS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPORQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPORQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VPORQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPORQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPORQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPORQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: '{evex} VCVTTSD2SI' + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 7 + port_pressure: [[1, '0'], [1, '015']] + throughput: 1.3333333333333333 + uops: 2 +- name: VPSLLVW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLVW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLVW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLVW + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLVW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLVW + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VCVTPD2PS + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VCVTPD2PS + operands: + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: '{evex} VCVTPD2PS' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTPD2PS + operands: + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: '{evex} VCVTPD2PS' + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTPD2PS + operands: + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VPSLLVD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLVD + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSLLVD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLVD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSLLVD' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLVD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VADDSD' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPS2PH + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: VCVTPS2PH + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: ymm + latency: 9 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: '{evex} VCVTPS2PH' + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTPS2PH + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: '{evex} VCVTPS2PH' + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: VCVTPS2PH + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: xmm + latency: 9 + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 2 +- name: '{evex} VPACKSSWB' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKSSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPACKSSWB' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKSSWB + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKSSWB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKSSWB + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: '{evex} VADDSS' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VADDSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLVQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLVQ + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: gpr + - class: register + name: zmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: '{evex} VPSLLVQ' + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLVQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: gpr + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: '{evex} VPSLLVQ' + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VPSLLVQ + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: gpr + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 1 +- name: VCVTPS2PD + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, '05'], [1, '5']] + throughput: 1.5 + uops: 2 +- name: '{evex} VCVTPS2PD' + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 +- name: '{evex} VCVTPS2PD' + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, '01']] + throughput: 0.5 + uops: 2 diff --git a/osaca/data/snb.yml b/osaca/data/snb.yml new file mode 100644 index 0000000..3b36118 --- /dev/null +++ b/osaca/data/snb.yml @@ -0,0 +1,10433 @@ +osaca_version: 0.3.1.dev1 +micro_architecture: Intel Sandy Bridge +arch_code: SNB +isa: x86 +ROB_size: 168 +retired_uOps_per_cycle: 4 +scheduler_size: 54 +hidden_loads: false +load_latency: {gpr: 4.0, xmm: 4.0, ymm: 4.0} +load_throughput: +- {base: gpr, index: gpr, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: gpr, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: gpr, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: gpr, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: ~, offset: imd, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: ~, offset: imd, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: ~, offset: ~, scale: 1, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +- {base: gpr, index: ~, offset: ~, scale: 8, port_pressure: [[1, '23'], [1, [2D, 3D]]]} +ports: ['0', '0DV', '1', '2', '2D', '3', '3D', '4', '5'] +port_model_scheme: | + ┌-----------------------------------------------------┐ + | 54 entry scheduler | + └-----------------------------------------------------┘ + 0 | 1 | 2 | 3 | 4 | 5 | + ▼ ▼ ▼ ▼ ▼ ▼ + ┌-------┐ ┌-------┐ ┌-----┐ ┌-----┐ ┌-----┐ ┌-------┐ + | ALU | | ALU | | LD | | LD | | ST | | ALU | + └-------┘ └-------┘ └-----┘ └-----┘ └-----┘ └-------┘ + ┌-------┐ ┌-------┐ ┌-----┐ ┌-----┐ ┌-------┐ + |AVX DIV| | Fast | | AGU | | AGU | | BRANCH| + └-------┘ | LEA | └-----┘ └-----┘ └-------┘ + ┌-------┐ └-------┘ ┌-------┐ + |AVX MUL| ┌-------┐┌-------┐ | Fast | + └-------┘ |AVX ADD||AVX FMA| | LEA | + ┌-------┐ └-------┘└-------┘ └-------┘ + | AVX |┌-------┐ ┌-------┐ ┌-------┐ + | Shift ||AVX FMA| |AVX MUL| | AVX | + └-------┘└-------┘ └-------┘ | SHUF | + └-------┘ +instruction_forms: +- name: mov + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: mov + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: mov + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: mov + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: mov + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: mov + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: mov + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movq + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: gpr + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: gpr + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movapd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movapd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movapd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movaps + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movaps + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movaps + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movdqa + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqa + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqa + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movdqu + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqu + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqu + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movq + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movsd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movsd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movsd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movss + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movss + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movss + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movupd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movupd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movupd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: movups + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movups + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movups + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: movups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovq + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovss + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovups + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: xmm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: xmm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovapd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovaps + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovaps + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqa + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovdqu + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovq + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovq + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovq + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovsd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovsd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovss + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovss + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovss + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovups + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovups + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovups + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.0 + port_pressure: [] + throughput: 0.0 + uops: 0 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + - class: register + name: ymm + latency: 4.0 + port_pressure: [[1, '23'], [1, [2D, 3D]]] + throughput: 0.5 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: ~ + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: ~ + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: vmovupd + operands: + - class: register + name: ymm + - class: memory + base: gpr + offset: imd + index: gpr + scale: 1 + latency: 0 + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 + +- name: SLDT + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '015'], [1, '1'], [2, '5']] + throughput: 2.3333333333333335 + uops: 5 +- name: POPFW + operands: [] + latency: ~ + port_pressure: [[3, '015'], [1, '1'], [1, '23'], [2, '5']] + throughput: 3.0 + uops: 10 +- name: CALL + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '4'], [1, '5']] + throughput: 1.0 + uops: 3 +- name: OUTSW + operands: [] + latency: ~ + port_pressure: [[10, '0'], [4, '01'], [2, '015'], [2, '05'], [11, '1'], [2, '15'], [2, '23'], [1, '4'], [24, '5']] + throughput: 26.666666666666668 + uops: 58 +- name: OUTSB + operands: [] + latency: ~ + port_pressure: [[10, '0'], [3, '01'], [4, '015'], [1, '05'], [12, '1'], [2, '23'], [1, '4'], [25, '5']] + throughput: 26.833333333333332 + uops: 58 +- name: OUTSD + operands: [] + latency: ~ + port_pressure: [[10, '0'], [4, '01'], [3, '015'], [1, '05'], [11, '1'], [1, '15'], [2, '23'], [1, '4'], [25, '5']] + throughput: 27.0 + uops: 58 +- name: JNE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNLE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: WRMSR + operands: [] + latency: ~ + port_pressure: [[19, '0'], [11, '05'], [18, '1'], [11, '15'], [1, '4'], [50, '5']] + throughput: 61.0 + uops: 110 +- name: REPE SCASW + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: REPE SCASD + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: REPE SCASB + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: REX64 REPE SCASB + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: JNS + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JL + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNP + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNZ + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNB + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNO + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JNL + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: CMC + operands: [] + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CMP + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CMP + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX CMP + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: LAHF + operands: [] + latency: 0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: CBW + operands: [] + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PUSHFW + operands: [] + latency: 9 + port_pressure: [[1, '05'], [1, '1'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 4 +- name: NOT + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX NOT + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: INC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX INC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CMPSW + operands: [] + latency: 4 + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: CMPSB + operands: [] + latency: 4 + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: CMPSD + operands: [] + latency: 4 + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: SETB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SETL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SETO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: BSR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SETP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: OUT + operands: + - class: register + name: gpr + - class: immediate + imd: int + latency: ~ + port_pressure: [[3, '015'], [1, '5']] + throughput: 2.0 + uops: 55 +- name: OUT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[3, '015']] + throughput: 1.0 + uops: 54 +- name: LODSB + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 3 +- name: LODSW + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 3 +- name: LODSD + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23']] + throughput: 0.5 + uops: 2 +- name: JNBE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: STD + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 3 +- name: STOSD + operands: [] + latency: 0 + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: XOR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX XOR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: SAR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SAR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: STC + operands: [] + latency: ~ + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: STI + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '1'], [3, '5']] + throughput: 3.6666666666666665 + uops: 6 +- name: STR + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '015'], [1, '1'], [2, '5']] + throughput: 2.3333333333333335 + uops: 5 +- name: STOSB + operands: [] + latency: 0 + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: REPE LODSW + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 10 +- name: REPNE LODSW + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 10 +- name: RDMSR + operands: [] + latency: ~ + port_pressure: [[2, '0'], [13, '01'], [15, '05'], [5, '1'], [6, '15'], [36, '5']] + throughput: 46.5 + uops: 77 +- name: REPE LODSB + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 10 +- name: REX64 REPE LODSB + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 10 +- name: REPNE LODSB + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 10 +- name: REX64 REPNE LODSB + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 10 +- name: REPE LODSD + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: REPNE LODSD + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: IDIV + operands: + - class: register + name: gpr + latency: 23 + port_pressure: [[2, '0'], [2, '015'], [2, '05'], [2, '1'], [2, '5'], [3, [0DV]]] + throughput: 3.6666666666666665 + uops: 10 +- name: REX IDIV + operands: + - class: register + name: gpr + latency: 22 + port_pressure: [[2, '0'], [3, '015'], [2, '1'], [2, '5'], [3, [0DV]]] + throughput: 3.0 + uops: 9 +- name: REPNE CMPSB + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: REX64 REPNE CMPSB + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: REPNE CMPSD + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: SETS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SHR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SHR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SHL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SHL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: BTS + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: BTS + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: BTR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: BTR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: LOOP + operands: + - class: identifier + latency: 3 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 8 +- name: BTC + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: BTC + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: WBINVD + operands: [] + latency: ~ + port_pressure: [[237594, '0'], [188428, '4'], [393278, '5']] + throughput: 393278.0 + uops: 819300 +- name: JBE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: MUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: REX MUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PUSH + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '1'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: PUSHW + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: PUSH + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: PUSHW + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '1'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: SETNO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETNO + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SETNL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETNL + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: CLI + operands: [] + latency: ~ + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: CLD + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '5']] + throughput: 1.3333333333333333 + uops: 3 +- name: SETNB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETNB + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SETNZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETNZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SETNS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETNS + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SETNP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETNP + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: LLDT + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '01'], [1, '015'], [3, '1'], [2, '23'], [1, '4'], [6, '5']] + throughput: 6.333333333333333 + uops: 14 +- name: RET + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [[5, '5']] + throughput: 5.0 + uops: 5 +- name: RET + operands: [] + latency: ~ + port_pressure: [[3, '5']] + throughput: 3.0 + uops: 3 +- name: SETNBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: REX SETNBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: REPE INSW + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [18, '5']] + throughput: 19.0 + uops: 43 +- name: REPNE INSW + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [18, '5']] + throughput: 19.0 + uops: 43 +- name: REPE INSB + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [1, '15'], [17, '5']] + throughput: 18.5 + uops: 43 +- name: REX64 REPE INSB + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [1, '15'], [17, '5']] + throughput: 18.5 + uops: 43 +- name: REPNE INSB + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [1, '15'], [17, '5']] + throughput: 18.5 + uops: 43 +- name: REX64 REPNE INSB + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [1, '15'], [17, '5']] + throughput: 18.5 + uops: 43 +- name: REPE INSD + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [1, '15'], [17, '5']] + throughput: 18.5 + uops: 43 +- name: REX64 REPE INSD + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [1, '15'], [17, '5']] + throughput: 18.5 + uops: 43 +- name: REPNE INSD + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [1, '15'], [17, '5']] + throughput: 18.5 + uops: 43 +- name: REX64 REPNE INSD + operands: [] + latency: ~ + port_pressure: [[8, '0'], [4, '01'], [3, '015'], [10, '1'], [1, '15'], [17, '5']] + throughput: 18.5 + uops: 43 +- name: REPE STOSD + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 53 +- name: REPNE STOSD + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 53 +- name: VERR + operands: + - class: register + name: gpr + latency: 62 + port_pressure: [[4, '0'], [1, '1'], [8, '5']] + throughput: 8.0 + uops: 13 +- name: REPE STOSB + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 19 +- name: REX64 REPE STOSB + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 19 +- name: REPNE STOSB + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 19 +- name: REX64 REPNE STOSB + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 19 +- name: REPE STOSW + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 53 +- name: REPNE STOSW + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 53 +- name: CWD + operands: [] + latency: 2 + port_pressure: [[1, '015'], [1, '05']] + throughput: 0.8333333333333333 + uops: 2 +- name: TEST + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX TEST + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: TEST + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX TEST + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: JZ + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: SCASW + operands: [] + latency: 1 + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 3 +- name: JP + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JS + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JO + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: SCASD + operands: [] + latency: 1 + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 3 +- name: SCASB + operands: [] + latency: 1 + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 3 +- name: JB + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: RDPMC + operands: [] + latency: ~ + port_pressure: [[1, '0'], [14, '01'], [8, '05'], [2, '1'], [1, '15'], [9, '5']] + throughput: 13.5 + uops: 35 +- name: ENTERW + operands: + - class: immediate + imd: int + - class: immediate + imd: int + latency: ~ + port_pressure: [[2, '01'], [4, '015'], [1, '05'], [2, '23'], [1, '4'], [2, '5']] + throughput: 3.833333333333333 + uops: 12 +- name: ENTER + operands: + - class: immediate + imd: int + - class: immediate + imd: int + latency: ~ + port_pressure: [[2, '01'], [4, '015'], [1, '05'], [2, '23'], [1, '4'], [2, '5']] + throughput: 3.833333333333333 + uops: 12 +- name: REPNE SCASB + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: REX64 REPNE SCASB + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: REPNE SCASD + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: REPNE SCASW + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: LEAVEW + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 4 +- name: LEAVE + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 3 +- name: REPE OUTSW + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [1, '05'], [11, '1'], [16, '5']] + throughput: 17.5 + uops: 42 +- name: REPNE OUTSW + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [1, '05'], [11, '1'], [16, '5']] + throughput: 17.5 + uops: 42 +- name: REPE OUTSB + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [11, '1'], [17, '5']] + throughput: 18.0 + uops: 42 +- name: REX64 REPE OUTSB + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [11, '1'], [17, '5']] + throughput: 18.0 + uops: 42 +- name: REPNE OUTSB + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [11, '1'], [17, '5']] + throughput: 18.0 + uops: 42 +- name: REX64 REPNE OUTSB + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [11, '1'], [17, '5']] + throughput: 18.0 + uops: 42 +- name: REPE OUTSD + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [11, '1'], [17, '5']] + throughput: 18.0 + uops: 42 +- name: REX64 REPE OUTSD + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [11, '1'], [17, '5']] + throughput: 18.0 + uops: 42 +- name: REPNE OUTSD + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [11, '1'], [17, '5']] + throughput: 18.0 + uops: 42 +- name: REX64 REPNE OUTSD + operands: [] + latency: ~ + port_pressure: [[7, '0'], [4, '01'], [3, '015'], [11, '1'], [17, '5']] + throughput: 18.0 + uops: 42 +- name: XLAT + operands: [] + latency: ~ + port_pressure: [[2, '015'], [1, '23']] + throughput: 0.6666666666666666 + uops: 3 +- name: SMSW + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '01'], [1, '015'], [2, '1'], [3, '5']] + throughput: 3.3333333333333335 + uops: 7 +- name: AND + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX AND + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: JLE + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: CPUID + operands: [] + latency: ~ + port_pressure: [[10, '0'], [38, '5']] + throughput: 38.0 + uops: 48 +- name: RDTSC + operands: [] + latency: ~ + port_pressure: [[6, '01'], [4, '015'], [1, '05'], [3, '1'], [1, '15'], [6, '5']] + throughput: 8.333333333333332 + uops: 21 +- name: CDQ + operands: [] + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: INSB + operands: [] + latency: ~ + port_pressure: [[11, '0'], [4, '01'], [3, '015'], [1, '05'], [10, '1'], [1, '15'], [3, '23'], [1, '4'], [25, '5']] + throughput: 27.0 + uops: 60 +- name: INSD + operands: [] + latency: ~ + port_pressure: [[11, '0'], [4, '01'], [3, '015'], [1, '05'], [10, '1'], [1, '15'], [3, '23'], [1, '4'], [25, '5']] + throughput: 27.0 + uops: 60 +- name: IMUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: REX IMUL + operands: + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: IMUL + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: RCR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '015'], [2, '05']] + throughput: 1.3333333333333333 + uops: 3 +- name: REX RCR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '015'], [2, '05']] + throughput: 1.3333333333333333 + uops: 3 +- name: RCL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '015'], [2, '05']] + throughput: 1.3333333333333333 + uops: 3 +- name: REX RCL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '015'], [2, '05']] + throughput: 1.3333333333333333 + uops: 3 +- name: INSW + operands: [] + latency: ~ + port_pressure: [[11, '0'], [4, '01'], [3, '015'], [1, '05'], [10, '1'], [1, '15'], [3, '23'], [1, '4'], [25, '5']] + throughput: 27.0 + uops: 60 +- name: STOSW + operands: [] + latency: 0 + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: IN + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: ~ + port_pressure: [[14, '0'], [2, '01'], [4, '015'], [11, '1'], [1, '15'], [1, '23'], [28, '5']] + throughput: 29.833333333333332 + uops: 61 +- name: IN + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[14, '0'], [6, '015'], [12, '1'], [1, '23'], [27, '5']] + throughput: 29.0 + uops: 60 +- name: BT + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: BT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: POP + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '23']] + throughput: 0.5 + uops: 1 +- name: JRCXZ + operands: + - class: identifier + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 2 +- name: SAHF + operands: [] + latency: 0 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: LMSW + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [[3, '0'], [4, '01'], [1, '015'], [1, '1'], [1, '23'], [1, '4'], [10, '5']] + throughput: 10.333333333333334 + uops: 21 +- name: REPE CMPSD + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: OR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX OR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REPE CMPSB + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: REX64 REPE CMPSB + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: REPE CMPSW + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: CLTS + operands: [] + latency: ~ + port_pressure: [[1, '05'], [5, '5']] + throughput: 5.5 + uops: 7 +- name: REPNE CMPSW + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: ROL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: REX ROL + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: VERW + operands: + - class: register + name: gpr + latency: 62 + port_pressure: [[4, '0'], [1, '1'], [8, '5']] + throughput: 8.0 + uops: 13 +- name: JMP + operands: + - class: register + name: gpr + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: JMP + operands: + - class: identifier + latency: 0 + port_pressure: [] + throughput: 0.0 + uops: 1 +- name: ROR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: REX ROR + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: SETLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: SUB + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX SUB + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: NEG + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX NEG + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: SETNLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETNLE + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: ADD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX ADD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CWDE + operands: [] + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: BSF + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SETZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REX SETZ + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: DEC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REX DEC + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: SETBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: REX SETBE + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: BSWAP + operands: + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '05'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: UNPCKHPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: DIVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[1, '0'], [3, [0DV]]] + throughput: 3.0 + uops: 1 +- name: ADDSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTPI2PS + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CMPSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ANDNPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: CVTTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: ORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: DIVSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[1, '0'], [3, [0DV]]] + throughput: 3.0 + uops: 1 +- name: RCPSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: SQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: SUBSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CMPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: XORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: SUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SHUFPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MINSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTSI2SS + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: SFENCE + operands: [] + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 2 +- name: RSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: UNPCKLPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MULSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: SQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: CVTTPS2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 2 +- name: RSQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: MINPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTPS2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 2 +- name: MULPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: CVTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: ANDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MAXPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: COMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: RCPPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: MAXSS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: UCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: UNPCKHPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PUNPCKHDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: CVTTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: DIVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 22 + port_pressure: [[1, '0'], [15, [0DV]]] + throughput: 15.0 + uops: 1 +- name: PCMPGTW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTPI2PD + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PACKUSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: ANDNPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSLLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: UNPCKLPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PSADBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PADDUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PACKSSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMULLW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: DIVSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 22 + port_pressure: [[1, '0'], [15, [0DV]]] + throughput: 15.0 + uops: 1 +- name: PCMPEQW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPEQB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPEQD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: ORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PXOR + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CMPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PSUBB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMAXSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSRLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CMPSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PMULHUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: MINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: CVTTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: ADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: POR + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CVTSD2SS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PSLLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: SQRTSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 21 + port_pressure: [[1, '0'], [21, [0DV]]] + throughput: 21.0 + uops: 1 +- name: PSLLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: CVTSI2SD + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PSLLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: MULSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PANDN + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: SHUFPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: SUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: SQRTPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 21 + port_pressure: [[1, '0'], [21, [0DV]]] + throughput: 21.0 + uops: 1 +- name: ANDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMULHW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMINSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PSHUFD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTSS2SD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 2 +- name: XORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: MAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: MINPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ADDSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PSRLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: SUBSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PADDSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: CVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: MULPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMULUDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMULUDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMADDWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PEXTRW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: PAND + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: CVTDQ2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PMAXUB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHWD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CVTPD2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: CVTPD2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: MFENCE + operands: [] + latency: ~ + port_pressure: [[1, '23'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: PSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: MAXPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PMINUB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PAVGW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PAVGB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSRAW + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: COMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: PSRAD + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PACKSSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: UCOMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: CVTTPD2PI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: FCHS + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FUCOM + operands: [] + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: FCOMI + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: FLDL2T + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FLDL2E + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FCOMIP + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: FADDP + operands: [] + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: FCOMPP + operands: [] + latency: ~ + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: FXAM + operands: [] + latency: ~ + port_pressure: [[2, '1']] + throughput: 2.0 + uops: ~ +- name: FFREE + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FNINIT + operands: [] + latency: ~ + port_pressure: [[3, '015'], [1, '5']] + throughput: 2.0 + uops: ~ +- name: FNOP + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FLDPI + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FNSTSW + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '015']] + throughput: 1.3333333333333333 + uops: ~ +- name: FWAIT + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FINCSTP + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FTST + operands: [] + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: FABS + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FLDLN2 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FDECSTP + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FLDLG2 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: ~ +- name: FLDZ + operands: [] + latency: ~ + port_pressure: [[1, '5']] + throughput: 1.0 + uops: ~ +- name: FUCOMPP + operands: [] + latency: ~ + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: FLD1 + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: FUCOMIP + operands: [] + latency: ~ + port_pressure: [[1, '0'], [1, '1'], [1, '5']] + throughput: 1.0 + uops: ~ +- name: PUNPCKHDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPGTD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PACKUSWB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSADBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PADDUSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDUSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PACKSSDW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMULLW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PCMPEQW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPEQB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PCMPEQD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLWD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PXOR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PSUBB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBUSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMAXSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PADDB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMULHUW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: POR + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PSLLD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLW + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLQ + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSLLQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSUBUSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKLDQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PANDN + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PMULHW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMINSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSHUFW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSRLQ + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLQ + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLW + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRLD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PADDSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: EMMS + operands: [] + latency: ~ + port_pressure: [[1, '0'], [18, '5']] + throughput: 18.0 + uops: 31 +- name: PUNPCKHBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMADDWD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PEXTRW + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: PAND + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: PMAXUB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PUNPCKHWD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMINUB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PAVGW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSUBSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PAVGB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSRAW + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAD + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PSRAD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PACKSSWB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PUNPCKLBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: REPE SCASQ + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: CMPSQ + operands: [] + latency: 4 + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 5 +- name: LODSQ + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23']] + throughput: 0.5 + uops: 2 +- name: CDQE + operands: [] + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: REPE LODSQ + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: REPNE LODSQ + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23']] + throughput: 0.5 + uops: 10 +- name: REPNE CMPSQ + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: PUSHFQ + operands: [] + latency: 9 + port_pressure: [[1, '05'], [1, '1'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 4 +- name: REPE STOSQ + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 53 +- name: REPNE STOSQ + operands: [] + latency: ~ + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 53 +- name: SCASQ + operands: [] + latency: 1 + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 3 +- name: REPNE SCASQ + operands: [] + latency: ~ + port_pressure: [[2, '015']] + throughput: 0.6666666666666666 + uops: 12 +- name: POPFQ + operands: [] + latency: ~ + port_pressure: [[3, '015'], [1, '1'], [1, '23'], [2, '5']] + throughput: 3.0 + uops: 10 +- name: STOSQ + operands: [] + latency: 0 + port_pressure: [[1, '015'], [1, '23'], [1, '4']] + throughput: 1.0 + uops: 3 +- name: CQO + operands: [] + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: REPE CMPSQ + operands: [] + latency: ~ + port_pressure: [[3, '015'], [2, '23']] + throughput: 1.0 + uops: 12 +- name: POPCNT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ROUNDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ROUNDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PBLENDW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: MPSADBW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '0'], [2, '15']] + throughput: 1.0 + uops: 3 +- name: PHMINPOSUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: INSERTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: PMULLD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PCMPEQQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PACKUSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: EXTRACTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMAXSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: BLENDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PTEST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: PMULDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMINSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: CRC32 + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: REX CRC32 + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: DPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 9 + port_pressure: [[1, '0'], [1, '1'], [1, '5']] + throughput: 1.0 + uops: 3 +- name: DPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 12 + port_pressure: [[1, '0'], [2, '1'], [1, '5']] + throughput: 2.0 + uops: 4 +- name: PEXTRD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: PMAXUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMAXUD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: BLENDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: PEXTRB + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: PMINUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PMINUD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: BLENDVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: BLENDVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '05']] + throughput: 1.0 + uops: 2 +- name: ROUNDSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ROUNDSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PEXTRQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: PBLENDVB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, '15'], [1, '23']] + throughput: 1.0 + uops: 2 +- name: PHSUBD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PHSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PMULHRSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMULHRSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PHSUBW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PHSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PSIGNW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGNW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGND + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGND + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGNB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSIGNB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PHADDSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PHADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PMADDUBSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PMADDUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: PHSUBSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PHSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PABSW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PHADDD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PHADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PALIGNR + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PALIGNR + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSHUFB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PSHUFB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSD + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSB + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PABSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: PHADDW + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: PHADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: ADDSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: ADDSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: HSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: HSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: HADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: HADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: TZCNT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: ~ + port_pressure: [[1, '1']] + throughput: 1.0 + uops: ~ +- name: RDTSCP + operands: [] + latency: ~ + port_pressure: [[5, '0'], [1, '01'], [7, '1'], [10, '5']] + throughput: 10.0 + uops: 23 +- name: AESKEYGENASSIST + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[2, '0'], [1, '015'], [1, '15'], [7, '5']] + throughput: 7.833333333333333 + uops: 11 +- name: AESIMC + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: LZCNT + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: PCLMULQDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[2, '0'], [4, '015'], [3, '05'], [4, '1'], [2, '15'], [3, '5']] + throughput: 6.833333333333333 + uops: 18 +- name: PAUSE + operands: [] + latency: ~ + port_pressure: [[3, '015'], [1, '5']] + throughput: 2.0 + uops: 7 +- name: VPMULHUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPMULUDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCPSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMULHRSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPERM2F128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VHADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VHADDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VPUNPCKLBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPERMILPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPCMPEQW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPAVGW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPEQB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPAVGB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VMULSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VANDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VANDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMAXSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VANDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VANDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMULSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VMULPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VMULPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSHUFHW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VMAXSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMAXSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPTEST + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPTEST + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPACKSSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXUB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VADDSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPXOR + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VSQRTSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 21 + port_pressure: [[1, '0'], [21, [0DV]]] + throughput: 21.0 + uops: 1 +- name: VEXTRACTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: VUNPCKHPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VCOMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VZEROALL + operands: [] + latency: ~ + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 20 +- name: VCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VPSRAD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRTSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSHUFD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSRAW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSHUFB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VDIVPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 22 + port_pressure: [[1, '0'], [21, [0DV]]] + throughput: 21.0 + uops: 1 +- name: VDIVPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 45 + port_pressure: [[2, '0'], [1, '05'], [42, [0DV]]] + throughput: 42.0 + uops: 3 +- name: VDIVPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: VDIVPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 29 + port_pressure: [[2, '0'], [1, '05'], [28, [0DV]]] + throughput: 28.0 + uops: 3 +- name: VCMPSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSHUFLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSLLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VCMPSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSLLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSLLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPAND + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VPHADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: VPANDN + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VSHUFPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSUBSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: VSQRTPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 29 + port_pressure: [[2, '0'], [1, '05'], [28, [0DV]]] + throughput: 28.0 + uops: 3 +- name: VCVTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTPS2DQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPHADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: VSQRTPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 21 + port_pressure: [[1, '0'], [21, [0DV]]] + throughput: 21.0 + uops: 1 +- name: VSQRTPD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 43 + port_pressure: [[2, '0'], [1, '05'], [42, [0DV]]] + throughput: 42.0 + uops: 3 +- name: VSUBSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSHUFPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VSHUFPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMULDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VDPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 9 + port_pressure: [[1, '0'], [1, '1'], [1, '5']] + throughput: 1.0 + uops: 3 +- name: VDPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 12 + port_pressure: [[1, '0'], [2, '1'], [1, '5']] + throughput: 2.0 + uops: 4 +- name: VDPPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 12 + port_pressure: [[1, '0'], [2, '1'], [1, '5']] + throughput: 2.0 + uops: 4 +- name: VPUNPCKHDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VCVTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTPD2DQ + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VMULPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VMULPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VINSERTPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPALIGNR + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VMAXPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMAXPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPACKUSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VMAXPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMAXPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSIGNW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSIGNB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VUNPCKHPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKHPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKLWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSIGND + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMULHW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VXORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VXORPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VROUNDSD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VROUNDSS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPMADDUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VXORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VXORPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VINSERTF128 + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VHSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VHSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VHSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VHSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VHADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VHADDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1'], [2, '5']] + throughput: 2.0 + uops: 3 +- name: VCVTTPS2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTTPS2DQ + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VTESTPD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VTESTPD + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VDIVSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[1, '0'], [14, [0DV]]] + throughput: 14.0 + uops: 1 +- name: VDIVSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 22 + port_pressure: [[1, '0'], [21, [0DV]]] + throughput: 21.0 + uops: 1 +- name: VTESTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VTESTPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCMPPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCMPPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSUBPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSUBPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTSS2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VMINSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPABSW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VSUBPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VSUBPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPHADDSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: VMINSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSUBUSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VMPSADBW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '0'], [2, '15']] + throughput: 1.0 + uops: 3 +- name: VPSUBUSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCMPGTB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VANDNPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VANDNPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPADDB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VANDNPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPADDD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPABSB + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VBLENDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VBLENDPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VBLENDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VBLENDPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '05']] + throughput: 0.5 + uops: 1 +- name: VRSQRTPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRSQRTPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 7 + port_pressure: [[2, '0'], [1, '05']] + throughput: 2.5 + uops: 3 +- name: VPEXTRB + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: VPEXTRD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: VPHSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: VPEXTRQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: VPEXTRW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 2 + port_pressure: [[1, '0'], [1, '15']] + throughput: 1.0 + uops: 2 +- name: VPHSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: VADDPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPBLENDW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPOR + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '015']] + throughput: 0.3333333333333333 + uops: 1 +- name: VADDPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VADDPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPMULLD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VUCOMISS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VPCMPISTRI + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 11 + port_pressure: [[3, '0']] + throughput: 3.0 + uops: 3 +- name: VPMULLW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VUCOMISD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VEXTRACTF128 + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPACKUSDW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXUD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMAXUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSRLW + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPSRLQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLQDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSRLD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPERMILPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VMINPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMINPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTDQ2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTDQ2PS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKLDQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VCVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTDQ2PD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VMINPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VMINPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSUBB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSADBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VROUNDPD + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VROUNDPD + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VROUNDPS + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VROUNDPS + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPSUBSB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPCLMULQDQ + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[2, '0'], [4, '015'], [3, '05'], [4, '1'], [2, '15'], [3, '5']] + throughput: 6.833333333333333 + uops: 18 +- name: VRCPPS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VRCPPS + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 7 + port_pressure: [[2, '0'], [1, '05']] + throughput: 2.5 + uops: 3 +- name: VCVTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VORPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VORPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VORPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VORPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VUNPCKLPS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPS + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPMINUB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMINUD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VUNPCKLPD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VUNPCKLPD + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 1 + port_pressure: [[1, '5']] + throughput: 1.0 + uops: 1 +- name: VPUNPCKHBW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VCVTTPD2DQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTTPD2DQ + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VPCMPGTD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPMADDWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTQ + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPCMPGTW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPHMINPOSUW + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '0']] + throughput: 1.0 + uops: 1 +- name: VPABSD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPUNPCKHWD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VPHSUBSW + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[3, '15']] + throughput: 1.5 + uops: 3 +- name: VCVTTSD2SI + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 4 + port_pressure: [[1, '0'], [1, '1']] + throughput: 1.0 + uops: 2 +- name: VCVTPD2PS + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTPD2PS + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '1'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VADDSD + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VPACKSSWB + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 1 + port_pressure: [[1, '15']] + throughput: 0.5 + uops: 1 +- name: VADDSS + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '1']] + throughput: 1.0 + uops: 1 +- name: VCVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VCVTPS2PD + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '0'], [1, '5']] + throughput: 1.0 + uops: 2 +- name: VAESIMC + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[2, '5']] + throughput: 2.0 + uops: 2 +- name: VAESKEYGENASSIST + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[2, '0'], [1, '015'], [1, '1'], [7, '5']] + throughput: 7.333333333333333 + uops: 11 diff --git a/osaca/db_interface.py b/osaca/db_interface.py index 12e8327..4915e7f 100755 --- a/osaca/db_interface.py +++ b/osaca/db_interface.py @@ -11,6 +11,15 @@ from osaca.semantics import MachineModel def sanity_check(arch: str, verbose=False): + """ + Checks the database for missing TP/LT values, instructions might missing int the ISA DB and + duplicate instructions. + + :param arch: micro-arch key to define DB to check + :type arch: str + :param verbose: verbose output flag, defaults to `False` + :type verbose: bool, optional + """ # load arch machine model arch_mm = MachineModel(arch=arch) data = arch_mm['instruction_forms'] @@ -24,7 +33,6 @@ def sanity_check(arch: str, verbose=False): missing_throughput, missing_latency, missing_port_pressure, - wrong_port, suspicious_instructions, duplicate_instr_arch, ) = _check_sanity_arch_db(arch_mm, isa_mm) @@ -36,7 +44,6 @@ def sanity_check(arch: str, verbose=False): missing_throughput, missing_latency, missing_port_pressure, - wrong_port, suspicious_instructions, duplicate_instr_arch, duplicate_instr_isa, @@ -46,6 +53,16 @@ def sanity_check(arch: str, verbose=False): def import_benchmark_output(arch, bench_type, filepath): + """ + Import benchmark results from micro-benchmarks. + + :param arch: target architecture key + :type arch: str + :param bench_type: key for defining type of benchmark output + :type bench_type: str + :param filepath: filepath to the output file + :type filepath: str + """ supported_bench_outputs = ['ibench', 'asmbench'] assert os.path.exists(filepath) if bench_type not in supported_bench_outputs: @@ -120,6 +137,7 @@ def _get_asmbench_output(input_data, isa): def _get_ibench_output(input_data, isa): + """Parse the standard output of ibench and add instructions to DB.""" db_entries = {} for line in input_data: if 'Using frequency' in line or len(line) == 0: @@ -242,7 +260,6 @@ def _check_sanity_arch_db(arch_mm, isa_mm): missing_throughput = [] missing_latency = [] missing_port_pressure = [] - wrong_port = [] suspicious_instructions = [] duplicate_instr_arch = [] @@ -254,12 +271,9 @@ def _check_sanity_arch_db(arch_mm, isa_mm): missing_latency.append(instr_form) if instr_form['port_pressure'] is None: missing_port_pressure.append(instr_form) - else: - if _check_for_wrong_port(arch_mm['ports'], instr_form): - wrong_port.append(instr_form) # check entry against ISA DB for prefix in suspicious_prefixes: - if instr_form['name'].startswith(prefix): + if instr_form['name'].lower().startswith(prefix): # check if instruction in ISA DB if isa_mm.get_instruction(instr_form['name'], instr_form['operands']) is None: # if not, mark them as suspicious and print it on the screen @@ -278,20 +292,11 @@ def _check_sanity_arch_db(arch_mm, isa_mm): missing_throughput, missing_latency, missing_port_pressure, - wrong_port, suspicious_instructions, duplicate_instr_arch, ) -def _check_for_wrong_port(port_list, instr_form): - for cycles, ports in instr_form['port_pressure']: - for p in ports: - if p not in port_list: - return False - return True - - def _check_sanity_isa_db(arch_mm, isa_mm): # returned lists duplicate_instr_isa = [] @@ -316,7 +321,7 @@ def _check_sanity_isa_db(arch_mm, isa_mm): def _print_sanity_report( - total, m_tp, m_l, m_pp, wrong_pp, suspic_instr, dup_arch, dup_isa, only_isa, verbose=False + total, m_tp, m_l, m_pp, suspic_instr, dup_arch, dup_isa, only_isa, verbose=False ): # non-verbose summary print('SUMMARY\n----------------------') @@ -335,11 +340,6 @@ def _print_sanity_report( round(100 * len(m_pp) / total), len(m_pp), total ) ) - print( - '{}% ({}/{}) of instruction forms have an invalid port identifier.'.format( - round(100 * len(wrong_pp) / total), len(wrong_pp), total - ) - ) print( '{}% ({}/{}) of instruction forms might miss an ISA DB entry.'.format( round(100 * len(suspic_instr) / total), len(suspic_instr), total @@ -355,12 +355,12 @@ def _print_sanity_report( # verbose version if verbose: _print_sanity_report_verbose( - total, m_tp, m_l, m_pp, wrong_pp, suspic_instr, dup_arch, dup_isa, only_isa + total, m_tp, m_l, m_pp, suspic_instr, dup_arch, dup_isa, only_isa ) def _print_sanity_report_verbose( - total, m_tp, m_l, m_pp, wrong_pp, suspic_instr, dup_arch, dup_isa, only_isa + total, m_tp, m_l, m_pp, suspic_instr, dup_arch, dup_isa, only_isa ): BRIGHT_CYAN = '\033[1;36;1m' BRIGHT_BLUE = '\033[1;34;1m' @@ -382,14 +382,6 @@ def _print_sanity_report_verbose( ) for instr_form in m_pp: print('{}{}{}'.format(BRIGHT_MAGENTA, _get_full_instruction_name(instr_form), WHITE)) - print( - 'Instruction forms with invalid port identifiers in port pressure:\n' - if len(wrong_pp) != 0 - else '', - end='', - ) - for instr_form in wrong_pp: - print('{}{}{}'.format(BRIGHT_MAGENTA, _get_full_instruction_name(instr_form), WHITE)) print( 'Instruction forms which might miss an ISA DB entry:\n' if len(suspic_instr) != 0 else '', end='', diff --git a/osaca/frontend.py b/osaca/frontend.py index ac421df..72fe3bc 100755 --- a/osaca/frontend.py +++ b/osaca/frontend.py @@ -1,5 +1,7 @@ #!/usr/bin/env python3 - +""" +Frontend interface for OSACA. Does everything necessary for printing analysis to the terminal. +""" import re from datetime import datetime as dt @@ -8,6 +10,16 @@ from osaca.semantics import INSTR_FLAGS, ArchSemantics, KernelDG, MachineModel class Frontend(object): def __init__(self, filename='', arch=None, path_to_yaml=None): + """ + Constructor method. + + :param filename: path to the analyzed kernel file for documentation, defaults to '' + :type filename: str, optional + :param arch: micro-arch code for getting the machine model, defaults to None + :type arch: str, optional + :param path_to_yaml: path to the YAML file for getting the machine model, defaults to None + :type path_to_yaml: str, optional + """ self._filename = filename if not arch and not path_to_yaml: raise ValueError('Either arch or path_to_yaml required.') @@ -22,9 +34,25 @@ class Frontend(object): self._arch = self._machine_model.get_arch() def _is_comment(self, instruction_form): + """ + Checks if instruction form is a comment-only line. + + :param instruction_form: instruction form as dict + :returns: `True` if comment line, `False` otherwise + """ return instruction_form['comment'] is not None and instruction_form['instruction'] is None def print_throughput_analysis(self, kernel, show_lineno=False, show_cmnts=True): + """ + Print throughput analysis only. + + :param kernel: Kernel to print throughput analysis for. + :type kernel: list + :param show_lineno: flag for showing the line number of instructions, defaults to `False` + :type show_lineno: bool, optional + :param show_cmnts: flag for showing comment-only lines in kernel, defaults to `True` + :type show_cmnts: bool, optional + """ lineno_filler = ' ' if show_lineno else '' port_len = self._get_max_port_len(kernel) separator = '-' * sum([x + 3 for x in port_len]) + '-' @@ -58,6 +86,14 @@ class Frontend(object): print(lineno_filler + self._get_port_pressure(tp_sum, port_len, separator=' ')) def print_latency_analysis(self, cp_kernel, separator='|'): + """ + Print a list-based CP analysis to the terminal. + + :param cp_kernel: loop kernel containing the CP information for each instruction form + :type cp_kernel: list + :separator: separator symbol for the columns, defaults to '|' + :type separator: str, optional + """ print('\n\nLatency Analysis Report\n' + '-----------------------') for instruction_form in cp_kernel: print( @@ -80,6 +116,14 @@ class Frontend(object): ) def print_loopcarried_dependencies(self, dep_dict, separator='|'): + """ + Print a list-based LCD analysis to the terminal. + + :param dep_dict: dictionary with first instruction in LCD as key and the deps as value + :type dep_dict: dict + :separator: separator symbol for the columns, defaults to '|' + :type separator: str, optional + """ print( '\n\nLoop-Carried Dependencies Analysis Report\n' + '-----------------------------------------' @@ -101,6 +145,17 @@ class Frontend(object): ) def print_full_analysis(self, kernel, kernel_dg: KernelDG, verbose=False): + """ + Prints the full analysis report including header, the symbol map, the combined TP/CP/LCD + view and the list based LCD view. + + :param kernel: kernel to print + :type kernel: list + :param kernel_dg: directed graph containing CP and LCD + :type kernel_dg: :class:`~osaca.semantics.KernelDG` + :param verbose: verbose output flag, defaults to `False` + :type verbose: bool, optional + """ self._print_header_report() self._print_symbol_map() self.print_combined_view( @@ -109,9 +164,20 @@ class Frontend(object): self.print_loopcarried_dependencies(kernel_dg.get_loopcarried_dependencies()) def print_combined_view(self, kernel, cp_kernel: KernelDG, dep_dict, show_cmnts=True): - self._print_header_report() - self._print_symbol_map() - print('\n\nCombined Analysis Report\n' + '-----------------------') + """ + Prints the combined view of the kernel including the port pressure (TP), a CP column and a + LCD column. + + :param kernel: kernel to print + :type kernel: list + :param kernel_dg: directed graph containing CP and LCD + :type kernel_dg: :class:`~osaca.semantics.KernelDG` + :param dep_dict: dictionary with first instruction in LCD as key and the deps as value + :type dep_dict: dict + :param show_cmnts: flag for showing comment-only lines in kernel, defaults to `True` + :type show_cmnts: bool, optional + """ + print('\n\nCombined Analysis Report\n' + '------------------------') lineno_filler = ' ' port_len = self._get_max_port_len(kernel) # Separator for ports @@ -180,6 +246,7 @@ class Frontend(object): #################### def _get_separator_list(self, separator, separator_2=' '): + """Creates column view for seperators in the TP/combined view.""" separator_list = [] for i in range(len(self._machine_model.get_ports()) - 1): match_1 = re.search(r'\d+', self._machine_model.get_ports()[i]) @@ -192,6 +259,7 @@ class Frontend(object): return separator_list def _get_flag_symbols(self, flag_obj): + """Returns flags for a flag object of an instruction""" string_result = '' string_result += '*' if INSTR_FLAGS.NOT_BOUND in flag_obj else '' string_result += 'X' if INSTR_FLAGS.TP_UNKWN in flag_obj else '' @@ -201,6 +269,7 @@ class Frontend(object): return string_result def _get_port_pressure(self, ports, port_len, used_ports=[], separator='|'): + """Returns line of port pressure for an instruction.""" if not isinstance(separator, list): separator = [separator for x in ports] string_result = '{} '.format(separator[-1]) @@ -214,20 +283,23 @@ class Frontend(object): return string_result[:-1] def _get_node_by_lineno(self, lineno, kernel): + """Returns instruction form from kernel by its line number.""" nodes = [instr for instr in kernel if instr['line_number'] == lineno] return nodes[0] if len(nodes) > 0 else None def _get_lcd_cp_ports(self, line_number, cp_dg, dependency, separator='|'): + """Returns the CP and LCD line for one instruction.""" lat_cp = lat_lcd = '' if cp_dg: - lat_cp = self._get_node_by_lineno(line_number, cp_dg)['latency_cp'] + lat_cp = float(self._get_node_by_lineno(line_number, cp_dg)['latency_cp']) if dependency: - lat_lcd = self._get_node_by_lineno(line_number, dependency['dependencies'])[ - 'latency_lcd' - ] + lat_lcd = float( + self._get_node_by_lineno(line_number, dependency['dependencies'])['latency_lcd'] + ) return '{} {:>4} {} {:>4} {}'.format(separator, lat_cp, separator, lat_lcd, separator) def _get_max_port_len(self, kernel): + """Returns the maximal length needed to print all throughputs of the kernel.""" port_len = [4 for x in self._machine_model.get_ports()] for instruction_form in kernel: for i, port in enumerate(instruction_form['port_pressure']): @@ -236,6 +308,7 @@ class Frontend(object): return port_len def _get_port_number_line(self, port_len, separator='|'): + """Returns column view of port identificators of machine_model.""" string_result = separator separator_list = self._get_separator_list(separator, '-') for i, length in enumerate(port_len): @@ -244,6 +317,7 @@ class Frontend(object): return string_result def _print_header_report(self): + """Prints header information""" version = 'v0.3' adjust = 20 header = '' @@ -256,6 +330,7 @@ class Frontend(object): print(header) def _print_symbol_map(self): + """Prints instruction flag map.""" symbol_dict = { INSTR_FLAGS.NOT_BOUND: 'Instruction micro-ops not bound to a port', INSTR_FLAGS.TP_UNKWN: 'No throughput/latency information for this instruction in ' diff --git a/osaca/osaca.py b/osaca/osaca.py index 5375f2b..707424d 100755 --- a/osaca/osaca.py +++ b/osaca/osaca.py @@ -1,5 +1,5 @@ #!/usr/bin/env python3 - +"""CLI for OSACA""" import argparse import io import os @@ -22,6 +22,7 @@ DATA_DIR = os.path.join(LOCAL_OSACA_DIR, 'data/') # Stolen from pip def __read(*names, **kwargs): + """Reads in file""" with io.open( os.path.join(os.path.dirname(__file__), *names), encoding=kwargs.get("encoding", "utf8") ) as fp: @@ -30,6 +31,7 @@ def __read(*names, **kwargs): # Stolen from pip def __find_version(*file_paths): + """Searches for a version attribute in the given file(s)""" version_file = __read(*file_paths) version_match = re.search(r"^__version__ = ['\"]([^'\"]*)['\"]", version_file, re.M) if version_match: @@ -38,11 +40,20 @@ def __find_version(*file_paths): def get_version(): + """ + Gets the current OSACA version stated in the __init__ file + + :returns: str -- the version string. + """ return __find_version('__init__.py') def create_parser(): - """Return argparse parser.""" + """ + Return argparse parser. + + :returns: The newly created :class:`~Argparse.ArgumentParser` object. + """ # Create parser parser = argparse.ArgumentParser( description='Analyzes a marked innermost loop snippet for a given architecture type.', @@ -79,8 +90,8 @@ def create_parser(): type=str, default=argparse.SUPPRESS, help='Import a given microbenchmark output file into the corresponding architecture ' - 'instruction database. Define the type of microbenchmark either as "ibench", ' - '"asmbench" or "uopsinfo".', + 'instruction database. Define the type of microbenchmark either as "ibench" or ' + '"asmbench".', ) parser.add_argument( '--insert-marker', @@ -109,9 +120,14 @@ def create_parser(): def check_arguments(args, parser): - """Check arguments passed by user that are not checked by argparse itself.""" + """ + Check arguments passed by user that are not checked by argparse itself. + + :param args: arguments given from :class:`~argparse.ArgumentParser` after parsing + :param parser: :class:`~argparse.ArgumentParser` object + """ supported_archs = ['SNB', 'IVB', 'HSW', 'BDW', 'SKX', 'CSX', 'ZEN1', 'TX2'] - supported_import_files = ['ibench', 'asmbench', 'uopsinfo'] + supported_import_files = ['ibench', 'asmbench'] if 'arch' in args and args.arch.upper() not in supported_archs: parser.error( @@ -125,6 +141,10 @@ def check_arguments(args, parser): def check_user_dir(): + """ + Creates user directory if it does not exist and copies all not already existing YAML files + into it. + """ # Check if data files are already in usr dir, otherwise create them if not os.path.isdir(DATA_DIR): os.makedirs(DATA_DIR) @@ -134,15 +154,30 @@ def check_user_dir(): def import_data(benchmark_type, arch, filepath): + """ + Imports benchmark results from micro-benchmarks. + + :param benchmark_type: key for defining type of benchmark output + :type benchmark_type: str + :param arch: target architecture to put the data into the right database + :type arch: str + :param filepath: filepath of the output file" + :type filepath: str + """ if benchmark_type.lower() == 'ibench': import_benchmark_output(arch, 'ibench', filepath) elif benchmark_type.lower() == 'asmbench': import_benchmark_output(arch, 'asmbench', filepath) else: - raise NotImplementedError('This benchmark input variant is not implemented yet.') + raise NotImplementedError('This benchmark input variant is not supported.') def insert_byte_marker(args): + """ + Inserts byte markers into an assembly file using kerncraft. + + :param args: arguments given from :class:`~argparse.ArgumentParser` after parsing + """ if MachineModel.get_isa_for_arch(args.arch) != 'x86': print('Marker insertion for non-x86 is not yet supported by Kerncraft.', file=sys.stderr) sys.exit(1) @@ -174,6 +209,12 @@ def insert_byte_marker(args): def inspect(args): + """ + Does the actual throughput and critical path analysis of OSACA and prints it to the + terminal. + + :param args: arguments given from :class:`~argparse.ArgumentParser` after parsing + """ arch = args.arch isa = MachineModel.get_isa_for_arch(arch) verbose = args.verbose @@ -203,6 +244,12 @@ def inspect(args): def run(args, output_file=sys.stdout): + """ + Main entry point for OSACAs workflow. Decides whether to run an analysis or other things. + + :param args: arguments given from :class:`~argparse.ArgumentParser` after parsing + :param output_file: Define the stream for output, defaults to :class:`sys.stdout` + """ if args.check_db: # Sanity check on DB verbose = True if args.verbose > 0 else False @@ -220,6 +267,13 @@ def run(args, output_file=sys.stdout): # --------------------------------------------------- def get_asm_parser(arch) -> BaseParser: + """ + Helper function to create the right parser for a specific architecture. + + :param arch: architecture code + :type arch: str + :returns: :class:`~osaca.parser.BaseParser` object + """ isa = MachineModel.get_isa_for_arch(arch) if isa == 'x86': return ParserX86ATT() diff --git a/osaca/semantics/arch_semantics.py b/osaca/semantics/arch_semantics.py index d398d9a..0e4af4c 100755 --- a/osaca/semantics/arch_semantics.py +++ b/osaca/semantics/arch_semantics.py @@ -125,6 +125,14 @@ class ArchSemantics(ISASemantics): instruction_data = self._machine_model.get_instruction( instruction_form['instruction'], instruction_form['operands'] ) + if ( + not instruction_data + and self._isa == 'x86' + and instruction_form['instruction'][-1] in 'bwlq' + ): + instruction_data = self._machine_model.get_instruction( + instruction_form['instruction'][:-1], instruction_form['operands'] + ) if instruction_data: # instruction form in DB throughput = instruction_data['throughput']