diff --git a/README.rst b/README.rst index 310bb3b..6f40adb 100644 --- a/README.rst +++ b/README.rst @@ -171,6 +171,8 @@ Supported microarchitectures +----------+-----------------+------------+ | AMD | Genoa / Zen 4 | ``ZEN4`` | +----------+-----------------+------------+ +| AMD | Turin / Zen 5 | ``ZEN5`` | ++----------+-----------------+------------+ **ARM AArch64 CPUs** diff --git a/osaca/data/zen5.yml b/osaca/data/zen5.yml new file mode 100644 index 0000000..04c54c7 --- /dev/null +++ b/osaca/data/zen5.yml @@ -0,0 +1,39665 @@ +osaca_version: 0.7.2 +micro_architecture: AMD Zen5 +arch_code: ZEN5 +isa: x86 +ROB_size: 448 +dispatched_uops_per_cycle: 8 +retired_uOps_per_cycle: ~ +scheduler_size: 114 +hidden_loads: false +load_latency: {gpr: 4.0, mm: 4.0, xmm: 4.0, ymm: 4.0, zmm: 4.0} +load_throughput: +- {dst: gpr, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['12', '13', '14', '15']]]} +- {dst: xmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['4D', '5D']], [1, ['12', '13', '14', '15']]]} +- {dst: ymm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['4D', '5D']], [1, ['12', '13', '14', '15']]]} +- {dst: zmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['4D', '5D']], [1, ['12', '13', '14', '15']]]} +load_throughput_default: [[1, ['4D', '5D']], [1, ['12', '13', '14', '15']]] +store_throughput: +- {src: gpr, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '45'], [1, ['12', '13', '14', '15']]]} +- {src: xmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '45'], [1, ['12', '13', '14', '15']]]} +- {src: ymm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '45'], [1, ['12', '13', '14', '15']]]} +- {src: zmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '4'], [1, '5'], [1, ['12', '13', '14', '15']]]} +store_throughput_default: [[1, '45'], [1, ['12', '13', '14', '15']]] +store_to_load_forward_latency: 0.0 +ports: ['0', 0DV, '1', '2', 2DV, '3', '4', 4D, '5', 5D, '6', '7', '8', '9', '10', '11', '12', '13', '14', '15'] +port_model_scheme: | + +-------------------------------------------------------+ +-----------------------------------------------------------------------------+ + |FP0-5 3x38 OoO scheduler | |INT0-9 2x?? OoO scheduler (ALUs / AGUs) | + | FP0 FP2 FP1 FP3 | | | + +-------------------------------------------------------+ +-----------------------------------------------------------------------------+ + 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | + \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ + +-------+ +-------+ +-------+ +-------+ +------+ +------+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ + |AVXiALU| |AVX ALU| |AVXiALU| |AVX ALU| | ST | | ST | | ALU | | ALU | | ALU | | ALU | | ALU | | ALU | | AGU | | AGU | | AGU | | AGU | + +-------+ +-------+ +-------+ +-------+ +------+ +------+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ + +-------+ +-------+ +-------+ +-------+ +------+ +------+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ + |AVX MUL| |AVX ADD| |AVX MUL| |AVX ADD| | FP2I | | FP2I | | MUL | | MUL | | MUL | | BR | | BR | | BR | | iLD | | iLD | | iLD | | iLD | + +-------+ +-------+ +-------+ +-------+ +------+ +------+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ + +-------+ +-------+ +-------+ +-------+ +------+ +------+ + |AVX FMA| | | |AVX FMA| | | | | | | + +-------+ +-------+ +-------+ +-------+ +------+ +------+ + +-------+ +-------+ + | DIV | | DIV | + +-------+ +-------+ + +instruction_forms: +########################################## +# assume all jmp instruction 0 +- name: [jo, jno, js, jns, jp, jpe, jnp, jpo] + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: [jc, jb, jae, jnb, jna, jbe, ja, jnbe] + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: [je, jz, jne, jnz, jl, jnge] + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: [jge, jnl, jle, jng, jg, jnle] + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +- name: jmp + operands: + - class: identifier + throughput: 0.0 + latency: 0.0 + port_pressure: [] +########################################## +# assume all cmp's equal for now +# TODO add cmp instructions +- name: [cmp, cmpeqpd, cmpltpd, cmplepd, cmpunordpd, cmpneqpd, cmpnltpd, cmpnlepd, cmpordpd, cmpltps, cmpleps, cmpunordps, cmpneqps, cmpnltps, cmpnleps, cmpordps] + operands: + - class: register + name: '*' + - class: register + name: '*' + latency: 1.0 + port_pressure: [[1, ['9', '10', '11']]] + throughput: 0.33333 + uops: 1 +- name: [cmp, cmpeqpd, cmpltpd, cmplepd, cmpunordpd, cmpneqpd, cmpnltpd, cmpnlepd, cmpordpd, cmpltps, cmpleps, cmpunordps, cmpneqps, cmpnltps, cmpnleps, cmpordps] + operands: + - class: register + name: '*' + - class: immediate + imd: int + latency: 1.0 + port_pressure: [[1, ['9', '10', '11']]] + throughput: 0.33333 + uops: 1 +########################################## +- name: push + operands: + - class: immediate + imd: int + latency: 0 + port_pressure: [] + throughput: ~ + uops: 2 +- name: push + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [] + throughput: ~ + uops: 2 +- name: push + operands: + - class: memory + base: '*' + offset: '*' + index: '*' + scale: '*' + latency: ~ + port_pressure: [] + throughput: ~ + uops: 2 +- name: pop + operands: + - class: immediate + imd: int + latency: ~ + port_pressure: [] + throughput: ~ + uops: 1 +- name: pop + operands: + - class: register + name: gpr + latency: ~ + port_pressure: [] + throughput: ~ + uops: 1 +- name: pop + operands: + - class: memory + base: '*' + offset: '*' + index: '*' + scale: '*' + latency: ~ + port_pressure: [] + throughput: ~ + uops: 2 +########################################## +# WINIC data +- name: xorps + llvm_name: XORPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: xorpd + llvm_name: XORPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16667 + uops: ~ +- name: xor + llvm_name: XOR64rr + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16667 + uops: ~ +- name: xor + llvm_name: XOR32ri + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16667 + uops: ~ +- name: xor + llvm_name: XOR8i8 + operands: + - class: immediate + imd: int + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16667 + uops: ~ +- name: xchg + llvm_name: XCHG64rr + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 0.2 + port_pressure: [[1, ['6', '7', '8', '9']]] + throughput: 0.25 + uops: ~ +- name: xchg + llvm_name: XCHG64ar + operands: + - class: register + name: gpr + latency: 0.2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16667 + uops: ~ +- name: xadd + llvm_name: XADD8rr + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[2, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.33333 + uops: ~ +- name: vxorps + llvm_name: VXORPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vxorps + llvm_name: VXORPSZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vxorps + llvm_name: VXORPSZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vxorps + llvm_name: VXORPSZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vxorps + llvm_name: VXORPSYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vxorps + llvm_name: VXORPSZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vxorpd + llvm_name: VXORPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vxorpd + llvm_name: VXORPDZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vxorpd + llvm_name: VXORPDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vxorpd + llvm_name: VXORPDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vxorpd + llvm_name: VXORPDYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vxorpd + llvm_name: VXORPDZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpcklps + llvm_name: VUNPCKLPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpcklps + llvm_name: VUNPCKLPSZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpcklps + llvm_name: VUNPCKLPSZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpcklps + llvm_name: VUNPCKLPSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpcklps + llvm_name: VUNPCKLPSYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpcklps + llvm_name: VUNPCKLPSZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpcklpd + llvm_name: VUNPCKLPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpcklpd + llvm_name: VUNPCKLPDZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpcklpd + llvm_name: VUNPCKLPDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpcklpd + llvm_name: VUNPCKLPDZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpcklpd + llvm_name: VUNPCKLPDYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpcklpd + llvm_name: VUNPCKLPDZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpckhps + llvm_name: VUNPCKHPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpckhps + llvm_name: VUNPCKHPSZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpckhps + llvm_name: VUNPCKHPSZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpckhps + llvm_name: VUNPCKHPSZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpckhps + llvm_name: VUNPCKHPSYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpckhps + llvm_name: VUNPCKHPSZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpckhpd + llvm_name: VUNPCKHPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpckhpd + llvm_name: VUNPCKHPDZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpckhpd + llvm_name: VUNPCKHPDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpckhpd + llvm_name: VUNPCKHPDZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpckhpd + llvm_name: VUNPCKHPDYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vunpckhpd + llvm_name: VUNPCKHPDZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vsubss + llvm_name: VSUBSSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vsubss + llvm_name: VSUBSSZrrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vsubsd + llvm_name: VSUBSDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vsubsd + llvm_name: VSUBSDZrrbkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vsubps + llvm_name: VSUBPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vsubps + llvm_name: VSUBPSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vsubps + llvm_name: VSUBPSZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vsubps + llvm_name: VSUBPSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vsubps + llvm_name: VSUBPSYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vsubps + llvm_name: VSUBPSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vsubpd + llvm_name: VSUBPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vsubpd + llvm_name: VSUBPDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vsubpd + llvm_name: VSUBPDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vsubpd + llvm_name: VSUBPDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vsubpd + llvm_name: VSUBPDYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vsubpd + llvm_name: VSUBPDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vsqrtss + llvm_name: VSQRTSSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 21 + port_pressure: [[19, ['0', '2']]] + throughput: 9.5 + uops: ~ +- name: vsqrtss + llvm_name: VSQRTSSZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 21 + port_pressure: [[19, ['0', '2']]] + throughput: 9.5 + uops: ~ +- name: vsqrtsd + llvm_name: VSQRTSDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 23 + port_pressure: [[19, ['0', '2']]] + throughput: 9.5 + uops: ~ +- name: vsqrtsd + llvm_name: VSQRTSDZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 20 + port_pressure: [[15, ['0', '2']]] + throughput: 7.5 + uops: ~ +- name: vsqrtps + llvm_name: VSQRTPSr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[19, ['0', '2']]] + throughput: 9.5 + uops: ~ +- name: vsqrtps + llvm_name: VSQRTPSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 14 + port_pressure: [[9, ['0', '2']]] + throughput: 4.5 + uops: ~ +- name: vsqrtps + llvm_name: VSQRTPSZr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 14 + port_pressure: [[19, ['0', '2']]] + throughput: 9.5 + uops: ~ +- name: vsqrtps + llvm_name: VSQRTPSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 14 + port_pressure: [[9, ['0', '2']]] + throughput: 4.5 + uops: ~ +- name: vsqrtps + llvm_name: VSQRTPSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 14 + port_pressure: [[19, ['0', '2']]] + throughput: 9.5 + uops: ~ +- name: vsqrtps + llvm_name: VSQRTPSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 14 + port_pressure: [[9, ['0', '2']]] + throughput: 4.5 + uops: ~ +- name: vsqrtpd + llvm_name: VSQRTPDr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[19, ['0', '2']]] + throughput: 9.5 + uops: ~ +- name: vsqrtpd + llvm_name: VSQRTPDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 20 + port_pressure: [[15, ['0', '2']]] + throughput: 7.5 + uops: ~ +- name: vsqrtpd + llvm_name: VSQRTPDZr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 20 + port_pressure: [[19, ['0', '2']]] + throughput: 9.5 + uops: ~ +- name: vsqrtpd + llvm_name: VSQRTPDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 20 + port_pressure: [[15, ['0', '2']]] + throughput: 7.5 + uops: ~ +- name: vsqrtpd + llvm_name: VSQRTPDYr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 20 + port_pressure: [[19, ['0', '2']]] + throughput: 9.5 + uops: ~ +- name: vsqrtpd + llvm_name: VSQRTPDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 20 + port_pressure: [[15, ['0', '2']]] + throughput: 7.5 + uops: ~ +- name: vshufps + llvm_name: VSHUFPSrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vshufps + llvm_name: VSHUFPSZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vshufps + llvm_name: VSHUFPSZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vshufps + llvm_name: VSHUFPSZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vshufps + llvm_name: VSHUFPSZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vshufps + llvm_name: VSHUFPSZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vshufpd + llvm_name: VSHUFPDrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vshufpd + llvm_name: VSHUFPDZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vshufpd + llvm_name: VSHUFPDZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vshufpd + llvm_name: VSHUFPDZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vshufpd + llvm_name: VSHUFPDZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vshufpd + llvm_name: VSHUFPDZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vshufi64x2 + llvm_name: VSHUFI64X2Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vshufi64x2 + llvm_name: VSHUFI64X2Zrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vshufi64x2 + llvm_name: VSHUFI64X2Z256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vshufi64x2 + llvm_name: VSHUFI64X2Z256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vshufi32x4 + llvm_name: VSHUFI32X4Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vshufi32x4 + llvm_name: VSHUFI32X4Zrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vshufi32x4 + llvm_name: VSHUFI32X4Z256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vshufi32x4 + llvm_name: VSHUFI32X4Z256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vshuff64x2 + llvm_name: VSHUFF64X2Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vshuff64x2 + llvm_name: VSHUFF64X2Zrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vshuff64x2 + llvm_name: VSHUFF64X2Z256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vshuff64x2 + llvm_name: VSHUFF64X2Z256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vshuff32x4 + llvm_name: VSHUFF32X4Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vshuff32x4 + llvm_name: VSHUFF32X4Zrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vshuff32x4 + llvm_name: VSHUFF32X4Z256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vshuff32x4 + llvm_name: VSHUFF32X4Z256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vscalefss + llvm_name: VSCALEFSSZrrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1']], [1, ['3']]] + throughput: 1.0 + uops: ~ +- name: vscalefss + llvm_name: VSCALEFSSZrrb_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1']], [1, ['3']]] + throughput: 1.0 + uops: ~ +- name: vscalefsd + llvm_name: VSCALEFSDZrrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1']], [1, ['3']]] + throughput: 2.0 + uops: ~ +- name: vscalefsd + llvm_name: VSCALEFSDZrrb_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1']], [1, ['3']]] + throughput: 2.0 + uops: ~ +- name: vscalefps + llvm_name: VSCALEFPSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, ['1']], [1, ['3']]] + throughput: 2.0 + uops: ~ +- name: vscalefps + llvm_name: VSCALEFPSZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, ['1']], [1, ['3']]] + throughput: 2.0 + uops: ~ +- name: vscalefps + llvm_name: VSCALEFPSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 6 + port_pressure: [[1, ['1']], [1, ['3']]] + throughput: 2.0 + uops: ~ +- name: vscalefps + llvm_name: VSCALEFPSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, ['1']], [1, ['3']]] + throughput: 2.0 + uops: ~ +- name: vscalefps + llvm_name: VSCALEFPSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1']], [1, ['3']]] + throughput: 2.0 + uops: ~ +- name: vscalefps + llvm_name: VSCALEFPSZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1']], [1, ['3']]] + throughput: 2.0 + uops: ~ +- name: vscalefpd + llvm_name: VSCALEFPDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, ['1']], [1, ['3']]] + throughput: 2.0 + uops: ~ +- name: vscalefpd + llvm_name: VSCALEFPDZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, ['1']], [1, ['3']]] + throughput: 2.0 + uops: ~ +- name: vscalefpd + llvm_name: VSCALEFPDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 6 + port_pressure: [[1, ['1']], [1, ['3']]] + throughput: 2.0 + uops: ~ +- name: vscalefpd + llvm_name: VSCALEFPDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, ['1']], [1, ['3']]] + throughput: 2.0 + uops: ~ +- name: vscalefpd + llvm_name: VSCALEFPDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1']], [1, ['3']]] + throughput: 2.0 + uops: ~ +- name: vscalefpd + llvm_name: VSCALEFPDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1']], [1, ['3']]] + throughput: 2.0 + uops: ~ +- name: vrsqrtss + llvm_name: VRSQRTSSr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrtps + llvm_name: VRSQRTPSr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrtps + llvm_name: VRSQRTPSYr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrt14ss + llvm_name: VRSQRT14SSZrrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrt14ss + llvm_name: VRSQRT14SSZrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrt14sd + llvm_name: VRSQRT14SDZrrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrt14sd + llvm_name: VRSQRT14SDZrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrt14ps + llvm_name: VRSQRT14PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrt14ps + llvm_name: VRSQRT14PSZr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrt14ps + llvm_name: VRSQRT14PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrt14ps + llvm_name: VRSQRT14PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrt14ps + llvm_name: VRSQRT14PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrt14ps + llvm_name: VRSQRT14PSZ128r + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrt14pd + llvm_name: VRSQRT14PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrt14pd + llvm_name: VRSQRT14PDZr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrt14pd + llvm_name: VRSQRT14PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrt14pd + llvm_name: VRSQRT14PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrt14pd + llvm_name: VRSQRT14PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrsqrt14pd + llvm_name: VRSQRT14PDZ128r + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vroundss + llvm_name: VROUNDSSri_Int + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vroundsd + llvm_name: VROUNDSDri_Int + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vroundps + llvm_name: VROUNDPSri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vroundps + llvm_name: VROUNDPSYri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vroundpd + llvm_name: VROUNDPDri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vroundpd + llvm_name: VROUNDPDYri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrndscaless + llvm_name: VRNDSCALESSZrrikz_Int + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrndscaless + llvm_name: VRNDSCALESSZrrib_Int + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrndscalesd + llvm_name: VRNDSCALESDZrrikz_Int + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrndscalesd + llvm_name: VRNDSCALESDZrrib_Int + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrndscaleps + llvm_name: VRNDSCALEPSZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrndscaleps + llvm_name: VRNDSCALEPSZrrib + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrndscaleps + llvm_name: VRNDSCALEPSZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrndscaleps + llvm_name: VRNDSCALEPSZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrndscaleps + llvm_name: VRNDSCALEPSZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrndscaleps + llvm_name: VRNDSCALEPSZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrndscalepd + llvm_name: VRNDSCALEPDZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrndscalepd + llvm_name: VRNDSCALEPDZrrib + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrndscalepd + llvm_name: VRNDSCALEPDZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrndscalepd + llvm_name: VRNDSCALEPDZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrndscalepd + llvm_name: VRNDSCALEPDZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrndscalepd + llvm_name: VRNDSCALEPDZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vreducess + llvm_name: VREDUCESSZrrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: vreducess + llvm_name: VREDUCESSZrrib + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: vreducesd + llvm_name: VREDUCESDZrrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: vreducesd + llvm_name: VREDUCESDZrrib + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: vreduceps + llvm_name: VREDUCEPSZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: vreduceps + llvm_name: VREDUCEPSZrrib + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: vreduceps + llvm_name: VREDUCEPSZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 6 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: vreduceps + llvm_name: VREDUCEPSZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: vreduceps + llvm_name: VREDUCEPSZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: vreduceps + llvm_name: VREDUCEPSZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: vreducepd + llvm_name: VREDUCEPDZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: vreducepd + llvm_name: VREDUCEPDZrrib + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: vreducepd + llvm_name: VREDUCEPDZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 6 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: vreducepd + llvm_name: VREDUCEPDZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: vreducepd + llvm_name: VREDUCEPDZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: vreducepd + llvm_name: VREDUCEPDZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: vrcpss + llvm_name: VRCPSSr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcpps + llvm_name: VRCPPSr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcpps + llvm_name: VRCPPSYr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcp14ss + llvm_name: VRCP14SSZrrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcp14ss + llvm_name: VRCP14SSZrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcp14sd + llvm_name: VRCP14SDZrrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcp14sd + llvm_name: VRCP14SDZrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcp14ps + llvm_name: VRCP14PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcp14ps + llvm_name: VRCP14PSZr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcp14ps + llvm_name: VRCP14PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcp14ps + llvm_name: VRCP14PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcp14ps + llvm_name: VRCP14PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcp14ps + llvm_name: VRCP14PSZ128r + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcp14pd + llvm_name: VRCP14PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcp14pd + llvm_name: VRCP14PDZr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcp14pd + llvm_name: VRCP14PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcp14pd + llvm_name: VRCP14PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcp14pd + llvm_name: VRCP14PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrcp14pd + llvm_name: VRCP14PDZ128r + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vrangess + llvm_name: VRANGESSZrrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrangess + llvm_name: VRANGESSZrrib + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrangesd + llvm_name: VRANGESDZrrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrangesd + llvm_name: VRANGESDZrrib + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrangeps + llvm_name: VRANGEPSZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrangeps + llvm_name: VRANGEPSZrrib + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrangeps + llvm_name: VRANGEPSZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrangeps + llvm_name: VRANGEPSZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrangeps + llvm_name: VRANGEPSZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrangeps + llvm_name: VRANGEPSZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrangepd + llvm_name: VRANGEPDZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrangepd + llvm_name: VRANGEPDZrrib + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrangepd + llvm_name: VRANGEPDZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrangepd + llvm_name: VRANGEPDZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrangepd + llvm_name: VRANGEPDZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vrangepd + llvm_name: VRANGEPDZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpxor + llvm_name: VPXORrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpxor + llvm_name: VPXORYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpxorq + llvm_name: VPXORQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpxorq + llvm_name: VPXORQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpxorq + llvm_name: VPXORQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpxorq + llvm_name: VPXORQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpxorq + llvm_name: VPXORQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpxorq + llvm_name: VPXORQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpxord + llvm_name: VPXORDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpxord + llvm_name: VPXORDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpxord + llvm_name: VPXORDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpxord + llvm_name: VPXORDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpxord + llvm_name: VPXORDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpxord + llvm_name: VPXORDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklwd + llvm_name: VPUNPCKLWDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklwd + llvm_name: VPUNPCKLWDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklwd + llvm_name: VPUNPCKLWDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklwd + llvm_name: VPUNPCKLWDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklwd + llvm_name: VPUNPCKLWDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklwd + llvm_name: VPUNPCKLWDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklqdq + llvm_name: VPUNPCKLQDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklqdq + llvm_name: VPUNPCKLQDQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklqdq + llvm_name: VPUNPCKLQDQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklqdq + llvm_name: VPUNPCKLQDQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklqdq + llvm_name: VPUNPCKLQDQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklqdq + llvm_name: VPUNPCKLQDQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckldq + llvm_name: VPUNPCKLDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckldq + llvm_name: VPUNPCKLDQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckldq + llvm_name: VPUNPCKLDQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckldq + llvm_name: VPUNPCKLDQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckldq + llvm_name: VPUNPCKLDQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckldq + llvm_name: VPUNPCKLDQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklbw + llvm_name: VPUNPCKLBWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklbw + llvm_name: VPUNPCKLBWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklbw + llvm_name: VPUNPCKLBWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklbw + llvm_name: VPUNPCKLBWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklbw + llvm_name: VPUNPCKLBWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpcklbw + llvm_name: VPUNPCKLBWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhwd + llvm_name: VPUNPCKHWDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhwd + llvm_name: VPUNPCKHWDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhwd + llvm_name: VPUNPCKHWDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhwd + llvm_name: VPUNPCKHWDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhwd + llvm_name: VPUNPCKHWDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhwd + llvm_name: VPUNPCKHWDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhqdq + llvm_name: VPUNPCKHQDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhqdq + llvm_name: VPUNPCKHQDQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhqdq + llvm_name: VPUNPCKHQDQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhqdq + llvm_name: VPUNPCKHQDQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhqdq + llvm_name: VPUNPCKHQDQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhqdq + llvm_name: VPUNPCKHQDQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhdq + llvm_name: VPUNPCKHDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhdq + llvm_name: VPUNPCKHDQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhdq + llvm_name: VPUNPCKHDQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhdq + llvm_name: VPUNPCKHDQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhdq + llvm_name: VPUNPCKHDQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhdq + llvm_name: VPUNPCKHDQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhbw + llvm_name: VPUNPCKHBWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhbw + llvm_name: VPUNPCKHBWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhbw + llvm_name: VPUNPCKHBWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhbw + llvm_name: VPUNPCKHBWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhbw + llvm_name: VPUNPCKHBWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpunpckhbw + llvm_name: VPUNPCKHBWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vptestnmw + llvm_name: VPTESTNMWZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmw + llvm_name: VPTESTNMWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmw + llvm_name: VPTESTNMWZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmw + llvm_name: VPTESTNMWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmw + llvm_name: VPTESTNMWZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmw + llvm_name: VPTESTNMWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmq + llvm_name: VPTESTNMQZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmq + llvm_name: VPTESTNMQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmq + llvm_name: VPTESTNMQZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmq + llvm_name: VPTESTNMQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmq + llvm_name: VPTESTNMQZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmq + llvm_name: VPTESTNMQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmd + llvm_name: VPTESTNMDZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmd + llvm_name: VPTESTNMDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmd + llvm_name: VPTESTNMDZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmd + llvm_name: VPTESTNMDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmd + llvm_name: VPTESTNMDZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmd + llvm_name: VPTESTNMDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmb + llvm_name: VPTESTNMBZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmb + llvm_name: VPTESTNMBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmb + llvm_name: VPTESTNMBZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmb + llvm_name: VPTESTNMBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmb + llvm_name: VPTESTNMBZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestnmb + llvm_name: VPTESTNMBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmw + llvm_name: VPTESTMWZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmw + llvm_name: VPTESTMWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmw + llvm_name: VPTESTMWZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmw + llvm_name: VPTESTMWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmw + llvm_name: VPTESTMWZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmw + llvm_name: VPTESTMWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmq + llvm_name: VPTESTMQZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmq + llvm_name: VPTESTMQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmq + llvm_name: VPTESTMQZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmq + llvm_name: VPTESTMQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmq + llvm_name: VPTESTMQZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmq + llvm_name: VPTESTMQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmd + llvm_name: VPTESTMDZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmd + llvm_name: VPTESTMDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmd + llvm_name: VPTESTMDZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmd + llvm_name: VPTESTMDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmd + llvm_name: VPTESTMDZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmd + llvm_name: VPTESTMDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmb + llvm_name: VPTESTMBZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmb + llvm_name: VPTESTMBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmb + llvm_name: VPTESTMBZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmb + llvm_name: VPTESTMBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmb + llvm_name: VPTESTMBZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vptestmb + llvm_name: VPTESTMBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpternlogq + llvm_name: VPTERNLOGQZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpternlogq + llvm_name: VPTERNLOGQZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpternlogq + llvm_name: VPTERNLOGQZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpternlogq + llvm_name: VPTERNLOGQZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpternlogq + llvm_name: VPTERNLOGQZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpternlogq + llvm_name: VPTERNLOGQZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpternlogd + llvm_name: VPTERNLOGDZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpternlogd + llvm_name: VPTERNLOGDZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpternlogd + llvm_name: VPTERNLOGDZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpternlogd + llvm_name: VPTERNLOGDZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpternlogd + llvm_name: VPTERNLOGDZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpternlogd + llvm_name: VPTERNLOGDZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubw + llvm_name: VPSUBWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubw + llvm_name: VPSUBWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubw + llvm_name: VPSUBWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubw + llvm_name: VPSUBWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubw + llvm_name: VPSUBWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubw + llvm_name: VPSUBWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubusw + llvm_name: VPSUBUSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubusw + llvm_name: VPSUBUSWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubusw + llvm_name: VPSUBUSWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubusw + llvm_name: VPSUBUSWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubusw + llvm_name: VPSUBUSWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubusw + llvm_name: VPSUBUSWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubusb + llvm_name: VPSUBUSBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubusb + llvm_name: VPSUBUSBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubusb + llvm_name: VPSUBUSBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubusb + llvm_name: VPSUBUSBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubusb + llvm_name: VPSUBUSBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubusb + llvm_name: VPSUBUSBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubsw + llvm_name: VPSUBSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubsw + llvm_name: VPSUBSWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubsw + llvm_name: VPSUBSWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubsw + llvm_name: VPSUBSWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubsw + llvm_name: VPSUBSWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubsw + llvm_name: VPSUBSWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubsb + llvm_name: VPSUBSBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubsb + llvm_name: VPSUBSBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubsb + llvm_name: VPSUBSBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubsb + llvm_name: VPSUBSBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubsb + llvm_name: VPSUBSBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubsb + llvm_name: VPSUBSBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpsubq + llvm_name: VPSUBQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubq + llvm_name: VPSUBQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubq + llvm_name: VPSUBQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubq + llvm_name: VPSUBQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubq + llvm_name: VPSUBQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubq + llvm_name: VPSUBQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubd + llvm_name: VPSUBDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubd + llvm_name: VPSUBDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubd + llvm_name: VPSUBDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubd + llvm_name: VPSUBDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubd + llvm_name: VPSUBDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubd + llvm_name: VPSUBDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubb + llvm_name: VPSUBBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubb + llvm_name: VPSUBBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubb + llvm_name: VPSUBBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubb + llvm_name: VPSUBBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubb + llvm_name: VPSUBBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsubb + llvm_name: VPSUBBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpsrlw + llvm_name: VPSRLWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrlw + llvm_name: VPSRLWri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlw + llvm_name: VPSRLWZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrlw + llvm_name: VPSRLWZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrlw + llvm_name: VPSRLWZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlw + llvm_name: VPSRLWZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlw + llvm_name: VPSRLWZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrlw + llvm_name: VPSRLWZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrlw + llvm_name: VPSRLWZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlw + llvm_name: VPSRLWZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlw + llvm_name: VPSRLWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrlw + llvm_name: VPSRLWZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlvw + llvm_name: VPSRLVWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrlvw + llvm_name: VPSRLVWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrlvw + llvm_name: VPSRLVWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrlvw + llvm_name: VPSRLVWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrlvw + llvm_name: VPSRLVWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrlvw + llvm_name: VPSRLVWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrlvq + llvm_name: VPSRLVQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlvq + llvm_name: VPSRLVQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlvq + llvm_name: VPSRLVQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlvq + llvm_name: VPSRLVQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlvq + llvm_name: VPSRLVQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlvq + llvm_name: VPSRLVQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlvd + llvm_name: VPSRLVDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlvd + llvm_name: VPSRLVDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlvd + llvm_name: VPSRLVDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlvd + llvm_name: VPSRLVDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlvd + llvm_name: VPSRLVDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlvd + llvm_name: VPSRLVDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlq + llvm_name: VPSRLQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrlq + llvm_name: VPSRLQri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlq + llvm_name: VPSRLQZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrlq + llvm_name: VPSRLQZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrlq + llvm_name: VPSRLQZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlq + llvm_name: VPSRLQZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlq + llvm_name: VPSRLQZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlq + llvm_name: VPSRLQZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlq + llvm_name: VPSRLQZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlq + llvm_name: VPSRLQZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlq + llvm_name: VPSRLQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrlq + llvm_name: VPSRLQZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrld + llvm_name: VPSRLDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrld + llvm_name: VPSRLDri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrld + llvm_name: VPSRLDZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrld + llvm_name: VPSRLDZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrld + llvm_name: VPSRLDZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrld + llvm_name: VPSRLDZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrld + llvm_name: VPSRLDZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrld + llvm_name: VPSRLDZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrld + llvm_name: VPSRLDZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrld + llvm_name: VPSRLDZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrld + llvm_name: VPSRLDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrld + llvm_name: VPSRLDZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrldq + llvm_name: VPSRLDQri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrldq + llvm_name: VPSRLDQZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrldq + llvm_name: VPSRLDQZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsraw + llvm_name: VPSRAWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsraw + llvm_name: VPSRAWri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsraw + llvm_name: VPSRAWZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsraw + llvm_name: VPSRAWZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsraw + llvm_name: VPSRAWZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsraw + llvm_name: VPSRAWZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsraw + llvm_name: VPSRAWZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsraw + llvm_name: VPSRAWZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsraw + llvm_name: VPSRAWZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsraw + llvm_name: VPSRAWZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsraw + llvm_name: VPSRAWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsraw + llvm_name: VPSRAWZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravw + llvm_name: VPSRAVWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravw + llvm_name: VPSRAVWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravw + llvm_name: VPSRAVWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravw + llvm_name: VPSRAVWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravw + llvm_name: VPSRAVWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravw + llvm_name: VPSRAVWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravq + llvm_name: VPSRAVQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravq + llvm_name: VPSRAVQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravq + llvm_name: VPSRAVQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravq + llvm_name: VPSRAVQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravq + llvm_name: VPSRAVQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravq + llvm_name: VPSRAVQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravd + llvm_name: VPSRAVDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravd + llvm_name: VPSRAVDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravd + llvm_name: VPSRAVDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravd + llvm_name: VPSRAVDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravd + llvm_name: VPSRAVDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsravd + llvm_name: VPSRAVDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsraq + llvm_name: VPSRAQZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsraq + llvm_name: VPSRAQZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsraq + llvm_name: VPSRAQZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsraq + llvm_name: VPSRAQZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsraq + llvm_name: VPSRAQZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsraq + llvm_name: VPSRAQZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsraq + llvm_name: VPSRAQZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsraq + llvm_name: VPSRAQZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsraq + llvm_name: VPSRAQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsraq + llvm_name: VPSRAQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsraq + llvm_name: VPSRAQZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsraq + llvm_name: VPSRAQZ128ri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrad + llvm_name: VPSRADrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrad + llvm_name: VPSRADri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrad + llvm_name: VPSRADZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrad + llvm_name: VPSRADZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrad + llvm_name: VPSRADZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrad + llvm_name: VPSRADZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrad + llvm_name: VPSRADZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrad + llvm_name: VPSRADZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrad + llvm_name: VPSRADZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrad + llvm_name: VPSRADZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsrad + llvm_name: VPSRADZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsrad + llvm_name: VPSRADZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllw + llvm_name: VPSLLWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsllw + llvm_name: VPSLLWri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllw + llvm_name: VPSLLWZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsllw + llvm_name: VPSLLWZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsllw + llvm_name: VPSLLWZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllw + llvm_name: VPSLLWZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllw + llvm_name: VPSLLWZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsllw + llvm_name: VPSLLWZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsllw + llvm_name: VPSLLWZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllw + llvm_name: VPSLLWZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllw + llvm_name: VPSLLWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsllw + llvm_name: VPSLLWZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvw + llvm_name: VPSLLVWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvw + llvm_name: VPSLLVWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvw + llvm_name: VPSLLVWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvw + llvm_name: VPSLLVWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvw + llvm_name: VPSLLVWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvw + llvm_name: VPSLLVWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvq + llvm_name: VPSLLVQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvq + llvm_name: VPSLLVQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvq + llvm_name: VPSLLVQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvq + llvm_name: VPSLLVQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvq + llvm_name: VPSLLVQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvq + llvm_name: VPSLLVQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvd + llvm_name: VPSLLVDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvd + llvm_name: VPSLLVDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvd + llvm_name: VPSLLVDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvd + llvm_name: VPSLLVDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvd + llvm_name: VPSLLVDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllvd + llvm_name: VPSLLVDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllq + llvm_name: VPSLLQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsllq + llvm_name: VPSLLQri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllq + llvm_name: VPSLLQZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsllq + llvm_name: VPSLLQZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsllq + llvm_name: VPSLLQZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllq + llvm_name: VPSLLQZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllq + llvm_name: VPSLLQZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsllq + llvm_name: VPSLLQZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsllq + llvm_name: VPSLLQZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllq + llvm_name: VPSLLQZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpsllq + llvm_name: VPSLLQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsllq + llvm_name: VPSLLQZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpslld + llvm_name: VPSLLDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpslld + llvm_name: VPSLLDri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpslld + llvm_name: VPSLLDZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpslld + llvm_name: VPSLLDZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpslld + llvm_name: VPSLLDZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpslld + llvm_name: VPSLLDZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpslld + llvm_name: VPSLLDZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpslld + llvm_name: VPSLLDZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpslld + llvm_name: VPSLLDZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpslld + llvm_name: VPSLLDZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpslld + llvm_name: VPSLLDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpslld + llvm_name: VPSLLDZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vpslldq + llvm_name: VPSLLDQri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpslldq + llvm_name: VPSLLDQZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpslldq + llvm_name: VPSLLDQZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpsignw + llvm_name: VPSIGNWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsignw + llvm_name: VPSIGNWYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsignd + llvm_name: VPSIGNDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsignd + llvm_name: VPSIGNDYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsignb + llvm_name: VPSIGNBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsignb + llvm_name: VPSIGNBYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshuflw + llvm_name: VPSHUFLWri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshuflw + llvm_name: VPSHUFLWZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshuflw + llvm_name: VPSHUFLWZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshuflw + llvm_name: VPSHUFLWZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshuflw + llvm_name: VPSHUFLWZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshuflw + llvm_name: VPSHUFLWZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshufhw + llvm_name: VPSHUFHWri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshufhw + llvm_name: VPSHUFHWZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshufhw + llvm_name: VPSHUFHWZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshufhw + llvm_name: VPSHUFHWZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshufhw + llvm_name: VPSHUFHWZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshufhw + llvm_name: VPSHUFHWZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshufd + llvm_name: VPSHUFDri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshufd + llvm_name: VPSHUFDZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshufd + llvm_name: VPSHUFDZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshufd + llvm_name: VPSHUFDZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshufd + llvm_name: VPSHUFDZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshufd + llvm_name: VPSHUFDZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpshufb + llvm_name: VPSHUFBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpshufb + llvm_name: VPSHUFBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpshufb + llvm_name: VPSHUFBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpshufb + llvm_name: VPSHUFBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpshufb + llvm_name: VPSHUFBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpshufb + llvm_name: VPSHUFBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpshufbitqmb + llvm_name: VPSHUFBITQMBZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshufbitqmb + llvm_name: VPSHUFBITQMBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshufbitqmb + llvm_name: VPSHUFBITQMBZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshufbitqmb + llvm_name: VPSHUFBITQMBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshufbitqmb + llvm_name: VPSHUFBITQMBZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshufbitqmb + llvm_name: VPSHUFBITQMBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdw + llvm_name: VPSHRDWZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdw + llvm_name: VPSHRDWZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdw + llvm_name: VPSHRDWZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdw + llvm_name: VPSHRDWZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdw + llvm_name: VPSHRDWZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdw + llvm_name: VPSHRDWZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvw + llvm_name: VPSHRDVWZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvw + llvm_name: VPSHRDVWZr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvw + llvm_name: VPSHRDVWZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvw + llvm_name: VPSHRDVWZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvw + llvm_name: VPSHRDVWZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvw + llvm_name: VPSHRDVWZ128r + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvq + llvm_name: VPSHRDVQZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvq + llvm_name: VPSHRDVQZr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvq + llvm_name: VPSHRDVQZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvq + llvm_name: VPSHRDVQZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvq + llvm_name: VPSHRDVQZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvq + llvm_name: VPSHRDVQZ128r + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvd + llvm_name: VPSHRDVDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvd + llvm_name: VPSHRDVDZr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvd + llvm_name: VPSHRDVDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvd + llvm_name: VPSHRDVDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvd + llvm_name: VPSHRDVDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdvd + llvm_name: VPSHRDVDZ128r + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdq + llvm_name: VPSHRDQZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdq + llvm_name: VPSHRDQZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdq + llvm_name: VPSHRDQZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdq + llvm_name: VPSHRDQZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdq + llvm_name: VPSHRDQZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdq + llvm_name: VPSHRDQZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdd + llvm_name: VPSHRDDZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdd + llvm_name: VPSHRDDZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdd + llvm_name: VPSHRDDZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdd + llvm_name: VPSHRDDZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdd + llvm_name: VPSHRDDZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshrdd + llvm_name: VPSHRDDZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldw + llvm_name: VPSHLDWZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldw + llvm_name: VPSHLDWZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldw + llvm_name: VPSHLDWZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldw + llvm_name: VPSHLDWZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldw + llvm_name: VPSHLDWZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldw + llvm_name: VPSHLDWZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvw + llvm_name: VPSHLDVWZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvw + llvm_name: VPSHLDVWZr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvw + llvm_name: VPSHLDVWZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvw + llvm_name: VPSHLDVWZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvw + llvm_name: VPSHLDVWZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvw + llvm_name: VPSHLDVWZ128r + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvq + llvm_name: VPSHLDVQZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvq + llvm_name: VPSHLDVQZr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvq + llvm_name: VPSHLDVQZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvq + llvm_name: VPSHLDVQZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvq + llvm_name: VPSHLDVQZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvq + llvm_name: VPSHLDVQZ128r + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvd + llvm_name: VPSHLDVDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvd + llvm_name: VPSHLDVDZr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvd + llvm_name: VPSHLDVDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvd + llvm_name: VPSHLDVDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvd + llvm_name: VPSHLDVDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldvd + llvm_name: VPSHLDVDZ128r + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldq + llvm_name: VPSHLDQZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldq + llvm_name: VPSHLDQZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldq + llvm_name: VPSHLDQZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldq + llvm_name: VPSHLDQZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldq + llvm_name: VPSHLDQZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldq + llvm_name: VPSHLDQZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldd + llvm_name: VPSHLDDZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldd + llvm_name: VPSHLDDZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldd + llvm_name: VPSHLDDZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldd + llvm_name: VPSHLDDZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldd + llvm_name: VPSHLDDZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpshldd + llvm_name: VPSHLDDZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsadbw + llvm_name: VPSADBWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsadbw + llvm_name: VPSADBWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpsadbw + llvm_name: VPSADBWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorvq + llvm_name: VPRORVQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorvq + llvm_name: VPRORVQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorvq + llvm_name: VPRORVQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorvq + llvm_name: VPRORVQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorvq + llvm_name: VPRORVQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorvq + llvm_name: VPRORVQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorvd + llvm_name: VPRORVDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorvd + llvm_name: VPRORVDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorvd + llvm_name: VPRORVDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorvd + llvm_name: VPRORVDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorvd + llvm_name: VPRORVDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorvd + llvm_name: VPRORVDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorq + llvm_name: VPRORQZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorq + llvm_name: VPRORQZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorq + llvm_name: VPRORQZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorq + llvm_name: VPRORQZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorq + llvm_name: VPRORQZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprorq + llvm_name: VPRORQZ128ri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprord + llvm_name: VPRORDZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprord + llvm_name: VPRORDZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprord + llvm_name: VPRORDZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprord + llvm_name: VPRORDZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprord + llvm_name: VPRORDZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprord + llvm_name: VPRORDZ128ri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolvq + llvm_name: VPROLVQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolvq + llvm_name: VPROLVQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolvq + llvm_name: VPROLVQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolvq + llvm_name: VPROLVQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolvq + llvm_name: VPROLVQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolvq + llvm_name: VPROLVQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolvd + llvm_name: VPROLVDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolvd + llvm_name: VPROLVDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolvd + llvm_name: VPROLVDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolvd + llvm_name: VPROLVDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolvd + llvm_name: VPROLVDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolvd + llvm_name: VPROLVDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolq + llvm_name: VPROLQZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolq + llvm_name: VPROLQZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolq + llvm_name: VPROLQZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolq + llvm_name: VPROLQZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolq + llvm_name: VPROLQZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprolq + llvm_name: VPROLQZ128ri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprold + llvm_name: VPROLDZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprold + llvm_name: VPROLDZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprold + llvm_name: VPROLDZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprold + llvm_name: VPROLDZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprold + llvm_name: VPROLDZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vprold + llvm_name: VPROLDZ128ri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpor + llvm_name: VPORrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpor + llvm_name: VPORYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vporq + llvm_name: VPORQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vporq + llvm_name: VPORQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vporq + llvm_name: VPORQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vporq + llvm_name: VPORQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vporq + llvm_name: VPORQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vporq + llvm_name: VPORQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpord + llvm_name: VPORDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpord + llvm_name: VPORDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpord + llvm_name: VPORDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpord + llvm_name: VPORDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpord + llvm_name: VPORDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpord + llvm_name: VPORDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpopcntw + llvm_name: VPOPCNTWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntw + llvm_name: VPOPCNTWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntw + llvm_name: VPOPCNTWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntw + llvm_name: VPOPCNTWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntw + llvm_name: VPOPCNTWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntw + llvm_name: VPOPCNTWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntq + llvm_name: VPOPCNTQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntq + llvm_name: VPOPCNTQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntq + llvm_name: VPOPCNTQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntq + llvm_name: VPOPCNTQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntq + llvm_name: VPOPCNTQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntq + llvm_name: VPOPCNTQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntd + llvm_name: VPOPCNTDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntd + llvm_name: VPOPCNTDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntd + llvm_name: VPOPCNTDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntd + llvm_name: VPOPCNTDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntd + llvm_name: VPOPCNTDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntd + llvm_name: VPOPCNTDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntb + llvm_name: VPOPCNTBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntb + llvm_name: VPOPCNTBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntb + llvm_name: VPOPCNTBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntb + llvm_name: VPOPCNTBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntb + llvm_name: VPOPCNTBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpopcntb + llvm_name: VPOPCNTBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpmuludq + llvm_name: VPMULUDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmuludq + llvm_name: VPMULUDQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmuludq + llvm_name: VPMULUDQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmuludq + llvm_name: VPMULUDQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmuludq + llvm_name: VPMULUDQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmuludq + llvm_name: VPMULUDQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmultishiftqb + llvm_name: VPMULTISHIFTQBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmultishiftqb + llvm_name: VPMULTISHIFTQBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmultishiftqb + llvm_name: VPMULTISHIFTQBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmultishiftqb + llvm_name: VPMULTISHIFTQBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmultishiftqb + llvm_name: VPMULTISHIFTQBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmultishiftqb + llvm_name: VPMULTISHIFTQBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmullw + llvm_name: VPMULLWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmullw + llvm_name: VPMULLWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmullw + llvm_name: VPMULLWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmullw + llvm_name: VPMULLWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmullw + llvm_name: VPMULLWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmullw + llvm_name: VPMULLWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmullq + llvm_name: VPMULLQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmullq + llvm_name: VPMULLQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmullq + llvm_name: VPMULLQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmullq + llvm_name: VPMULLQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmullq + llvm_name: VPMULLQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmullq + llvm_name: VPMULLQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulld + llvm_name: VPMULLDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulld + llvm_name: VPMULLDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulld + llvm_name: VPMULLDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulld + llvm_name: VPMULLDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulld + llvm_name: VPMULLDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulld + llvm_name: VPMULLDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhw + llvm_name: VPMULHWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhw + llvm_name: VPMULHWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhw + llvm_name: VPMULHWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhw + llvm_name: VPMULHWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhw + llvm_name: VPMULHWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhw + llvm_name: VPMULHWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhuw + llvm_name: VPMULHUWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhuw + llvm_name: VPMULHUWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhuw + llvm_name: VPMULHUWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhuw + llvm_name: VPMULHUWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhuw + llvm_name: VPMULHUWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhuw + llvm_name: VPMULHUWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhrsw + llvm_name: VPMULHRSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhrsw + llvm_name: VPMULHRSWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhrsw + llvm_name: VPMULHRSWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhrsw + llvm_name: VPMULHRSWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhrsw + llvm_name: VPMULHRSWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmulhrsw + llvm_name: VPMULHRSWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmuldq + llvm_name: VPMULDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmuldq + llvm_name: VPMULDQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmuldq + llvm_name: VPMULDQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmuldq + llvm_name: VPMULDQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmuldq + llvm_name: VPMULDQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmuldq + llvm_name: VPMULDQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmovzxwq + llvm_name: VPMOVZXWQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxwq + llvm_name: VPMOVZXWQZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + mask: true + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxwq + llvm_name: VPMOVZXWQZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxwq + llvm_name: VPMOVZXWQZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxwq + llvm_name: VPMOVZXWQZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxwq + llvm_name: VPMOVZXWQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxwd + llvm_name: VPMOVZXWDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxwd + llvm_name: VPMOVZXWDZrrkz + operands: + - class: register + name: ymm + - class: register + name: zmm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxwd + llvm_name: VPMOVZXWDZrr + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxwd + llvm_name: VPMOVZXWDZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxwd + llvm_name: VPMOVZXWDZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxwd + llvm_name: VPMOVZXWDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxdq + llvm_name: VPMOVZXDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxdq + llvm_name: VPMOVZXDQZrrkz + operands: + - class: register + name: ymm + - class: register + name: zmm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxdq + llvm_name: VPMOVZXDQZrr + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxdq + llvm_name: VPMOVZXDQZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxdq + llvm_name: VPMOVZXDQZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxdq + llvm_name: VPMOVZXDQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbw + llvm_name: VPMOVZXBWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbw + llvm_name: VPMOVZXBWZrrkz + operands: + - class: register + name: ymm + - class: register + name: zmm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbw + llvm_name: VPMOVZXBWZrr + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbw + llvm_name: VPMOVZXBWZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbw + llvm_name: VPMOVZXBWZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbw + llvm_name: VPMOVZXBWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbq + llvm_name: VPMOVZXBQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbq + llvm_name: VPMOVZXBQZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + mask: true + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbq + llvm_name: VPMOVZXBQZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbq + llvm_name: VPMOVZXBQZ256rrk + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbq + llvm_name: VPMOVZXBQZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbq + llvm_name: VPMOVZXBQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbd + llvm_name: VPMOVZXBDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbd + llvm_name: VPMOVZXBDZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + mask: true + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbd + llvm_name: VPMOVZXBDZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbd + llvm_name: VPMOVZXBDZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbd + llvm_name: VPMOVZXBDZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovzxbd + llvm_name: VPMOVZXBDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovwb + llvm_name: VPMOVWBZrrkz + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovwb + llvm_name: VPMOVWBZrr + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovwb + llvm_name: VPMOVWBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovwb + llvm_name: VPMOVWBZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovwb + llvm_name: VPMOVWBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovwb + llvm_name: VPMOVWBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovw2m + llvm_name: VPMOVW2MZkr + operands: + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmovw2m + llvm_name: VPMOVW2MZ256kr + operands: + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmovw2m + llvm_name: VPMOVW2MZ128kr + operands: + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmovuswb + llvm_name: VPMOVUSWBZrrkz + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovuswb + llvm_name: VPMOVUSWBZrr + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovuswb + llvm_name: VPMOVUSWBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovuswb + llvm_name: VPMOVUSWBZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovuswb + llvm_name: VPMOVUSWBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovuswb + llvm_name: VPMOVUSWBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqw + llvm_name: VPMOVUSQWZrrkz + operands: + - class: register + name: zmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqw + llvm_name: VPMOVUSQWZrr + operands: + - class: register + name: zmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqw + llvm_name: VPMOVUSQWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqw + llvm_name: VPMOVUSQWZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqw + llvm_name: VPMOVUSQWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqw + llvm_name: VPMOVUSQWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqd + llvm_name: VPMOVUSQDZrrkz + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqd + llvm_name: VPMOVUSQDZrr + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqd + llvm_name: VPMOVUSQDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqd + llvm_name: VPMOVUSQDZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqd + llvm_name: VPMOVUSQDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqd + llvm_name: VPMOVUSQDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqb + llvm_name: VPMOVUSQBZrrkz + operands: + - class: register + name: zmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqb + llvm_name: VPMOVUSQBZrr + operands: + - class: register + name: zmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqb + llvm_name: VPMOVUSQBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqb + llvm_name: VPMOVUSQBZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqb + llvm_name: VPMOVUSQBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusqb + llvm_name: VPMOVUSQBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusdw + llvm_name: VPMOVUSDWZrrkz + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusdw + llvm_name: VPMOVUSDWZrr + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusdw + llvm_name: VPMOVUSDWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusdw + llvm_name: VPMOVUSDWZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusdw + llvm_name: VPMOVUSDWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusdw + llvm_name: VPMOVUSDWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusdb + llvm_name: VPMOVUSDBZrrkz + operands: + - class: register + name: zmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusdb + llvm_name: VPMOVUSDBZrr + operands: + - class: register + name: zmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusdb + llvm_name: VPMOVUSDBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusdb + llvm_name: VPMOVUSDBZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusdb + llvm_name: VPMOVUSDBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovusdb + llvm_name: VPMOVUSDBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxwq + llvm_name: VPMOVSXWQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxwq + llvm_name: VPMOVSXWQZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + mask: true + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxwq + llvm_name: VPMOVSXWQZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxwq + llvm_name: VPMOVSXWQZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxwq + llvm_name: VPMOVSXWQZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxwq + llvm_name: VPMOVSXWQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxwd + llvm_name: VPMOVSXWDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxwd + llvm_name: VPMOVSXWDZrrkz + operands: + - class: register + name: ymm + - class: register + name: zmm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxwd + llvm_name: VPMOVSXWDZrr + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxwd + llvm_name: VPMOVSXWDZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxwd + llvm_name: VPMOVSXWDZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxwd + llvm_name: VPMOVSXWDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxdq + llvm_name: VPMOVSXDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxdq + llvm_name: VPMOVSXDQZrrkz + operands: + - class: register + name: ymm + - class: register + name: zmm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxdq + llvm_name: VPMOVSXDQZrr + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxdq + llvm_name: VPMOVSXDQZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxdq + llvm_name: VPMOVSXDQZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxdq + llvm_name: VPMOVSXDQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbw + llvm_name: VPMOVSXBWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbw + llvm_name: VPMOVSXBWZrrkz + operands: + - class: register + name: ymm + - class: register + name: zmm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbw + llvm_name: VPMOVSXBWZrr + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbw + llvm_name: VPMOVSXBWZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbw + llvm_name: VPMOVSXBWZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbw + llvm_name: VPMOVSXBWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbq + llvm_name: VPMOVSXBQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbq + llvm_name: VPMOVSXBQZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + mask: true + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbq + llvm_name: VPMOVSXBQZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbq + llvm_name: VPMOVSXBQZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbq + llvm_name: VPMOVSXBQZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbq + llvm_name: VPMOVSXBQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbd + llvm_name: VPMOVSXBDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbd + llvm_name: VPMOVSXBDZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + mask: true + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbd + llvm_name: VPMOVSXBDZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbd + llvm_name: VPMOVSXBDZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbd + llvm_name: VPMOVSXBDZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsxbd + llvm_name: VPMOVSXBDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovswb + llvm_name: VPMOVSWBZrrkz + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovswb + llvm_name: VPMOVSWBZrr + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovswb + llvm_name: VPMOVSWBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovswb + llvm_name: VPMOVSWBZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovswb + llvm_name: VPMOVSWBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovswb + llvm_name: VPMOVSWBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqw + llvm_name: VPMOVSQWZrrkz + operands: + - class: register + name: zmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqw + llvm_name: VPMOVSQWZrr + operands: + - class: register + name: zmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqw + llvm_name: VPMOVSQWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqw + llvm_name: VPMOVSQWZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqw + llvm_name: VPMOVSQWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqw + llvm_name: VPMOVSQWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqd + llvm_name: VPMOVSQDZrrkz + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqd + llvm_name: VPMOVSQDZrr + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqd + llvm_name: VPMOVSQDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqd + llvm_name: VPMOVSQDZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqd + llvm_name: VPMOVSQDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqd + llvm_name: VPMOVSQDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqb + llvm_name: VPMOVSQBZrrkz + operands: + - class: register + name: zmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqb + llvm_name: VPMOVSQBZrr + operands: + - class: register + name: zmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqb + llvm_name: VPMOVSQBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqb + llvm_name: VPMOVSQBZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqb + llvm_name: VPMOVSQBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsqb + llvm_name: VPMOVSQBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsdw + llvm_name: VPMOVSDWZrrkz + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsdw + llvm_name: VPMOVSDWZrr + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsdw + llvm_name: VPMOVSDWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsdw + llvm_name: VPMOVSDWZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsdw + llvm_name: VPMOVSDWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsdw + llvm_name: VPMOVSDWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsdb + llvm_name: VPMOVSDBZrrkz + operands: + - class: register + name: zmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsdb + llvm_name: VPMOVSDBZrr + operands: + - class: register + name: zmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsdb + llvm_name: VPMOVSDBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsdb + llvm_name: VPMOVSDBZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsdb + llvm_name: VPMOVSDBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovsdb + llvm_name: VPMOVSDBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqw + llvm_name: VPMOVQWZrrkz + operands: + - class: register + name: zmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqw + llvm_name: VPMOVQWZrr + operands: + - class: register + name: zmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqw + llvm_name: VPMOVQWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqw + llvm_name: VPMOVQWZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqw + llvm_name: VPMOVQWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqw + llvm_name: VPMOVQWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqd + llvm_name: VPMOVQDZrrkz + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqd + llvm_name: VPMOVQDZrr + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqd + llvm_name: VPMOVQDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqd + llvm_name: VPMOVQDZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqd + llvm_name: VPMOVQDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqd + llvm_name: VPMOVQDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqb + llvm_name: VPMOVQBZrrkz + operands: + - class: register + name: zmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqb + llvm_name: VPMOVQBZrr + operands: + - class: register + name: zmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqb + llvm_name: VPMOVQBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqb + llvm_name: VPMOVQBZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqb + llvm_name: VPMOVQBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovqb + llvm_name: VPMOVQBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovq2m + llvm_name: VPMOVQ2MZkr + operands: + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmovq2m + llvm_name: VPMOVQ2MZ256kr + operands: + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmovq2m + llvm_name: VPMOVQ2MZ128kr + operands: + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmovmskb + llvm_name: VPMOVMSKBrr + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 6 + port_pressure: [[1, ['4', '5']]] + throughput: 0.5 + uops: ~ +- name: vpmovm2w + llvm_name: VPMOVM2WZrk + operands: + - class: register + name: k + - class: register + name: zmm + latency: 7 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmovm2w + llvm_name: VPMOVM2WZ256rk + operands: + - class: register + name: k + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmovm2w + llvm_name: VPMOVM2WZ128rk + operands: + - class: register + name: k + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmovm2q + llvm_name: VPMOVM2QZrk + operands: + - class: register + name: k + - class: register + name: zmm + latency: 7 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmovm2q + llvm_name: VPMOVM2QZ256rk + operands: + - class: register + name: k + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmovm2q + llvm_name: VPMOVM2QZ128rk + operands: + - class: register + name: k + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmovm2d + llvm_name: VPMOVM2DZrk + operands: + - class: register + name: k + - class: register + name: zmm + latency: 7 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmovm2d + llvm_name: VPMOVM2DZ256rk + operands: + - class: register + name: k + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmovm2d + llvm_name: VPMOVM2DZ128rk + operands: + - class: register + name: k + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmovm2b + llvm_name: VPMOVM2BZrk + operands: + - class: register + name: k + - class: register + name: zmm + latency: 7 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmovm2b + llvm_name: VPMOVM2BZ256rk + operands: + - class: register + name: k + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmovm2b + llvm_name: VPMOVM2BZ128rk + operands: + - class: register + name: k + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmovdw + llvm_name: VPMOVDWZrrkz + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovdw + llvm_name: VPMOVDWZrr + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovdw + llvm_name: VPMOVDWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovdw + llvm_name: VPMOVDWZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovdw + llvm_name: VPMOVDWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovdw + llvm_name: VPMOVDWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovdb + llvm_name: VPMOVDBZrrkz + operands: + - class: register + name: zmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovdb + llvm_name: VPMOVDBZrr + operands: + - class: register + name: zmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovdb + llvm_name: VPMOVDBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovdb + llvm_name: VPMOVDBZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovdb + llvm_name: VPMOVDBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovdb + llvm_name: VPMOVDBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpmovd2m + llvm_name: VPMOVD2MZkr + operands: + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmovd2m + llvm_name: VPMOVD2MZ256kr + operands: + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmovd2m + llvm_name: VPMOVD2MZ128kr + operands: + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmovb2m + llvm_name: VPMOVB2MZkr + operands: + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmovb2m + llvm_name: VPMOVB2MZ256kr + operands: + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmovb2m + llvm_name: VPMOVB2MZ128kr + operands: + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpminuw + llvm_name: VPMINUWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminuw + llvm_name: VPMINUWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminuw + llvm_name: VPMINUWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminuw + llvm_name: VPMINUWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminuw + llvm_name: VPMINUWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminuw + llvm_name: VPMINUWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminuq + llvm_name: VPMINUQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpminuq + llvm_name: VPMINUQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpminuq + llvm_name: VPMINUQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpminuq + llvm_name: VPMINUQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpminuq + llvm_name: VPMINUQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpminuq + llvm_name: VPMINUQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpminud + llvm_name: VPMINUDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminud + llvm_name: VPMINUDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminud + llvm_name: VPMINUDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminud + llvm_name: VPMINUDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminud + llvm_name: VPMINUDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminud + llvm_name: VPMINUDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminub + llvm_name: VPMINUBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminub + llvm_name: VPMINUBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminub + llvm_name: VPMINUBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminub + llvm_name: VPMINUBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminub + llvm_name: VPMINUBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminub + llvm_name: VPMINUBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsw + llvm_name: VPMINSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsw + llvm_name: VPMINSWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsw + llvm_name: VPMINSWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsw + llvm_name: VPMINSWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsw + llvm_name: VPMINSWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsw + llvm_name: VPMINSWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsq + llvm_name: VPMINSQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpminsq + llvm_name: VPMINSQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpminsq + llvm_name: VPMINSQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpminsq + llvm_name: VPMINSQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpminsq + llvm_name: VPMINSQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpminsq + llvm_name: VPMINSQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpminsd + llvm_name: VPMINSDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsd + llvm_name: VPMINSDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsd + llvm_name: VPMINSDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsd + llvm_name: VPMINSDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsd + llvm_name: VPMINSDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsd + llvm_name: VPMINSDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsb + llvm_name: VPMINSBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsb + llvm_name: VPMINSBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsb + llvm_name: VPMINSBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsb + llvm_name: VPMINSBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsb + llvm_name: VPMINSBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpminsb + llvm_name: VPMINSBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxuw + llvm_name: VPMAXUWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxuw + llvm_name: VPMAXUWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxuw + llvm_name: VPMAXUWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxuw + llvm_name: VPMAXUWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxuw + llvm_name: VPMAXUWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxuw + llvm_name: VPMAXUWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxuq + llvm_name: VPMAXUQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpmaxuq + llvm_name: VPMAXUQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpmaxuq + llvm_name: VPMAXUQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpmaxuq + llvm_name: VPMAXUQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpmaxuq + llvm_name: VPMAXUQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpmaxuq + llvm_name: VPMAXUQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpmaxud + llvm_name: VPMAXUDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxud + llvm_name: VPMAXUDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxud + llvm_name: VPMAXUDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxud + llvm_name: VPMAXUDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxud + llvm_name: VPMAXUDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxud + llvm_name: VPMAXUDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxub + llvm_name: VPMAXUBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxub + llvm_name: VPMAXUBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxub + llvm_name: VPMAXUBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxub + llvm_name: VPMAXUBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxub + llvm_name: VPMAXUBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxub + llvm_name: VPMAXUBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsw + llvm_name: VPMAXSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsw + llvm_name: VPMAXSWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsw + llvm_name: VPMAXSWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsw + llvm_name: VPMAXSWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsw + llvm_name: VPMAXSWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsw + llvm_name: VPMAXSWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsq + llvm_name: VPMAXSQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpmaxsq + llvm_name: VPMAXSQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpmaxsq + llvm_name: VPMAXSQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpmaxsq + llvm_name: VPMAXSQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpmaxsq + llvm_name: VPMAXSQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpmaxsq + llvm_name: VPMAXSQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpmaxsd + llvm_name: VPMAXSDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsd + llvm_name: VPMAXSDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsd + llvm_name: VPMAXSDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsd + llvm_name: VPMAXSDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsd + llvm_name: VPMAXSDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsd + llvm_name: VPMAXSDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsb + llvm_name: VPMAXSBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsb + llvm_name: VPMAXSBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsb + llvm_name: VPMAXSBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsb + llvm_name: VPMAXSBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsb + llvm_name: VPMAXSBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaxsb + llvm_name: VPMAXSBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpmaddwd + llvm_name: VPMADDWDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmaddwd + llvm_name: VPMADDWDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmaddwd + llvm_name: VPMADDWDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmaddwd + llvm_name: VPMADDWDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmaddwd + llvm_name: VPMADDWDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmaddwd + llvm_name: VPMADDWDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmaddubsw + llvm_name: VPMADDUBSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmaddubsw + llvm_name: VPMADDUBSWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmaddubsw + llvm_name: VPMADDUBSWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmaddubsw + llvm_name: VPMADDUBSWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmaddubsw + llvm_name: VPMADDUBSWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmaddubsw + llvm_name: VPMADDUBSWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmadd52luq + llvm_name: VPMADD52LUQZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmadd52luq + llvm_name: VPMADD52LUQZr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmadd52luq + llvm_name: VPMADD52LUQZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmadd52luq + llvm_name: VPMADD52LUQZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmadd52luq + llvm_name: VPMADD52LUQZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmadd52luq + llvm_name: VPMADD52LUQZ128r + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmadd52huq + llvm_name: VPMADD52HUQZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmadd52huq + llvm_name: VPMADD52HUQZr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmadd52huq + llvm_name: VPMADD52HUQZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmadd52huq + llvm_name: VPMADD52HUQZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmadd52huq + llvm_name: VPMADD52HUQZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpmadd52huq + llvm_name: VPMADD52HUQZ128r + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vplzcntq + llvm_name: VPLZCNTQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vplzcntq + llvm_name: VPLZCNTQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vplzcntq + llvm_name: VPLZCNTQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vplzcntq + llvm_name: VPLZCNTQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vplzcntq + llvm_name: VPLZCNTQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vplzcntq + llvm_name: VPLZCNTQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vplzcntd + llvm_name: VPLZCNTDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vplzcntd + llvm_name: VPLZCNTDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vplzcntd + llvm_name: VPLZCNTDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vplzcntd + llvm_name: VPLZCNTDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vplzcntd + llvm_name: VPLZCNTDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vplzcntd + llvm_name: VPLZCNTDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '03']] + throughput: 0.5 + uops: ~ +- name: vpinsrw + llvm_name: VPINSRWrri + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpinsrq + llvm_name: VPINSRQrri + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpinsrd + llvm_name: VPINSRDrri + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpinsrb + llvm_name: VPINSRBrri + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vphsubw + llvm_name: VPHSUBWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vphsubw + llvm_name: VPHSUBWYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vphsubsw + llvm_name: VPHSUBSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vphsubsw + llvm_name: VPHSUBSWYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vphsubd + llvm_name: VPHSUBDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vphsubd + llvm_name: VPHSUBDYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vphminposuw + llvm_name: VPHMINPOSUWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vphaddw + llvm_name: VPHADDWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vphaddw + llvm_name: VPHADDWYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vphaddsw + llvm_name: VPHADDSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vphaddsw + llvm_name: VPHADDSWYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vphaddd + llvm_name: VPHADDDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vphaddd + llvm_name: VPHADDDYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vpextrw + llvm_name: VPEXTRWrri_REV + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, ['4', '5']], [1, '13']] + throughput: 0.5 + uops: ~ +- name: vpextrq + llvm_name: VPEXTRQrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, ['4', '5']], [1, '13']] + throughput: 0.5 + uops: ~ +- name: vpextrd + llvm_name: VPEXTRDrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, ['4', '5']], [1, ['0', '1', '2', '3']]] + throughput: 0.75 + uops: ~ +- name: vpextrb + llvm_name: VPEXTRBrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, ['4', '5']], [1, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandw + llvm_name: VPEXPANDWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandw + llvm_name: VPEXPANDWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandw + llvm_name: VPEXPANDWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandw + llvm_name: VPEXPANDWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandw + llvm_name: VPEXPANDWZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandw + llvm_name: VPEXPANDWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandq + llvm_name: VPEXPANDQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandq + llvm_name: VPEXPANDQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandq + llvm_name: VPEXPANDQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandq + llvm_name: VPEXPANDQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandq + llvm_name: VPEXPANDQZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandq + llvm_name: VPEXPANDQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandd + llvm_name: VPEXPANDDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandd + llvm_name: VPEXPANDDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandd + llvm_name: VPEXPANDDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandd + llvm_name: VPEXPANDDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandd + llvm_name: VPEXPANDDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandd + llvm_name: VPEXPANDDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandb + llvm_name: VPEXPANDBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandb + llvm_name: VPEXPANDBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandb + llvm_name: VPEXPANDBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandb + llvm_name: VPEXPANDBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandb + llvm_name: VPEXPANDBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpexpandb + llvm_name: VPEXPANDBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpermw + llvm_name: VPERMWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermw + llvm_name: VPERMWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermw + llvm_name: VPERMWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermw + llvm_name: VPERMWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermw + llvm_name: VPERMWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermw + llvm_name: VPERMWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2w + llvm_name: VPERMT2WZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2w + llvm_name: VPERMT2WZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2w + llvm_name: VPERMT2WZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2w + llvm_name: VPERMT2WZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2w + llvm_name: VPERMT2WZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2w + llvm_name: VPERMT2WZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2q + llvm_name: VPERMT2QZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2q + llvm_name: VPERMT2QZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2q + llvm_name: VPERMT2QZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2q + llvm_name: VPERMT2QZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2q + llvm_name: VPERMT2QZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2q + llvm_name: VPERMT2QZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2ps + llvm_name: VPERMT2PSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2ps + llvm_name: VPERMT2PSZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2ps + llvm_name: VPERMT2PSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2ps + llvm_name: VPERMT2PSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2ps + llvm_name: VPERMT2PSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2ps + llvm_name: VPERMT2PSZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2pd + llvm_name: VPERMT2PDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2pd + llvm_name: VPERMT2PDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2pd + llvm_name: VPERMT2PDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2pd + llvm_name: VPERMT2PDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2pd + llvm_name: VPERMT2PDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2pd + llvm_name: VPERMT2PDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2d + llvm_name: VPERMT2DZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2d + llvm_name: VPERMT2DZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2d + llvm_name: VPERMT2DZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2d + llvm_name: VPERMT2DZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2d + llvm_name: VPERMT2DZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2d + llvm_name: VPERMT2DZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2b + llvm_name: VPERMT2BZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2b + llvm_name: VPERMT2BZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2b + llvm_name: VPERMT2BZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2b + llvm_name: VPERMT2BZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2b + llvm_name: VPERMT2BZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermt2b + llvm_name: VPERMT2BZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermq + llvm_name: VPERMQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermq + llvm_name: VPERMQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermq + llvm_name: VPERMQZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermq + llvm_name: VPERMQZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermq + llvm_name: VPERMQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermq + llvm_name: VPERMQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermq + llvm_name: VPERMQZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermq + llvm_name: VPERMQZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermps + llvm_name: VPERMPSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermps + llvm_name: VPERMPSZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermps + llvm_name: VPERMPSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermps + llvm_name: VPERMPSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermpd + llvm_name: VPERMPDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermpd + llvm_name: VPERMPDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermpd + llvm_name: VPERMPDZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermpd + llvm_name: VPERMPDZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermpd + llvm_name: VPERMPDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermpd + llvm_name: VPERMPDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermpd + llvm_name: VPERMPDZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermpd + llvm_name: VPERMPDZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermilps + llvm_name: VPERMILPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermilps + llvm_name: VPERMILPSZ128ri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpermilps + llvm_name: VPERMILPSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermilps + llvm_name: VPERMILPSZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermilps + llvm_name: VPERMILPSZrik + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpermilps + llvm_name: VPERMILPSZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpermilps + llvm_name: VPERMILPSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermilps + llvm_name: VPERMILPSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermilps + llvm_name: VPERMILPSZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpermilps + llvm_name: VPERMILPSZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpermilps + llvm_name: VPERMILPSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermilps + llvm_name: VPERMILPSZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpermilpd + llvm_name: VPERMILPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermilpd + llvm_name: VPERMILPDri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpermilpd + llvm_name: VPERMILPDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermilpd + llvm_name: VPERMILPDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermilpd + llvm_name: VPERMILPDZrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpermilpd + llvm_name: VPERMILPDZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpermilpd + llvm_name: VPERMILPDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermilpd + llvm_name: VPERMILPDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermilpd + llvm_name: VPERMILPDZ256rikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpermilpd + llvm_name: VPERMILPDZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpermilpd + llvm_name: VPERMILPDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermilpd + llvm_name: VPERMILPDZ128rikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpermi2w + llvm_name: VPERMI2WZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2w + llvm_name: VPERMI2WZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2w + llvm_name: VPERMI2WZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2w + llvm_name: VPERMI2WZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2w + llvm_name: VPERMI2WZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2w + llvm_name: VPERMI2WZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2q + llvm_name: VPERMI2QZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2q + llvm_name: VPERMI2QZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2q + llvm_name: VPERMI2QZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2q + llvm_name: VPERMI2QZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2q + llvm_name: VPERMI2QZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2q + llvm_name: VPERMI2QZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2ps + llvm_name: VPERMI2PSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2ps + llvm_name: VPERMI2PSZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2ps + llvm_name: VPERMI2PSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2ps + llvm_name: VPERMI2PSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2ps + llvm_name: VPERMI2PSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2ps + llvm_name: VPERMI2PSZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2pd + llvm_name: VPERMI2PDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2pd + llvm_name: VPERMI2PDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2pd + llvm_name: VPERMI2PDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2pd + llvm_name: VPERMI2PDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2pd + llvm_name: VPERMI2PDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2pd + llvm_name: VPERMI2PDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2d + llvm_name: VPERMI2DZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2d + llvm_name: VPERMI2DZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2d + llvm_name: VPERMI2DZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2d + llvm_name: VPERMI2DZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2d + llvm_name: VPERMI2DZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2d + llvm_name: VPERMI2DZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2b + llvm_name: VPERMI2BZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2b + llvm_name: VPERMI2BZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2b + llvm_name: VPERMI2BZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2b + llvm_name: VPERMI2BZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2b + llvm_name: VPERMI2BZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermi2b + llvm_name: VPERMI2BZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermd + llvm_name: VPERMDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermd + llvm_name: VPERMDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermd + llvm_name: VPERMDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermd + llvm_name: VPERMDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermb + llvm_name: VPERMBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermb + llvm_name: VPERMBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermb + llvm_name: VPERMBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermb + llvm_name: VPERMBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermb + llvm_name: VPERMBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpermb + llvm_name: VPERMBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vperm2i128 + llvm_name: VPERM2I128rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vperm2f128 + llvm_name: VPERM2F128rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpdpwssd + llvm_name: VPDPWSSDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpwssd + llvm_name: VPDPWSSDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpwssd + llvm_name: VPDPWSSDZr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpwssd + llvm_name: VPDPWSSDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpwssd + llvm_name: VPDPWSSDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpwssd + llvm_name: VPDPWSSDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpwssds + llvm_name: VPDPWSSDSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpwssds + llvm_name: VPDPWSSDSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpwssds + llvm_name: VPDPWSSDSZr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpwssds + llvm_name: VPDPWSSDSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpwssds + llvm_name: VPDPWSSDSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpwssds + llvm_name: VPDPWSSDSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpbusd + llvm_name: VPDPBUSDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpbusd + llvm_name: VPDPBUSDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpbusd + llvm_name: VPDPBUSDZr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpbusd + llvm_name: VPDPBUSDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpbusd + llvm_name: VPDPBUSDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpbusd + llvm_name: VPDPBUSDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpbusds + llvm_name: VPDPBUSDSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpbusds + llvm_name: VPDPBUSDSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpbusds + llvm_name: VPDPBUSDSZr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpbusds + llvm_name: VPDPBUSDSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpbusds + llvm_name: VPDPBUSDSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpdpbusds + llvm_name: VPDPBUSDSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpconflictq + llvm_name: VPCONFLICTQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 7 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpconflictq + llvm_name: VPCONFLICTQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 7 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpconflictq + llvm_name: VPCONFLICTQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 7 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpconflictq + llvm_name: VPCONFLICTQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 7 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpconflictq + llvm_name: VPCONFLICTQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpconflictq + llvm_name: VPCONFLICTQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpconflictd + llvm_name: VPCONFLICTDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 7 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpconflictd + llvm_name: VPCONFLICTDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 7 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpconflictd + llvm_name: VPCONFLICTDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 7 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpconflictd + llvm_name: VPCONFLICTDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 7 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpconflictd + llvm_name: VPCONFLICTDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpconflictd + llvm_name: VPCONFLICTDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcompressw + llvm_name: VPCOMPRESSWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressw + llvm_name: VPCOMPRESSWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressw + llvm_name: VPCOMPRESSWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressw + llvm_name: VPCOMPRESSWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressw + llvm_name: VPCOMPRESSWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressw + llvm_name: VPCOMPRESSWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1.9 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressq + llvm_name: VPCOMPRESSQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressq + llvm_name: VPCOMPRESSQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressq + llvm_name: VPCOMPRESSQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressq + llvm_name: VPCOMPRESSQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressq + llvm_name: VPCOMPRESSQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressq + llvm_name: VPCOMPRESSQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2.3 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressd + llvm_name: VPCOMPRESSDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressd + llvm_name: VPCOMPRESSDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressd + llvm_name: VPCOMPRESSDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressd + llvm_name: VPCOMPRESSDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressd + llvm_name: VPCOMPRESSDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressd + llvm_name: VPCOMPRESSDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressb + llvm_name: VPCOMPRESSBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressb + llvm_name: VPCOMPRESSBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressb + llvm_name: VPCOMPRESSBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressb + llvm_name: VPCOMPRESSBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressb + llvm_name: VPCOMPRESSBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcompressb + llvm_name: VPCOMPRESSBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vpcmpw + llvm_name: VPCMPWZrrik + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpw + llvm_name: VPCMPWZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpw + llvm_name: VPCMPWZ256rrik + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpw + llvm_name: VPCMPWZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpw + llvm_name: VPCMPWZ128rrik + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpw + llvm_name: VPCMPWZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpuw + llvm_name: VPCMPUWZrrik + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpuw + llvm_name: VPCMPUWZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpuw + llvm_name: VPCMPUWZ256rrik + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpuw + llvm_name: VPCMPUWZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpuw + llvm_name: VPCMPUWZ128rrik + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpuw + llvm_name: VPCMPUWZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpuq + llvm_name: VPCMPUQZrrik + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpuq + llvm_name: VPCMPUQZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpuq + llvm_name: VPCMPUQZ256rrik + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpuq + llvm_name: VPCMPUQZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpuq + llvm_name: VPCMPUQZ128rrik + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpuq + llvm_name: VPCMPUQZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpud + llvm_name: VPCMPUDZrrik + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpud + llvm_name: VPCMPUDZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpud + llvm_name: VPCMPUDZ256rrik + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpud + llvm_name: VPCMPUDZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpud + llvm_name: VPCMPUDZ128rrik + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpud + llvm_name: VPCMPUDZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpub + llvm_name: VPCMPUBZrrik + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpub + llvm_name: VPCMPUBZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpub + llvm_name: VPCMPUBZ256rrik + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpub + llvm_name: VPCMPUBZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpub + llvm_name: VPCMPUBZ128rrik + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpub + llvm_name: VPCMPUBZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpq + llvm_name: VPCMPQZrrik + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpq + llvm_name: VPCMPQZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpq + llvm_name: VPCMPQZ256rrik + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpq + llvm_name: VPCMPQZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpq + llvm_name: VPCMPQZ128rrik + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpq + llvm_name: VPCMPQZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtw + llvm_name: VPCMPGTWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpcmpgtw + llvm_name: VPCMPGTWZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtw + llvm_name: VPCMPGTWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtw + llvm_name: VPCMPGTWZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtw + llvm_name: VPCMPGTWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtw + llvm_name: VPCMPGTWZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtw + llvm_name: VPCMPGTWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtw + llvm_name: VPCMPGTWYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpcmpgtq + llvm_name: VPCMPGTQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtq + llvm_name: VPCMPGTQZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtq + llvm_name: VPCMPGTQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtq + llvm_name: VPCMPGTQZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtq + llvm_name: VPCMPGTQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtq + llvm_name: VPCMPGTQZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtq + llvm_name: VPCMPGTQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtq + llvm_name: VPCMPGTQYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtd + llvm_name: VPCMPGTDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpcmpgtd + llvm_name: VPCMPGTDZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtd + llvm_name: VPCMPGTDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtd + llvm_name: VPCMPGTDZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtd + llvm_name: VPCMPGTDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtd + llvm_name: VPCMPGTDZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtd + llvm_name: VPCMPGTDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtd + llvm_name: VPCMPGTDYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpcmpgtb + llvm_name: VPCMPGTBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpcmpgtb + llvm_name: VPCMPGTBZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtb + llvm_name: VPCMPGTBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtb + llvm_name: VPCMPGTBZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtb + llvm_name: VPCMPGTBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtb + llvm_name: VPCMPGTBZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtb + llvm_name: VPCMPGTBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpgtb + llvm_name: VPCMPGTBYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpcmpestri + llvm_name: VPCMPESTRIrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 17 + port_pressure: [[3, ['2']], [2, ['4', '5']]] + throughput: 4.0 + uops: ~ +- name: vpcmpeqw + llvm_name: VPCMPEQWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpcmpeqw + llvm_name: VPCMPEQWZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqw + llvm_name: VPCMPEQWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqw + llvm_name: VPCMPEQWZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqw + llvm_name: VPCMPEQWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqw + llvm_name: VPCMPEQWZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqw + llvm_name: VPCMPEQWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqw + llvm_name: VPCMPEQWYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpcmpeqq + llvm_name: VPCMPEQQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqq + llvm_name: VPCMPEQQZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqq + llvm_name: VPCMPEQQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqq + llvm_name: VPCMPEQQZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqq + llvm_name: VPCMPEQQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqq + llvm_name: VPCMPEQQZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqq + llvm_name: VPCMPEQQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqq + llvm_name: VPCMPEQQYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqd + llvm_name: VPCMPEQDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpcmpeqd + llvm_name: VPCMPEQDZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqd + llvm_name: VPCMPEQDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqd + llvm_name: VPCMPEQDZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqd + llvm_name: VPCMPEQDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqd + llvm_name: VPCMPEQDZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqd + llvm_name: VPCMPEQDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqd + llvm_name: VPCMPEQDYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpcmpeqb + llvm_name: VPCMPEQBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpcmpeqb + llvm_name: VPCMPEQBZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqb + llvm_name: VPCMPEQBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqb + llvm_name: VPCMPEQBZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqb + llvm_name: VPCMPEQBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqb + llvm_name: VPCMPEQBZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqb + llvm_name: VPCMPEQBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpeqb + llvm_name: VPCMPEQBYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpcmpd + llvm_name: VPCMPDZrrik + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpd + llvm_name: VPCMPDZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpd + llvm_name: VPCMPDZ256rrik + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpd + llvm_name: VPCMPDZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpd + llvm_name: VPCMPDZ128rrik + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpd + llvm_name: VPCMPDZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpb + llvm_name: VPCMPBZrrik + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpb + llvm_name: VPCMPBZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpb + llvm_name: VPCMPBZ256rrik + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpb + llvm_name: VPCMPBZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpb + llvm_name: VPCMPBZ128rrik + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpcmpb + llvm_name: VPCMPBZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpclmulqdq + llvm_name: VPCLMULQDQrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[4, ['0', '2']]] + throughput: 2.0 + uops: ~ +- name: vpclmulqdq + llvm_name: VPCLMULQDQZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[4, ['0', '2']]] + throughput: 2.0 + uops: ~ +- name: vpclmulqdq + llvm_name: VPCLMULQDQZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[4, ['0', '2']]] + throughput: 2.0 + uops: ~ +- name: vpbroadcastw + llvm_name: VPBROADCASTWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpbroadcastw + llvm_name: VPBROADCASTWrZrrk + operands: + - class: register + name: gpr + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpbroadcastw + llvm_name: VPBROADCASTWrZ256rrk + operands: + - class: register + name: gpr + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpbroadcastw + llvm_name: VPBROADCASTWrZ128rrkz + operands: + - class: register + name: gpr + - class: register + name: xmm + mask: true + latency: 8 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpbroadcastw + llvm_name: VPBROADCASTWrZ128rr + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 8 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpbroadcastw + llvm_name: VPBROADCASTWZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastw + llvm_name: VPBROADCASTWZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastw + llvm_name: VPBROADCASTWZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastw + llvm_name: VPBROADCASTWZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastw + llvm_name: VPBROADCASTWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastq + llvm_name: VPBROADCASTQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpbroadcastq + llvm_name: VPBROADCASTQrZrrk + operands: + - class: register + name: gpr + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpbroadcastq + llvm_name: VPBROADCASTQrZ256rrk + operands: + - class: register + name: gpr + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpbroadcastq + llvm_name: VPBROADCASTQrZ128rrkz + operands: + - class: register + name: gpr + - class: register + name: xmm + mask: true + latency: 8 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpbroadcastq + llvm_name: VPBROADCASTQrZ128rr + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 8 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpbroadcastq + llvm_name: VPBROADCASTQZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastq + llvm_name: VPBROADCASTQZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastq + llvm_name: VPBROADCASTQZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastq + llvm_name: VPBROADCASTQZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastq + llvm_name: VPBROADCASTQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastmw2d + llvm_name: VPBROADCASTMW2DZrr + operands: + - class: register + name: k + - class: register + name: zmm + latency: 7 + port_pressure: [[1, ['0', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastmw2d + llvm_name: VPBROADCASTMW2DZ256rr + operands: + - class: register + name: k + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['0', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastmw2d + llvm_name: VPBROADCASTMW2DZ128rr + operands: + - class: register + name: k + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['0', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastmb2q + llvm_name: VPBROADCASTMB2QZrr + operands: + - class: register + name: k + - class: register + name: zmm + latency: 7 + port_pressure: [[1, ['0', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastmb2q + llvm_name: VPBROADCASTMB2QZ256rr + operands: + - class: register + name: k + - class: register + name: ymm + latency: 5 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpbroadcastmb2q + llvm_name: VPBROADCASTMB2QZ128rr + operands: + - class: register + name: k + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vpbroadcastd + llvm_name: VPBROADCASTDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpbroadcastd + llvm_name: VPBROADCASTDrZrrk + operands: + - class: register + name: gpr + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpbroadcastd + llvm_name: VPBROADCASTDrZ256rrk + operands: + - class: register + name: gpr + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpbroadcastd + llvm_name: VPBROADCASTDrZ128rrkz + operands: + - class: register + name: gpr + - class: register + name: xmm + mask: true + latency: 8 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpbroadcastd + llvm_name: VPBROADCASTDrZ128rr + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 8 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpbroadcastd + llvm_name: VPBROADCASTDZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastd + llvm_name: VPBROADCASTDZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastd + llvm_name: VPBROADCASTDZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastd + llvm_name: VPBROADCASTDZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastd + llvm_name: VPBROADCASTDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastb + llvm_name: VPBROADCASTBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpbroadcastb + llvm_name: VPBROADCASTBrZrrk + operands: + - class: register + name: gpr + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpbroadcastb + llvm_name: VPBROADCASTBrZ256rrk + operands: + - class: register + name: gpr + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpbroadcastb + llvm_name: VPBROADCASTBrZ128rrkz + operands: + - class: register + name: gpr + - class: register + name: xmm + mask: true + latency: 8 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpbroadcastb + llvm_name: VPBROADCASTBrZ128rr + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 8 + port_pressure: [[1, ['2']]] + throughput: 1.0 + uops: ~ +- name: vpbroadcastb + llvm_name: VPBROADCASTBZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastb + llvm_name: VPBROADCASTBZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastb + llvm_name: VPBROADCASTBZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastb + llvm_name: VPBROADCASTBZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpbroadcastb + llvm_name: VPBROADCASTBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpblendw + llvm_name: VPBLENDWrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendw + llvm_name: VPBLENDWYrri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendvb + llvm_name: VPBLENDVBrrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpblendvb + llvm_name: VPBLENDVBYrrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpblendmw + llvm_name: VPBLENDMWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmw + llvm_name: VPBLENDMWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmw + llvm_name: VPBLENDMWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmw + llvm_name: VPBLENDMWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmw + llvm_name: VPBLENDMWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmw + llvm_name: VPBLENDMWZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmq + llvm_name: VPBLENDMQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmq + llvm_name: VPBLENDMQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmq + llvm_name: VPBLENDMQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmq + llvm_name: VPBLENDMQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmq + llvm_name: VPBLENDMQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmq + llvm_name: VPBLENDMQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmd + llvm_name: VPBLENDMDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmd + llvm_name: VPBLENDMDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmd + llvm_name: VPBLENDMDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmd + llvm_name: VPBLENDMDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmd + llvm_name: VPBLENDMDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmd + llvm_name: VPBLENDMDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmb + llvm_name: VPBLENDMBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmb + llvm_name: VPBLENDMBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmb + llvm_name: VPBLENDMBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmb + llvm_name: VPBLENDMBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmb + llvm_name: VPBLENDMBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendmb + llvm_name: VPBLENDMBZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendd + llvm_name: VPBLENDDrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpblendd + llvm_name: VPBLENDDYrri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpavgw + llvm_name: VPAVGWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpavgw + llvm_name: VPAVGWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpavgw + llvm_name: VPAVGWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpavgw + llvm_name: VPAVGWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpavgw + llvm_name: VPAVGWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpavgw + llvm_name: VPAVGWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpavgb + llvm_name: VPAVGBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpavgb + llvm_name: VPAVGBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpavgb + llvm_name: VPAVGBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpavgb + llvm_name: VPAVGBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpavgb + llvm_name: VPAVGBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpavgb + llvm_name: VPAVGBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpand + llvm_name: VPANDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpand + llvm_name: VPANDYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandq + llvm_name: VPANDQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandq + llvm_name: VPANDQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandq + llvm_name: VPANDQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandq + llvm_name: VPANDQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandq + llvm_name: VPANDQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandq + llvm_name: VPANDQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandn + llvm_name: VPANDNrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandn + llvm_name: VPANDNYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandnq + llvm_name: VPANDNQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandnq + llvm_name: VPANDNQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandnq + llvm_name: VPANDNQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandnq + llvm_name: VPANDNQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandnq + llvm_name: VPANDNQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandnq + llvm_name: VPANDNQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandnd + llvm_name: VPANDNDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandnd + llvm_name: VPANDNDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandnd + llvm_name: VPANDNDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandnd + llvm_name: VPANDNDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandnd + llvm_name: VPANDNDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandnd + llvm_name: VPANDNDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandd + llvm_name: VPANDDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandd + llvm_name: VPANDDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandd + llvm_name: VPANDDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandd + llvm_name: VPANDDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandd + llvm_name: VPANDDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpandd + llvm_name: VPANDDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpalignr + llvm_name: VPALIGNRrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpalignr + llvm_name: VPALIGNRZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpalignr + llvm_name: VPALIGNRZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpalignr + llvm_name: VPALIGNRZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpalignr + llvm_name: VPALIGNRZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpalignr + llvm_name: VPALIGNRZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpaddw + llvm_name: VPADDWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddw + llvm_name: VPADDWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddw + llvm_name: VPADDWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddw + llvm_name: VPADDWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddw + llvm_name: VPADDWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddw + llvm_name: VPADDWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddusw + llvm_name: VPADDUSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddusw + llvm_name: VPADDUSWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddusw + llvm_name: VPADDUSWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddusw + llvm_name: VPADDUSWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddusw + llvm_name: VPADDUSWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddusw + llvm_name: VPADDUSWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddusb + llvm_name: VPADDUSBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddusb + llvm_name: VPADDUSBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddusb + llvm_name: VPADDUSBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddusb + llvm_name: VPADDUSBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddusb + llvm_name: VPADDUSBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddusb + llvm_name: VPADDUSBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddsw + llvm_name: VPADDSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddsw + llvm_name: VPADDSWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddsw + llvm_name: VPADDSWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddsw + llvm_name: VPADDSWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddsw + llvm_name: VPADDSWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddsw + llvm_name: VPADDSWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddsb + llvm_name: VPADDSBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddsb + llvm_name: VPADDSBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddsb + llvm_name: VPADDSBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddsb + llvm_name: VPADDSBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddsb + llvm_name: VPADDSBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddsb + llvm_name: VPADDSBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpaddq + llvm_name: VPADDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddq + llvm_name: VPADDQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddq + llvm_name: VPADDQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddq + llvm_name: VPADDQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddq + llvm_name: VPADDQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddq + llvm_name: VPADDQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddd + llvm_name: VPADDDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddd + llvm_name: VPADDDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddd + llvm_name: VPADDDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddd + llvm_name: VPADDDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddd + llvm_name: VPADDDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddd + llvm_name: VPADDDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddb + llvm_name: VPADDBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddb + llvm_name: VPADDBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddb + llvm_name: VPADDBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddb + llvm_name: VPADDBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddb + llvm_name: VPADDBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpaddb + llvm_name: VPADDBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vpackuswb + llvm_name: VPACKUSWBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackuswb + llvm_name: VPACKUSWBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackuswb + llvm_name: VPACKUSWBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackuswb + llvm_name: VPACKUSWBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackuswb + llvm_name: VPACKUSWBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackuswb + llvm_name: VPACKUSWBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackusdw + llvm_name: VPACKUSDWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackusdw + llvm_name: VPACKUSDWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackusdw + llvm_name: VPACKUSDWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackusdw + llvm_name: VPACKUSDWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackusdw + llvm_name: VPACKUSDWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackusdw + llvm_name: VPACKUSDWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpacksswb + llvm_name: VPACKSSWBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpacksswb + llvm_name: VPACKSSWBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpacksswb + llvm_name: VPACKSSWBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpacksswb + llvm_name: VPACKSSWBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpacksswb + llvm_name: VPACKSSWBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpacksswb + llvm_name: VPACKSSWBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackssdw + llvm_name: VPACKSSDWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackssdw + llvm_name: VPACKSSDWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackssdw + llvm_name: VPACKSSDWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackssdw + llvm_name: VPACKSSDWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackssdw + llvm_name: VPACKSSDWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpackssdw + llvm_name: VPACKSSDWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vpabsw + llvm_name: VPABSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsw + llvm_name: VPABSWZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsw + llvm_name: VPABSWZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsw + llvm_name: VPABSWZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsw + llvm_name: VPABSWZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsw + llvm_name: VPABSWZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsq + llvm_name: VPABSQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsq + llvm_name: VPABSQZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsq + llvm_name: VPABSQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsq + llvm_name: VPABSQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsq + llvm_name: VPABSQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsq + llvm_name: VPABSQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsd + llvm_name: VPABSDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsd + llvm_name: VPABSDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsd + llvm_name: VPABSDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsd + llvm_name: VPABSDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsd + llvm_name: VPABSDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsd + llvm_name: VPABSDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsb + llvm_name: VPABSBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsb + llvm_name: VPABSBZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsb + llvm_name: VPABSBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsb + llvm_name: VPABSBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsb + llvm_name: VPABSBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vpabsb + llvm_name: VPABSBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: vorps + llvm_name: VORPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vorps + llvm_name: VORPSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vorps + llvm_name: VORPSZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vorps + llvm_name: VORPSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vorps + llvm_name: VORPSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vorps + llvm_name: VORPSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vorpd + llvm_name: VORPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vorpd + llvm_name: VORPDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vorpd + llvm_name: VORPDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vorpd + llvm_name: VORPDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vorpd + llvm_name: VORPDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vorpd + llvm_name: VORPDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmulss + llvm_name: VMULSSrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vmulss + llvm_name: VMULSSZrrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vmulsd + llvm_name: VMULSDrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vmulsd + llvm_name: VMULSDZrrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vmulps + llvm_name: VMULPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vmulps + llvm_name: VMULPSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vmulps + llvm_name: VMULPSZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vmulps + llvm_name: VMULPSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vmulps + llvm_name: VMULPSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vmulps + llvm_name: VMULPSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vmulpd + llvm_name: VMULPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vmulpd + llvm_name: VMULPDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vmulpd + llvm_name: VMULPDZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vmulpd + llvm_name: VMULPDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vmulpd + llvm_name: VMULPDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vmulpd + llvm_name: VMULPDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vmpsadbw + llvm_name: VMPSADBWrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[2, ['2']], [1, ['0']], [1, ['1']]] + throughput: 4.0 + uops: ~ +- name: vmpsadbw + llvm_name: VMPSADBWZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[2, ['2']], [1, ['0']], [1, ['1']]] + throughput: 4.0 + uops: ~ +- name: vmovq + llvm_name: VMOVZPQILo2PQIrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovups + llvm_name: VMOVUPSZrrkz_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovups + llvm_name: VMOVUPSZrr_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovups + llvm_name: VMOVUPSZ256rrkz_REV + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovups + llvm_name: VMOVUPSZ128rrkz_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovupd + llvm_name: VMOVUPDZrrkz_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovupd + llvm_name: VMOVUPDZrr_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovupd + llvm_name: VMOVUPDZ256rrkz_REV + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovupd + llvm_name: VMOVUPDZ128rrkz_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovss + llvm_name: VMOVSSrr_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovss + llvm_name: VMOVSSZrrkz_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovd + llvm_name: VMOVSS2DIZrr + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 6 + port_pressure: [[1, ['4', '5']]] + throughput: 0.5 + uops: ~ +- name: vmovsldup + llvm_name: VMOVSLDUPrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovsldup + llvm_name: VMOVSLDUPZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovsldup + llvm_name: VMOVSLDUPZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovsldup + llvm_name: VMOVSLDUPZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovsldup + llvm_name: VMOVSLDUPZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovsldup + llvm_name: VMOVSLDUPZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovshdup + llvm_name: VMOVSHDUPrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovshdup + llvm_name: VMOVSHDUPZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovshdup + llvm_name: VMOVSHDUPZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovshdup + llvm_name: VMOVSHDUPZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovshdup + llvm_name: VMOVSHDUPZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovshdup + llvm_name: VMOVSHDUPZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovq + llvm_name: VMOVSDto64rr + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 6 + port_pressure: [[1, ['4', '5']]] + throughput: 0.5 + uops: ~ +- name: vmovsd + llvm_name: VMOVSDrr_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovsd + llvm_name: VMOVSDZrrkz_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovmskps + llvm_name: VMOVMSKPSrr + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 6 + port_pressure: [[1, ['4', '5']]] + throughput: 0.5 + uops: ~ +- name: vmovmskpd + llvm_name: VMOVMSKPDrr + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 6 + port_pressure: [[1, ['4', '5']]] + throughput: 0.5 + uops: ~ +- name: vmovlhps + llvm_name: VMOVLHPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovhlps + llvm_name: VMOVHLPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqu8 + llvm_name: VMOVDQU8Zrrkz_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqu8 + llvm_name: VMOVDQU8Zrr_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqu8 + llvm_name: VMOVDQU8Z256rrkz_REV + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqu8 + llvm_name: VMOVDQU8Z256rr_REV + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqu8 + llvm_name: VMOVDQU8Z128rrkz_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqu8 + llvm_name: VMOVDQU8Z128rr_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqu64 + llvm_name: VMOVDQU64Zrrkz_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqu64 + llvm_name: VMOVDQU64Zrr_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqu64 + llvm_name: VMOVDQU64Z256rrkz_REV + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqu64 + llvm_name: VMOVDQU64Z256rr_REV + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqu64 + llvm_name: VMOVDQU64Z128rrkz_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqu64 + llvm_name: VMOVDQU64Z128rr_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqu32 + llvm_name: VMOVDQU32Zrrkz_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqu32 + llvm_name: VMOVDQU32Zrr_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqu32 + llvm_name: VMOVDQU32Z256rrkz_REV + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqu32 + llvm_name: VMOVDQU32Z256rr_REV + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqu32 + llvm_name: VMOVDQU32Z128rrkz_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqu32 + llvm_name: VMOVDQU32Z128rr_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqu16 + llvm_name: VMOVDQU16Zrrkz_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqu16 + llvm_name: VMOVDQU16Zrr_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqu16 + llvm_name: VMOVDQU16Z256rrkz_REV + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqu16 + llvm_name: VMOVDQU16Z256rr_REV + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqu16 + llvm_name: VMOVDQU16Z128rrkz_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqu16 + llvm_name: VMOVDQU16Z128rr_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqa64 + llvm_name: VMOVDQA64Zrrkz_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqa64 + llvm_name: VMOVDQA64Zrr_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqa64 + llvm_name: VMOVDQA64Z256rrkz_REV + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqa64 + llvm_name: VMOVDQA64Z256rr_REV + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqa64 + llvm_name: VMOVDQA64Z128rrkz_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqa64 + llvm_name: VMOVDQA64Z128rr_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqa32 + llvm_name: VMOVDQA32Zrrkz_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqa32 + llvm_name: VMOVDQA32Zrr_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqa32 + llvm_name: VMOVDQA32Z256rrkz_REV + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqa32 + llvm_name: VMOVDQA32Z256rr_REV + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqa32 + llvm_name: VMOVDQA32Z128rrkz_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovdqa32 + llvm_name: VMOVDQA32Z128rr_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovdqa32 + llvm_name: VMOVDQA32Z128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovd + llvm_name: VMOVDI2SSrr + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 6 + port_pressure: [[2, ['4', '5']]] + throughput: 1.0 + uops: ~ +- name: vmovddup + llvm_name: VMOVDDUPrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovddup + llvm_name: VMOVDDUPZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vmovddup + llvm_name: VMOVDDUPZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vmovddup + llvm_name: VMOVDDUPZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vmovddup + llvm_name: VMOVDDUPZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovddup + llvm_name: VMOVDDUPZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vmovaps + llvm_name: VMOVAPSZrrkz_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovaps + llvm_name: VMOVAPSZrr_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovaps + llvm_name: VMOVAPSZ256rrkz_REV + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovaps + llvm_name: VMOVAPSZ128rrkz_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovapd + llvm_name: VMOVAPDZrrkz_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovapd + llvm_name: VMOVAPDZrr_REV + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 0.2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: vmovapd + llvm_name: VMOVAPDZ256rrkz_REV + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovapd + llvm_name: VMOVAPDZ128rrkz_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vmovq + llvm_name: VMOV64toSDrr + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 6 + port_pressure: [[2, ['4', '5']]] + throughput: 1.0 + uops: ~ +- name: vminss + llvm_name: VMINSSrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vminss + llvm_name: VMINSSZrrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vminsd + llvm_name: VMINSDrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vminsd + llvm_name: VMINSDZrrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vminps + llvm_name: VMINPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vminps + llvm_name: VMINPSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vminps + llvm_name: VMINPSZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vminps + llvm_name: VMINPSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vminps + llvm_name: VMINPSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vminps + llvm_name: VMINPSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vminpd + llvm_name: VMINPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vminpd + llvm_name: VMINPDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vminpd + llvm_name: VMINPDZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vminpd + llvm_name: VMINPDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vminpd + llvm_name: VMINPDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vminpd + llvm_name: VMINPDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vmaxss + llvm_name: VMAXSSrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vmaxss + llvm_name: VMAXSSZrrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vmaxsd + llvm_name: VMAXSDrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vmaxsd + llvm_name: VMAXSDZrrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vmaxps + llvm_name: VMAXPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vmaxps + llvm_name: VMAXPSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vmaxps + llvm_name: VMAXPSZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vmaxps + llvm_name: VMAXPSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vmaxps + llvm_name: VMAXPSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vmaxps + llvm_name: VMAXPSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vmaxpd + llvm_name: VMAXPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vmaxpd + llvm_name: VMAXPDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vmaxpd + llvm_name: VMAXPDZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vmaxpd + llvm_name: VMAXPDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vmaxpd + llvm_name: VMAXPDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vmaxpd + llvm_name: VMAXPDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vinsertps + llvm_name: VINSERTPSrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vinserti64x4 + llvm_name: VINSERTI64X4Zrrik + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinserti64x4 + llvm_name: VINSERTI64X4Zrri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinserti64x2 + llvm_name: VINSERTI64X2Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinserti64x2 + llvm_name: VINSERTI64X2Zrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinserti64x2 + llvm_name: VINSERTI64X2Z256rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinserti64x2 + llvm_name: VINSERTI64X2Z256rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinserti32x8 + llvm_name: VINSERTI32X8Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinserti32x8 + llvm_name: VINSERTI32X8Zrri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinserti32x4 + llvm_name: VINSERTI32X4Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinserti32x4 + llvm_name: VINSERTI32X4Zrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinserti32x4 + llvm_name: VINSERTI32X4Z256rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinserti32x4 + llvm_name: VINSERTI32X4Z256rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinserti128 + llvm_name: VINSERTI128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinsertf64x4 + llvm_name: VINSERTF64X4Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinsertf64x4 + llvm_name: VINSERTF64X4Zrri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinsertf64x2 + llvm_name: VINSERTF64X2Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinsertf64x2 + llvm_name: VINSERTF64X2Zrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinsertf64x2 + llvm_name: VINSERTF64X2Z256rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinsertf64x2 + llvm_name: VINSERTF64X2Z256rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinsertf32x8 + llvm_name: VINSERTF32X8Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinsertf32x8 + llvm_name: VINSERTF32X8Zrri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinsertf32x4 + llvm_name: VINSERTF32X4Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinsertf32x4 + llvm_name: VINSERTF32X4Zrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinsertf32x4 + llvm_name: VINSERTF32X4Z256rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinsertf32x4 + llvm_name: VINSERTF32X4Z256rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vinsertf128 + llvm_name: VINSERTF128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vhsubps + llvm_name: VHSUBPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vhsubps + llvm_name: VHSUBPSYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vhsubpd + llvm_name: VHSUBPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vhsubpd + llvm_name: VHSUBPDYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vhaddps + llvm_name: VHADDPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vhaddps + llvm_name: VHADDPSYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vhaddpd + llvm_name: VHADDPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vhaddpd + llvm_name: VHADDPDYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: vgf2p8mulb + llvm_name: VGF2P8MULBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8mulb + llvm_name: VGF2P8MULBZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8mulb + llvm_name: VGF2P8MULBZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8mulb + llvm_name: VGF2P8MULBZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8mulb + llvm_name: VGF2P8MULBZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8mulb + llvm_name: VGF2P8MULBZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8affineqb + llvm_name: VGF2P8AFFINEQBrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8affineqb + llvm_name: VGF2P8AFFINEQBZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8affineqb + llvm_name: VGF2P8AFFINEQBZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8affineqb + llvm_name: VGF2P8AFFINEQBZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8affineqb + llvm_name: VGF2P8AFFINEQBZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8affineqb + llvm_name: VGF2P8AFFINEQBZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8affineinvqb + llvm_name: VGF2P8AFFINEINVQBrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8affineinvqb + llvm_name: VGF2P8AFFINEINVQBZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8affineinvqb + llvm_name: VGF2P8AFFINEINVQBZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8affineinvqb + llvm_name: VGF2P8AFFINEINVQBZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8affineinvqb + llvm_name: VGF2P8AFFINEINVQBZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgf2p8affineinvqb + llvm_name: VGF2P8AFFINEINVQBZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vgetmantss + llvm_name: VGETMANTSSZrrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetmantss + llvm_name: VGETMANTSSZrrib + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetmantsd + llvm_name: VGETMANTSDZrrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetmantsd + llvm_name: VGETMANTSDZrrib + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetmantps + llvm_name: VGETMANTPSZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetmantps + llvm_name: VGETMANTPSZrrib + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetmantps + llvm_name: VGETMANTPSZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetmantps + llvm_name: VGETMANTPSZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetmantps + llvm_name: VGETMANTPSZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetmantps + llvm_name: VGETMANTPSZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetmantpd + llvm_name: VGETMANTPDZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetmantpd + llvm_name: VGETMANTPDZrrib + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetmantpd + llvm_name: VGETMANTPDZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetmantpd + llvm_name: VGETMANTPDZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetmantpd + llvm_name: VGETMANTPDZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetmantpd + llvm_name: VGETMANTPDZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetexpss + llvm_name: VGETEXPSSZrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetexpss + llvm_name: VGETEXPSSZrb + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetexpsd + llvm_name: VGETEXPSDZrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetexpsd + llvm_name: VGETEXPSDZrb + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetexpps + llvm_name: VGETEXPPSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetexpps + llvm_name: VGETEXPPSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetexpps + llvm_name: VGETEXPPSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetexpps + llvm_name: VGETEXPPSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetexpps + llvm_name: VGETEXPPSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetexpps + llvm_name: VGETEXPPSZ128r + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetexppd + llvm_name: VGETEXPPDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetexppd + llvm_name: VGETEXPPDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetexppd + llvm_name: VGETEXPPDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetexppd + llvm_name: VGETEXPPDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetexppd + llvm_name: VGETEXPPDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vgetexppd + llvm_name: VGETEXPPDZ128r + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vfpclassps + llvm_name: VFPCLASSPSZrik + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vfpclassps + llvm_name: VFPCLASSPSZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vfpclassps + llvm_name: VFPCLASSPSZ256rik + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vfpclassps + llvm_name: VFPCLASSPSZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vfpclassps + llvm_name: VFPCLASSPSZ128rik + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vfpclassps + llvm_name: VFPCLASSPSZ128ri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vfpclasspd + llvm_name: VFPCLASSPDZrik + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vfpclasspd + llvm_name: VFPCLASSPDZri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vfpclasspd + llvm_name: VFPCLASSPDZ256rik + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vfpclasspd + llvm_name: VFPCLASSPDZ256ri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vfpclasspd + llvm_name: VFPCLASSPDZ128rik + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vfpclasspd + llvm_name: VFPCLASSPDZ128ri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vfnmsub231ss + llvm_name: VFNMSUB231SSr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub231ss + llvm_name: VFNMSUB231SSZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub231sd + llvm_name: VFNMSUB231SDr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub231sd + llvm_name: VFNMSUB231SDZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub231ps + llvm_name: VFNMSUB231PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub231ps + llvm_name: VFNMSUB231PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub231ps + llvm_name: VFNMSUB231PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub231ps + llvm_name: VFNMSUB231PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub231ps + llvm_name: VFNMSUB231PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub231ps + llvm_name: VFNMSUB231PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub231pd + llvm_name: VFNMSUB231PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub231pd + llvm_name: VFNMSUB231PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub231pd + llvm_name: VFNMSUB231PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub231pd + llvm_name: VFNMSUB231PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub231pd + llvm_name: VFNMSUB231PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub231pd + llvm_name: VFNMSUB231PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub213ss + llvm_name: VFNMSUB213SSr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub213ss + llvm_name: VFNMSUB213SSZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub213sd + llvm_name: VFNMSUB213SDr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub213sd + llvm_name: VFNMSUB213SDZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub213ps + llvm_name: VFNMSUB213PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub213ps + llvm_name: VFNMSUB213PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub213ps + llvm_name: VFNMSUB213PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub213ps + llvm_name: VFNMSUB213PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub213ps + llvm_name: VFNMSUB213PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub213ps + llvm_name: VFNMSUB213PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub213pd + llvm_name: VFNMSUB213PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub213pd + llvm_name: VFNMSUB213PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub213pd + llvm_name: VFNMSUB213PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub213pd + llvm_name: VFNMSUB213PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub213pd + llvm_name: VFNMSUB213PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub213pd + llvm_name: VFNMSUB213PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub132ss + llvm_name: VFNMSUB132SSr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub132ss + llvm_name: VFNMSUB132SSZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub132sd + llvm_name: VFNMSUB132SDr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub132sd + llvm_name: VFNMSUB132SDZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub132ps + llvm_name: VFNMSUB132PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub132ps + llvm_name: VFNMSUB132PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub132ps + llvm_name: VFNMSUB132PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub132ps + llvm_name: VFNMSUB132PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub132ps + llvm_name: VFNMSUB132PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub132ps + llvm_name: VFNMSUB132PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub132pd + llvm_name: VFNMSUB132PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub132pd + llvm_name: VFNMSUB132PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub132pd + llvm_name: VFNMSUB132PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub132pd + llvm_name: VFNMSUB132PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub132pd + llvm_name: VFNMSUB132PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmsub132pd + llvm_name: VFNMSUB132PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd231ss + llvm_name: VFNMADD231SSr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd231ss + llvm_name: VFNMADD231SSZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd231sd + llvm_name: VFNMADD231SDr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd231sd + llvm_name: VFNMADD231SDZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd231ps + llvm_name: VFNMADD231PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd231ps + llvm_name: VFNMADD231PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd231ps + llvm_name: VFNMADD231PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd231ps + llvm_name: VFNMADD231PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd231ps + llvm_name: VFNMADD231PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd231ps + llvm_name: VFNMADD231PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd231pd + llvm_name: VFNMADD231PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd231pd + llvm_name: VFNMADD231PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd231pd + llvm_name: VFNMADD231PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd231pd + llvm_name: VFNMADD231PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd231pd + llvm_name: VFNMADD231PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd231pd + llvm_name: VFNMADD231PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd213ss + llvm_name: VFNMADD213SSr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd213ss + llvm_name: VFNMADD213SSZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd213sd + llvm_name: VFNMADD213SDr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd213sd + llvm_name: VFNMADD213SDZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd213ps + llvm_name: VFNMADD213PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd213ps + llvm_name: VFNMADD213PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd213ps + llvm_name: VFNMADD213PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd213ps + llvm_name: VFNMADD213PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd213ps + llvm_name: VFNMADD213PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd213ps + llvm_name: VFNMADD213PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd213pd + llvm_name: VFNMADD213PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd213pd + llvm_name: VFNMADD213PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd213pd + llvm_name: VFNMADD213PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd213pd + llvm_name: VFNMADD213PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd213pd + llvm_name: VFNMADD213PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd213pd + llvm_name: VFNMADD213PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd132ss + llvm_name: VFNMADD132SSr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd132ss + llvm_name: VFNMADD132SSZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd132sd + llvm_name: VFNMADD132SDr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd132sd + llvm_name: VFNMADD132SDZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd132ps + llvm_name: VFNMADD132PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd132ps + llvm_name: VFNMADD132PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd132ps + llvm_name: VFNMADD132PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd132ps + llvm_name: VFNMADD132PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd132ps + llvm_name: VFNMADD132PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd132ps + llvm_name: VFNMADD132PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd132pd + llvm_name: VFNMADD132PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd132pd + llvm_name: VFNMADD132PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd132pd + llvm_name: VFNMADD132PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd132pd + llvm_name: VFNMADD132PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd132pd + llvm_name: VFNMADD132PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfnmadd132pd + llvm_name: VFNMADD132PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd231ps + llvm_name: VFMSUBADD231PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd231ps + llvm_name: VFMSUBADD231PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd231ps + llvm_name: VFMSUBADD231PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd231ps + llvm_name: VFMSUBADD231PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd231ps + llvm_name: VFMSUBADD231PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd231ps + llvm_name: VFMSUBADD231PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd231pd + llvm_name: VFMSUBADD231PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd231pd + llvm_name: VFMSUBADD231PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd231pd + llvm_name: VFMSUBADD231PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd231pd + llvm_name: VFMSUBADD231PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd231pd + llvm_name: VFMSUBADD231PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd231pd + llvm_name: VFMSUBADD231PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd213ps + llvm_name: VFMSUBADD213PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd213ps + llvm_name: VFMSUBADD213PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd213ps + llvm_name: VFMSUBADD213PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd213ps + llvm_name: VFMSUBADD213PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd213ps + llvm_name: VFMSUBADD213PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd213ps + llvm_name: VFMSUBADD213PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd213pd + llvm_name: VFMSUBADD213PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd213pd + llvm_name: VFMSUBADD213PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd213pd + llvm_name: VFMSUBADD213PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd213pd + llvm_name: VFMSUBADD213PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd213pd + llvm_name: VFMSUBADD213PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd213pd + llvm_name: VFMSUBADD213PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd132ps + llvm_name: VFMSUBADD132PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd132ps + llvm_name: VFMSUBADD132PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd132ps + llvm_name: VFMSUBADD132PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd132ps + llvm_name: VFMSUBADD132PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd132ps + llvm_name: VFMSUBADD132PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd132ps + llvm_name: VFMSUBADD132PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd132pd + llvm_name: VFMSUBADD132PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd132pd + llvm_name: VFMSUBADD132PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd132pd + llvm_name: VFMSUBADD132PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd132pd + llvm_name: VFMSUBADD132PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd132pd + llvm_name: VFMSUBADD132PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsubadd132pd + llvm_name: VFMSUBADD132PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub231ss + llvm_name: VFMSUB231SSr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub231ss + llvm_name: VFMSUB231SSZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub231sd + llvm_name: VFMSUB231SDr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub231sd + llvm_name: VFMSUB231SDZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub231ps + llvm_name: VFMSUB231PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub231ps + llvm_name: VFMSUB231PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub231ps + llvm_name: VFMSUB231PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub231ps + llvm_name: VFMSUB231PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub231ps + llvm_name: VFMSUB231PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub231ps + llvm_name: VFMSUB231PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub231pd + llvm_name: VFMSUB231PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub231pd + llvm_name: VFMSUB231PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub231pd + llvm_name: VFMSUB231PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub231pd + llvm_name: VFMSUB231PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub231pd + llvm_name: VFMSUB231PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub231pd + llvm_name: VFMSUB231PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub213ss + llvm_name: VFMSUB213SSr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub213ss + llvm_name: VFMSUB213SSZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub213sd + llvm_name: VFMSUB213SDr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub213sd + llvm_name: VFMSUB213SDZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub213ps + llvm_name: VFMSUB213PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub213ps + llvm_name: VFMSUB213PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub213ps + llvm_name: VFMSUB213PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub213ps + llvm_name: VFMSUB213PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub213ps + llvm_name: VFMSUB213PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub213ps + llvm_name: VFMSUB213PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub213pd + llvm_name: VFMSUB213PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub213pd + llvm_name: VFMSUB213PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub213pd + llvm_name: VFMSUB213PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub213pd + llvm_name: VFMSUB213PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub213pd + llvm_name: VFMSUB213PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub213pd + llvm_name: VFMSUB213PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub132ss + llvm_name: VFMSUB132SSr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub132ss + llvm_name: VFMSUB132SSZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub132sd + llvm_name: VFMSUB132SDr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub132sd + llvm_name: VFMSUB132SDZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub132ps + llvm_name: VFMSUB132PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub132ps + llvm_name: VFMSUB132PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub132ps + llvm_name: VFMSUB132PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub132ps + llvm_name: VFMSUB132PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub132ps + llvm_name: VFMSUB132PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub132ps + llvm_name: VFMSUB132PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub132pd + llvm_name: VFMSUB132PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub132pd + llvm_name: VFMSUB132PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub132pd + llvm_name: VFMSUB132PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub132pd + llvm_name: VFMSUB132PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub132pd + llvm_name: VFMSUB132PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmsub132pd + llvm_name: VFMSUB132PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub231ps + llvm_name: VFMADDSUB231PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub231ps + llvm_name: VFMADDSUB231PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub231ps + llvm_name: VFMADDSUB231PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub231ps + llvm_name: VFMADDSUB231PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub231ps + llvm_name: VFMADDSUB231PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub231ps + llvm_name: VFMADDSUB231PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub231pd + llvm_name: VFMADDSUB231PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub231pd + llvm_name: VFMADDSUB231PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub231pd + llvm_name: VFMADDSUB231PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub231pd + llvm_name: VFMADDSUB231PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub231pd + llvm_name: VFMADDSUB231PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub231pd + llvm_name: VFMADDSUB231PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub213ps + llvm_name: VFMADDSUB213PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub213ps + llvm_name: VFMADDSUB213PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub213ps + llvm_name: VFMADDSUB213PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub213ps + llvm_name: VFMADDSUB213PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub213ps + llvm_name: VFMADDSUB213PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub213ps + llvm_name: VFMADDSUB213PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub213pd + llvm_name: VFMADDSUB213PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub213pd + llvm_name: VFMADDSUB213PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub213pd + llvm_name: VFMADDSUB213PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub213pd + llvm_name: VFMADDSUB213PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub213pd + llvm_name: VFMADDSUB213PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub213pd + llvm_name: VFMADDSUB213PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub132ps + llvm_name: VFMADDSUB132PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub132ps + llvm_name: VFMADDSUB132PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub132ps + llvm_name: VFMADDSUB132PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub132ps + llvm_name: VFMADDSUB132PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub132ps + llvm_name: VFMADDSUB132PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub132ps + llvm_name: VFMADDSUB132PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub132pd + llvm_name: VFMADDSUB132PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub132pd + llvm_name: VFMADDSUB132PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub132pd + llvm_name: VFMADDSUB132PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub132pd + llvm_name: VFMADDSUB132PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub132pd + llvm_name: VFMADDSUB132PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmaddsub132pd + llvm_name: VFMADDSUB132PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd231ss + llvm_name: VFMADD231SSr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd231ss + llvm_name: VFMADD231SSZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd231sd + llvm_name: VFMADD231SDr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd231sd + llvm_name: VFMADD231SDZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd231ps + llvm_name: VFMADD231PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd231ps + llvm_name: VFMADD231PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd231ps + llvm_name: VFMADD231PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd231ps + llvm_name: VFMADD231PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd231ps + llvm_name: VFMADD231PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd231ps + llvm_name: VFMADD231PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd231pd + llvm_name: VFMADD231PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd231pd + llvm_name: VFMADD231PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd231pd + llvm_name: VFMADD231PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd231pd + llvm_name: VFMADD231PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd231pd + llvm_name: VFMADD231PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd231pd + llvm_name: VFMADD231PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd213ss + llvm_name: VFMADD213SSr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd213ss + llvm_name: VFMADD213SSZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd213sd + llvm_name: VFMADD213SDr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd213sd + llvm_name: VFMADD213SDZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd213ps + llvm_name: VFMADD213PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd213ps + llvm_name: VFMADD213PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd213ps + llvm_name: VFMADD213PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd213ps + llvm_name: VFMADD213PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd213ps + llvm_name: VFMADD213PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd213ps + llvm_name: VFMADD213PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd213pd + llvm_name: VFMADD213PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd213pd + llvm_name: VFMADD213PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd213pd + llvm_name: VFMADD213PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd213pd + llvm_name: VFMADD213PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd213pd + llvm_name: VFMADD213PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd213pd + llvm_name: VFMADD213PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd132ss + llvm_name: VFMADD132SSr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd132ss + llvm_name: VFMADD132SSZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd132sd + llvm_name: VFMADD132SDr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd132sd + llvm_name: VFMADD132SDZrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd132ps + llvm_name: VFMADD132PSr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd132ps + llvm_name: VFMADD132PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd132ps + llvm_name: VFMADD132PSZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd132ps + llvm_name: VFMADD132PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd132ps + llvm_name: VFMADD132PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd132ps + llvm_name: VFMADD132PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd132pd + llvm_name: VFMADD132PDr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd132pd + llvm_name: VFMADD132PDZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd132pd + llvm_name: VFMADD132PDZrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd132pd + llvm_name: VFMADD132PDZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd132pd + llvm_name: VFMADD132PDZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfmadd132pd + llvm_name: VFMADD132PDZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfixupimmss + llvm_name: VFIXUPIMMSSZrrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfixupimmss + llvm_name: VFIXUPIMMSSZrrib + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfixupimmsd + llvm_name: VFIXUPIMMSDZrrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfixupimmsd + llvm_name: VFIXUPIMMSDZrrib + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfixupimmps + llvm_name: VFIXUPIMMPSZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfixupimmps + llvm_name: VFIXUPIMMPSZrrib + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfixupimmps + llvm_name: VFIXUPIMMPSZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfixupimmps + llvm_name: VFIXUPIMMPSZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfixupimmps + llvm_name: VFIXUPIMMPSZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfixupimmps + llvm_name: VFIXUPIMMPSZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfixupimmpd + llvm_name: VFIXUPIMMPDZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfixupimmpd + llvm_name: VFIXUPIMMPDZrrib + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfixupimmpd + llvm_name: VFIXUPIMMPDZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfixupimmpd + llvm_name: VFIXUPIMMPDZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfixupimmpd + llvm_name: VFIXUPIMMPDZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vfixupimmpd + llvm_name: VFIXUPIMMPDZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vextractps + llvm_name: VEXTRACTPSrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, ['0123']], [1, ['4', '5']]] + throughput: 1.5 + uops: ~ +- name: vextracti64x4 + llvm_name: VEXTRACTI64X4Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextracti64x4 + llvm_name: VEXTRACTI64X4Zrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextracti64x2 + llvm_name: VEXTRACTI64X2Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextracti64x2 + llvm_name: VEXTRACTI64X2Zrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextracti64x2 + llvm_name: VEXTRACTI64X2Z256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextracti64x2 + llvm_name: VEXTRACTI64X2Z256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextracti32x8 + llvm_name: VEXTRACTI32X8Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextracti32x8 + llvm_name: VEXTRACTI32X8Zrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextracti32x4 + llvm_name: VEXTRACTI32X4Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextracti32x4 + llvm_name: VEXTRACTI32X4Zrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextracti32x4 + llvm_name: VEXTRACTI32X4Z256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextracti32x4 + llvm_name: VEXTRACTI32X4Z256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextracti128 + llvm_name: VEXTRACTI128rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextractf64x4 + llvm_name: VEXTRACTF64X4Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextractf64x4 + llvm_name: VEXTRACTF64X4Zrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextractf64x2 + llvm_name: VEXTRACTF64X2Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextractf64x2 + llvm_name: VEXTRACTF64X2Zrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextractf64x2 + llvm_name: VEXTRACTF64X2Z256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextractf64x2 + llvm_name: VEXTRACTF64X2Z256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextractf32x8 + llvm_name: VEXTRACTF32X8Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextractf32x8 + llvm_name: VEXTRACTF32X8Zrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextractf32x4 + llvm_name: VEXTRACTF32X4Zrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextractf32x4 + llvm_name: VEXTRACTF32X4Zrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextractf32x4 + llvm_name: VEXTRACTF32X4Z256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextractf32x4 + llvm_name: VEXTRACTF32X4Z256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vextractf128 + llvm_name: VEXTRACTF128rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vexpandps + llvm_name: VEXPANDPSZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vexpandps + llvm_name: VEXPANDPSZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vexpandps + llvm_name: VEXPANDPSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vexpandps + llvm_name: VEXPANDPSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vexpandps + llvm_name: VEXPANDPSZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2.2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vexpandps + llvm_name: VEXPANDPSZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vexpandpd + llvm_name: VEXPANDPDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vexpandpd + llvm_name: VEXPANDPDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vexpandpd + llvm_name: VEXPANDPDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vexpandpd + llvm_name: VEXPANDPDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vexpandpd + llvm_name: VEXPANDPDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vexpandpd + llvm_name: VEXPANDPDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2.2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vdpps + llvm_name: VDPPSrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: {0: [[1, '0'], [4, '1']], 1: [[1, '0'], [4, '3']], 2: [[1, '2'], [4, '1']], 3: [[1, '2'], [4, '3']]} + throughput: 4.0 + uops: ~ +- name: vdpps + llvm_name: VDPPSYrri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 13 + port_pressure: {0: [[1, '0'], [4, '1']], 1: [[1, '0'], [4, '3']], 2: [[1, '2'], [4, '1']], 3: [[1, '2'], [4, '3']]} + throughput: 4.0 + uops: ~ +- name: vdppd + llvm_name: VDPPDrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: {0: [[1, '0'], [3, '1']], 1: [[1, '0'], [3, '3']], 2: [[1, '2'], [3, '1']], 3: [[1, '2'], [3, '3']]} + throughput: 3 + uops: ~ +- name: vdpbf16ps + llvm_name: VDPBF16PSZrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vdpbf16ps + llvm_name: VDPBF16PSZr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vdpbf16ps + llvm_name: VDPBF16PSZ256rkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vdpbf16ps + llvm_name: VDPBF16PSZ256r + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vdpbf16ps + llvm_name: VDPBF16PSZ128rkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vdpbf16ps + llvm_name: VDPBF16PSZ128r + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 6 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vdivss + llvm_name: VDIVSSrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[1, '02'], [5, [0DV, 2DV]]] + throughput: 2.5 + uops: ~ +- name: vdivss + llvm_name: VDIVSSZrrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 10 + port_pressure: [[1, '02'], [5, [0DV, 2DV]]] + throughput: 2.5 + uops: ~ +- name: vdivsd + llvm_name: VDIVSDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '02'], [8, [0DV, 2DV]]] + throughput: 4.0 + uops: ~ +- name: vdivsd + llvm_name: VDIVSDZrrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 13 + port_pressure: [[1, '02'], [8, [0DV, 2DV]]] + throughput: 4.0 + uops: ~ +- name: vdivps + llvm_name: VDIVPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[1, '02'], [5, [0DV, 2DV]]] + throughput: 2.5 + uops: ~ +- name: vdivps + llvm_name: VDIVPSZrrk + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 10 + port_pressure: [[1, '02'], [5, [0DV, 2DV]]] + throughput: 2.5 + uops: ~ +- name: vdivps + llvm_name: VDIVPSZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 10 + port_pressure: [[1, '02'], [5, [0DV, 2DV]]] + throughput: 2.5 + uops: ~ +- name: vdivps + llvm_name: VDIVPSZ256rrk + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 10 + port_pressure: [[1, '02'], [5, [0DV, 2DV]]] + throughput: 2.5 + uops: ~ +- name: vdivps + llvm_name: VDIVPSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 10 + port_pressure: [[1, '02'], [5, [0DV, 2DV]]] + throughput: 2.5 + uops: ~ +- name: vdivps + llvm_name: VDIVPSZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 10 + port_pressure: [[1, '02'], [5, [0DV, 2DV]]] + throughput: 2.5 + uops: ~ +- name: vdivps + llvm_name: VDIVPSZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[1, '02'], [5, [0DV, 2DV]]] + throughput: 2.5 + uops: ~ +- name: vdivps + llvm_name: VDIVPSYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 10 + port_pressure: [[1, '02'], [5, [0DV, 2DV]]] + throughput: 2.5 + uops: ~ +- name: vdivpd + llvm_name: VDIVPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '02'], [8, [0DV, 2DV]]] + throughput: 4.0 + uops: ~ +- name: vdivpd + llvm_name: VDIVPDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 13 + port_pressure: [[1, '02'], [8, [0DV, 2DV]]] + throughput: 4.0 + uops: ~ +- name: vdivpd + llvm_name: VDIVPDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 13 + port_pressure: [[1, '02'], [8, [0DV, 2DV]]] + throughput: 4.0 + uops: ~ +- name: vdivpd + llvm_name: VDIVPDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 13 + port_pressure: [[1, '02'], [8, [0DV, 2DV]]] + throughput: 4.0 + uops: ~ +- name: vdivpd + llvm_name: VDIVPDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 13 + port_pressure: [[1, '02'], [8, [0DV, 2DV]]] + throughput: 4.0 + uops: ~ +- name: vdivpd + llvm_name: VDIVPDZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 13 + port_pressure: [[1, '02'], [8, [0DV, 2DV]]] + throughput: 4.0 + uops: ~ +- name: vdivpd + llvm_name: VDIVPDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '02'], [8, [0DV, 2DV]]] + throughput: 4.0 + uops: ~ +- name: vdivpd + llvm_name: VDIVPDYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 13 + port_pressure: [[1, '02'], [8, [0DV, 2DV]]] + throughput: 4.0 + uops: ~ +- name: vdbpsadbw + llvm_name: VDBPSADBWZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['0', '1', '2', '3']], [1, ['0', '2']]] + throughput: 0.75 + uops: ~ +- name: vdbpsadbw + llvm_name: VDBPSADBWZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['0', '1', '2', '3']], [1, ['0', '2']]] + throughput: 0.75 + uops: ~ +- name: vdbpsadbw + llvm_name: VDBPSADBWZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 5 + port_pressure: [[1, ['0', '1', '2', '3']], [1, ['0', '2']]] + throughput: 0.75 + uops: ~ +- name: vdbpsadbw + llvm_name: VDBPSADBWZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 5 + port_pressure: [[1, ['0', '1', '2', '3']], [1, ['0', '2']]] + throughput: 0.75 + uops: ~ +- name: vdbpsadbw + llvm_name: VDBPSADBWZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 5 + port_pressure: [[1, ['0', '1', '2', '3']], [1, ['0', '2']]] + throughput: 0.75 + uops: ~ +- name: vdbpsadbw + llvm_name: VDBPSADBWZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['0', '1', '2', '3']], [1, ['0', '2']]] + throughput: 0.75 + uops: ~ +- name: vcvtusi2ss + llvm_name: VCVTUSI642SSZrrb_Int + operands: + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 9 + port_pressure: [[2, '13']] + throughput: 1.0 + uops: ~ +- name: vcvtusi2sd + llvm_name: VCVTUSI642SDZrrb_Int + operands: + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 9 + port_pressure: [[2, '13']] + throughput: 1.0 + uops: ~ +- name: vcvtuqq2ps + llvm_name: VCVTUQQ2PSZrrkz + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtuqq2ps + llvm_name: VCVTUQQ2PSZrrb + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtuqq2ps + llvm_name: VCVTUQQ2PSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtuqq2ps + llvm_name: VCVTUQQ2PSZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtuqq2ps + llvm_name: VCVTUQQ2PSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtuqq2ps + llvm_name: VCVTUQQ2PSZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtuqq2pd + llvm_name: VCVTUQQ2PDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtuqq2pd + llvm_name: VCVTUQQ2PDZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtuqq2pd + llvm_name: VCVTUQQ2PDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtuqq2pd + llvm_name: VCVTUQQ2PDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtuqq2pd + llvm_name: VCVTUQQ2PDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtuqq2pd + llvm_name: VCVTUQQ2PDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtudq2ps + llvm_name: VCVTUDQ2PSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtudq2ps + llvm_name: VCVTUDQ2PSZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtudq2ps + llvm_name: VCVTUDQ2PSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtudq2ps + llvm_name: VCVTUDQ2PSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtudq2ps + llvm_name: VCVTUDQ2PSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtudq2ps + llvm_name: VCVTUDQ2PSZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtudq2pd + llvm_name: VCVTUDQ2PDZrrkz + operands: + - class: register + name: ymm + - class: register + name: zmm + mask: true + latency: 9 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtudq2pd + llvm_name: VCVTUDQ2PDZrr + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 9 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtudq2pd + llvm_name: VCVTUDQ2PDZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtudq2pd + llvm_name: VCVTUDQ2PDZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtudq2pd + llvm_name: VCVTUDQ2PDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtudq2pd + llvm_name: VCVTUDQ2PDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttss2usi + llvm_name: VCVTTSS2USIZrr + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 9 + port_pressure: [[1, ['1', '3']], [1, ['4', '5']]] + throughput: 0.5 + uops: ~ +- name: vcvttss2si + llvm_name: VCVTTSS2SIrr_Int + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 9 + port_pressure: [[1, ['1', '3']], [1, ['4', '5']]] + throughput: 0.5 + uops: ~ +- name: vcvttsd2usi + llvm_name: VCVTTSD2USIZrrb_Int + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 9 + port_pressure: [[1, ['1', '3']], [1, ['4', '5']]] + throughput: 0.5 + uops: ~ +- name: vcvttsd2si + llvm_name: VCVTTSD2SIZrrb_Int + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 9 + port_pressure: [[1, ['1', '3']], [1, ['4', '5']]] + throughput: 0.5 + uops: ~ +- name: vcvttps2uqq + llvm_name: VCVTTPS2UQQZrrkz + operands: + - class: register + name: ymm + - class: register + name: zmm + mask: true + latency: 9 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvttps2uqq + llvm_name: VCVTTPS2UQQZrrb + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 9 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvttps2uqq + llvm_name: VCVTTPS2UQQZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvttps2uqq + llvm_name: VCVTTPS2UQQZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvttps2uqq + llvm_name: VCVTTPS2UQQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttps2uqq + llvm_name: VCVTTPS2UQQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttps2udq + llvm_name: VCVTTPS2UDQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttps2udq + llvm_name: VCVTTPS2UDQZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttps2udq + llvm_name: VCVTTPS2UDQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttps2udq + llvm_name: VCVTTPS2UDQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttps2udq + llvm_name: VCVTTPS2UDQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttps2udq + llvm_name: VCVTTPS2UDQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttps2qq + llvm_name: VCVTTPS2QQZrrkz + operands: + - class: register + name: ymm + - class: register + name: zmm + mask: true + latency: 9 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvttps2qq + llvm_name: VCVTTPS2QQZrrb + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 9 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvttps2qq + llvm_name: VCVTTPS2QQZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvttps2qq + llvm_name: VCVTTPS2QQZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvttps2qq + llvm_name: VCVTTPS2QQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttps2qq + llvm_name: VCVTTPS2QQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttps2dq + llvm_name: VCVTTPS2DQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttps2dq + llvm_name: VCVTTPS2DQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttps2dq + llvm_name: VCVTTPS2DQZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttps2dq + llvm_name: VCVTTPS2DQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttps2dq + llvm_name: VCVTTPS2DQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttps2dq + llvm_name: VCVTTPS2DQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttpd2uqq + llvm_name: VCVTTPD2UQQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttpd2uqq + llvm_name: VCVTTPD2UQQZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttpd2uqq + llvm_name: VCVTTPD2UQQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttpd2uqq + llvm_name: VCVTTPD2UQQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttpd2uqq + llvm_name: VCVTTPD2UQQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttpd2uqq + llvm_name: VCVTTPD2UQQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttpd2udq + llvm_name: VCVTTPD2UDQZrrkz + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvttpd2udq + llvm_name: VCVTTPD2UDQZrrb + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvttpd2udq + llvm_name: VCVTTPD2UDQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvttpd2udq + llvm_name: VCVTTPD2UDQZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvttpd2udq + llvm_name: VCVTTPD2UDQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttpd2udq + llvm_name: VCVTTPD2UDQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttpd2qq + llvm_name: VCVTTPD2QQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttpd2qq + llvm_name: VCVTTPD2QQZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttpd2qq + llvm_name: VCVTTPD2QQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttpd2qq + llvm_name: VCVTTPD2QQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttpd2qq + llvm_name: VCVTTPD2QQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttpd2qq + llvm_name: VCVTTPD2QQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttpd2dq + llvm_name: VCVTTPD2DQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvttpd2dq + llvm_name: VCVTTPD2DQZrrkz + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvttpd2dq + llvm_name: VCVTTPD2DQZrrb + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvttpd2dq + llvm_name: VCVTTPD2DQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvttpd2dq + llvm_name: VCVTTPD2DQZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvttpd2dq + llvm_name: VCVTTPD2DQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtss2usi + llvm_name: VCVTSS2USIZrrb_Int + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 9 + port_pressure: [[1, '13'], [1, '45']] + throughput: 0.5 + uops: ~ +- name: vcvtss2si + llvm_name: VCVTSS2SIrr_Int + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 9 + port_pressure: [[1, '13'], [1, '45']] + throughput: 0.5 + uops: ~ +- name: vcvtss2sd + llvm_name: VCVTSS2SDrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtss2sd + llvm_name: VCVTSS2SDZrrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtsi2ss + llvm_name: VCVTSI642SSrr_Int + operands: + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 9 + port_pressure: [[2, ['1', '3']]] + throughput: 1.00 + uops: ~ +- name: vcvtsi2sd + llvm_name: VCVTSI642SDrr_Int + operands: + - class: register + name: gpr + - class: register + name: xmm + - class: register + name: xmm + latency: 9 + port_pressure: [[2, ['1', '3']]] + throughput: 1.00 + uops: ~ +- name: vcvtsd2usi + llvm_name: VCVTSD2USIZrrb_Int + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 9 + port_pressure: [[1, ['1', '3']], [1, ['4', '5']]] + throughput: 0.66666 + uops: ~ +- name: vcvtsd2ss + llvm_name: VCVTSD2SSrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtsd2ss + llvm_name: VCVTSD2SSZrrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtsd2si + llvm_name: VCVTSD2SI64rr_Int + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 9 + port_pressure: [[1, ['1', '3']], [1, ['4', '5']]] + throughput: 0.66666 + uops: ~ +- name: vcvtqq2ps + llvm_name: VCVTQQ2PSZrrkz + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtqq2ps + llvm_name: VCVTQQ2PSZrrb + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtqq2ps + llvm_name: VCVTQQ2PSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtqq2ps + llvm_name: VCVTQQ2PSZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtqq2ps + llvm_name: VCVTQQ2PSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtqq2ps + llvm_name: VCVTQQ2PSZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtqq2pd + llvm_name: VCVTQQ2PDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtqq2pd + llvm_name: VCVTQQ2PDZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtqq2pd + llvm_name: VCVTQQ2PDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtqq2pd + llvm_name: VCVTQQ2PDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtqq2pd + llvm_name: VCVTQQ2PDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtqq2pd + llvm_name: VCVTQQ2PDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2uqq + llvm_name: VCVTPS2UQQZrrkz + operands: + - class: register + name: ymm + - class: register + name: zmm + mask: true + latency: 9 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtps2uqq + llvm_name: VCVTPS2UQQZrrb + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 9 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtps2uqq + llvm_name: VCVTPS2UQQZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtps2uqq + llvm_name: VCVTPS2UQQZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtps2uqq + llvm_name: VCVTPS2UQQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2uqq + llvm_name: VCVTPS2UQQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2udq + llvm_name: VCVTPS2UDQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2udq + llvm_name: VCVTPS2UDQZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2udq + llvm_name: VCVTPS2UDQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2udq + llvm_name: VCVTPS2UDQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2udq + llvm_name: VCVTPS2UDQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2udq + llvm_name: VCVTPS2UDQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2qq + llvm_name: VCVTPS2QQZrrkz + operands: + - class: register + name: ymm + - class: register + name: zmm + mask: true + latency: 9 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtps2qq + llvm_name: VCVTPS2QQZrrb + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 9 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtps2qq + llvm_name: VCVTPS2QQZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtps2qq + llvm_name: VCVTPS2QQZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtps2qq + llvm_name: VCVTPS2QQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2qq + llvm_name: VCVTPS2QQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2ph + llvm_name: VCVTPS2PHZ128rr + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2ph + llvm_name: VCVTPS2PHZrrkz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtps2ph + llvm_name: VCVTPS2PHZrrb + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: ymm + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtps2ph + llvm_name: VCVTPS2PHZ256rrkz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtps2ph + llvm_name: VCVTPS2PHZ256rr + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtps2ph + llvm_name: VCVTPS2PHZ128rrkz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2pd + llvm_name: VCVTPS2PDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2pd + llvm_name: VCVTPS2PDZrrkz + operands: + - class: register + name: ymm + - class: register + name: zmm + mask: true + latency: 9 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtps2pd + llvm_name: VCVTPS2PDZrrb + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 9 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtps2pd + llvm_name: VCVTPS2PDZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtps2pd + llvm_name: VCVTPS2PDZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtps2pd + llvm_name: VCVTPS2PDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2dq + llvm_name: VCVTPS2DQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2dq + llvm_name: VCVTPS2DQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2dq + llvm_name: VCVTPS2DQZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2dq + llvm_name: VCVTPS2DQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2dq + llvm_name: VCVTPS2DQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtps2dq + llvm_name: VCVTPS2DQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtph2ps + llvm_name: VCVTPH2PSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtph2ps + llvm_name: VCVTPH2PSZrrkz + operands: + - class: register + name: ymm + - class: register + name: zmm + mask: true + latency: 9 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtph2ps + llvm_name: VCVTPH2PSZrrb + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 9 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtph2ps + llvm_name: VCVTPH2PSZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtph2ps + llvm_name: VCVTPH2PSZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtph2ps + llvm_name: VCVTPH2PSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2uqq + llvm_name: VCVTPD2UQQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2uqq + llvm_name: VCVTPD2UQQZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2uqq + llvm_name: VCVTPD2UQQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2uqq + llvm_name: VCVTPD2UQQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2uqq + llvm_name: VCVTPD2UQQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2uqq + llvm_name: VCVTPD2UQQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2udq + llvm_name: VCVTPD2UDQZrrk + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtpd2udq + llvm_name: VCVTPD2UDQZrrb + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtpd2udq + llvm_name: VCVTPD2UDQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtpd2udq + llvm_name: VCVTPD2UDQZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtpd2udq + llvm_name: VCVTPD2UDQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2udq + llvm_name: VCVTPD2UDQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2qq + llvm_name: VCVTPD2QQZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2qq + llvm_name: VCVTPD2QQZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2qq + llvm_name: VCVTPD2QQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2qq + llvm_name: VCVTPD2QQZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2qq + llvm_name: VCVTPD2QQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2qq + llvm_name: VCVTPD2QQZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2ps + llvm_name: VCVTPD2PSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2ps + llvm_name: VCVTPD2PSZrrkz + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtpd2ps + llvm_name: VCVTPD2PSZrrb + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtpd2ps + llvm_name: VCVTPD2PSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtpd2ps + llvm_name: VCVTPD2PSZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtpd2ps + llvm_name: VCVTPD2PSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2dq + llvm_name: VCVTPD2DQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtpd2dq + llvm_name: VCVTPD2DQZrrkz + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtpd2dq + llvm_name: VCVTPD2DQZrrb + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtpd2dq + llvm_name: VCVTPD2DQZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtpd2dq + llvm_name: VCVTPD2DQZ256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtpd2dq + llvm_name: VCVTPD2DQZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtneps2bf16 + llvm_name: VCVTNEPS2BF16Zrrkz + operands: + - class: register + name: zmm + - class: register + name: ymm + mask: true + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtneps2bf16 + llvm_name: VCVTNEPS2BF16Zrr + operands: + - class: register + name: zmm + - class: register + name: ymm + latency: 8 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtneps2bf16 + llvm_name: VCVTNEPS2BF16Z256rrkz + operands: + - class: register + name: ymm + - class: register + name: xmm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtneps2bf16 + llvm_name: VCVTNEPS2BF16Z256rr + operands: + - class: register + name: ymm + - class: register + name: xmm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtneps2bf16 + llvm_name: VCVTNEPS2BF16Z128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtneps2bf16 + llvm_name: VCVTNEPS2BF16Z128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtne2ps2bf16 + llvm_name: VCVTNE2PS2BF16Zrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtne2ps2bf16 + llvm_name: VCVTNE2PS2BF16Zrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtne2ps2bf16 + llvm_name: VCVTNE2PS2BF16Z256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtne2ps2bf16 + llvm_name: VCVTNE2PS2BF16Z256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 6 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtne2ps2bf16 + llvm_name: VCVTNE2PS2BF16Z128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtne2ps2bf16 + llvm_name: VCVTNE2PS2BF16Z128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtdq2ps + llvm_name: VCVTDQ2PSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtdq2ps + llvm_name: VCVTDQ2PSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtdq2ps + llvm_name: VCVTDQ2PSZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtdq2ps + llvm_name: VCVTDQ2PSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtdq2ps + llvm_name: VCVTDQ2PSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtdq2ps + llvm_name: VCVTDQ2PSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtdq2pd + llvm_name: VCVTDQ2PDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcvtdq2pd + llvm_name: VCVTDQ2PDZrrkz + operands: + - class: register + name: ymm + - class: register + name: zmm + mask: true + latency: 9 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtdq2pd + llvm_name: VCVTDQ2PDZrr + operands: + - class: register + name: ymm + - class: register + name: zmm + latency: 9 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtdq2pd + llvm_name: VCVTDQ2PDZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtdq2pd + llvm_name: VCVTDQ2PDZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 7 + port_pressure: [[1, ['1', '2']], [1, ['1', '3']]] + throughput: 0.66666 + uops: ~ +- name: vcvtdq2pd + llvm_name: VCVTDQ2PDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcompressps + llvm_name: VCOMPRESSPSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vcompressps + llvm_name: VCOMPRESSPSZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vcompressps + llvm_name: VCOMPRESSPSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vcompressps + llvm_name: VCOMPRESSPSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vcompressps + llvm_name: VCOMPRESSPSZ128rrk + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2.2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vcompressps + llvm_name: VCOMPRESSPSZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2.2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vcompresspd + llvm_name: VCOMPRESSPDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vcompresspd + llvm_name: VCOMPRESSPDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vcompresspd + llvm_name: VCOMPRESSPDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vcompresspd + llvm_name: VCOMPRESSPDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vcompresspd + llvm_name: VCOMPRESSPDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2.2 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vcompresspd + llvm_name: VCOMPRESSPDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 1.9 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: vcmpss + llvm_name: VCMPSSrri_Int + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmpsd + llvm_name: VCMPSDrri_Int + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmpps + llvm_name: VCMPPSrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmpps + llvm_name: VCMPPSZrrik + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmpps + llvm_name: VCMPPSZrrib + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmpps + llvm_name: VCMPPSZ256rrik + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmpps + llvm_name: VCMPPSZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmpps + llvm_name: VCMPPSZ128rrik + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmpps + llvm_name: VCMPPSZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmpps + llvm_name: VCMPPSYrri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmppd + llvm_name: VCMPPDrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmppd + llvm_name: VCMPPDZrrik + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + mask: true + latency: 7 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmppd + llvm_name: VCMPPDZrrib + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: k + latency: 7 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmppd + llvm_name: VCMPPDZ256rrik + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + mask: true + latency: 5 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmppd + llvm_name: VCMPPDZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: k + latency: 5 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmppd + llvm_name: VCMPPDZ128rrik + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + mask: true + latency: 4 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmppd + llvm_name: VCMPPDZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: k + latency: 4 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vcmppd + llvm_name: VCMPPDYrri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vbroadcastss + llvm_name: VBROADCASTSSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vbroadcastss + llvm_name: VBROADCASTSSZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcastss + llvm_name: VBROADCASTSSZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcastss + llvm_name: VBROADCASTSSZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcastss + llvm_name: VBROADCASTSSZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcastss + llvm_name: VBROADCASTSSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcastsd + llvm_name: VBROADCASTSDZrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcastsd + llvm_name: VBROADCASTSDZrr + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcastsd + llvm_name: VBROADCASTSDZ256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcastsd + llvm_name: VBROADCASTSDZ256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcasti32x2 + llvm_name: VBROADCASTI32X2Zrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcasti32x2 + llvm_name: VBROADCASTI32X2Zrr + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcasti32x2 + llvm_name: VBROADCASTI32X2Z256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcasti32x2 + llvm_name: VBROADCASTI32X2Z256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcasti32x2 + llvm_name: VBROADCASTI32X2Z128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcasti32x2 + llvm_name: VBROADCASTI32X2Z128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcastf32x2 + llvm_name: VBROADCASTF32X2Zrrkz + operands: + - class: register + name: xmm + - class: register + name: zmm + mask: true + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcastf32x2 + llvm_name: VBROADCASTF32X2Zrr + operands: + - class: register + name: xmm + - class: register + name: zmm + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcastf32x2 + llvm_name: VBROADCASTF32X2Z256rrkz + operands: + - class: register + name: xmm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vbroadcastf32x2 + llvm_name: VBROADCASTF32X2Z256rr + operands: + - class: register + name: xmm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vblendvps + llvm_name: VBLENDVPSrrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vblendvps + llvm_name: VBLENDVPSYrrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vblendvpd + llvm_name: VBLENDVPDrrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vblendvpd + llvm_name: VBLENDVPDYrrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vblendps + llvm_name: VBLENDPSrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vblendps + llvm_name: VBLENDPSYrri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vblendpd + llvm_name: VBLENDPDrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vblendpd + llvm_name: VBLENDPDYrri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vblendmps + llvm_name: VBLENDMPSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vblendmps + llvm_name: VBLENDMPSZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vblendmps + llvm_name: VBLENDMPSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vblendmps + llvm_name: VBLENDMPSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vblendmps + llvm_name: VBLENDMPSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vblendmps + llvm_name: VBLENDMPSZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vblendmpd + llvm_name: VBLENDMPDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vblendmpd + llvm_name: VBLENDMPDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vblendmpd + llvm_name: VBLENDMPDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vblendmpd + llvm_name: VBLENDMPDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vblendmpd + llvm_name: VBLENDMPDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vblendmpd + llvm_name: VBLENDMPDZ128rr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandps + llvm_name: VANDPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandps + llvm_name: VANDPSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandps + llvm_name: VANDPSZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandps + llvm_name: VANDPSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandps + llvm_name: VANDPSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandps + llvm_name: VANDPSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandpd + llvm_name: VANDPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandpd + llvm_name: VANDPDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandpd + llvm_name: VANDPDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandpd + llvm_name: VANDPDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandpd + llvm_name: VANDPDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandpd + llvm_name: VANDPDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandnps + llvm_name: VANDNPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandnps + llvm_name: VANDNPSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandnps + llvm_name: VANDNPSZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandnps + llvm_name: VANDNPSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandnps + llvm_name: VANDNPSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandnps + llvm_name: VANDNPSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandnpd + llvm_name: VANDNPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandnpd + llvm_name: VANDNPDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandnpd + llvm_name: VANDNPDZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandnpd + llvm_name: VANDNPDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandnpd + llvm_name: VANDNPDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: vandnpd + llvm_name: VANDNPDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: valignq + llvm_name: VALIGNQZrrik + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: valignq + llvm_name: VALIGNQZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: valignq + llvm_name: VALIGNQZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: valignq + llvm_name: VALIGNQZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: valignq + llvm_name: VALIGNQZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: valignq + llvm_name: VALIGNQZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: valignd + llvm_name: VALIGNDZrrikz + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: valignd + llvm_name: VALIGNDZrri + operands: + - class: immediate + imd: int + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 5 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: valignd + llvm_name: VALIGNDZ256rrikz + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: valignd + llvm_name: VALIGNDZ256rri + operands: + - class: immediate + imd: int + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: valignd + llvm_name: VALIGNDZ128rrikz + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: valignd + llvm_name: VALIGNDZ128rri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: vaeskeygenassist + llvm_name: VAESKEYGENASSIST128rr + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vaesimc + llvm_name: VAESIMCrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vaesenc + llvm_name: VAESENCrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vaesenc + llvm_name: VAESENCZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vaesenc + llvm_name: VAESENCZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vaesenclast + llvm_name: VAESENCLASTrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vaesenclast + llvm_name: VAESENCLASTZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vaesenclast + llvm_name: VAESENCLASTZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vaesdec + llvm_name: VAESDECrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vaesdec + llvm_name: VAESDECZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vaesdec + llvm_name: VAESDECZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vaesdeclast + llvm_name: VAESDECLASTrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vaesdeclast + llvm_name: VAESDECLASTZrr + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vaesdeclast + llvm_name: VAESDECLASTZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: vaddsubps + llvm_name: VADDSUBPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddsubps + llvm_name: VADDSUBPSYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddsubpd + llvm_name: VADDSUBPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddsubpd + llvm_name: VADDSUBPDYrr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddss + llvm_name: VADDSSrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddss + llvm_name: VADDSSZrrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddsd + llvm_name: VADDSDrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddsd + llvm_name: VADDSDZrrkz_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddps + llvm_name: VADDPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddps + llvm_name: VADDPSZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddps + llvm_name: VADDPSZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddps + llvm_name: VADDPSZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddps + llvm_name: VADDPSZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddps + llvm_name: VADDPSZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddpd + llvm_name: VADDPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddpd + llvm_name: VADDPDZrrkz + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddpd + llvm_name: VADDPDZrrb + operands: + - class: register + name: zmm + - class: register + name: zmm + - class: register + name: zmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddpd + llvm_name: VADDPDZ256rrkz + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddpd + llvm_name: VADDPDZ256rr + operands: + - class: register + name: ymm + - class: register + name: ymm + - class: register + name: ymm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: vaddpd + llvm_name: VADDPDZ128rrkz + operands: + - class: register + name: xmm + - class: register + name: xmm + - class: register + name: xmm + mask: true + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: unpcklps + llvm_name: UNPCKLPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: unpcklpd + llvm_name: UNPCKLPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: unpckhps + llvm_name: UNPCKHPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: unpckhpd + llvm_name: UNPCKHPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: test + llvm_name: TEST8rr + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: test + llvm_name: TEST8ri + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: test + llvm_name: TEST8i8 + operands: + - class: immediate + imd: int + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: test + llvm_name: TEST64rr + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: subss + llvm_name: SUBSSrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: subsd + llvm_name: SUBSDrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: subps + llvm_name: SUBPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: subpd + llvm_name: SUBPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: sub + llvm_name: SUB8rr_REV + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: sub + llvm_name: SUB8ri8 + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: sub + llvm_name: SUB8i8 + operands: + - class: immediate + imd: int + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: stc + llvm_name: STC + operands: [] + latency: 0.1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: sqrtss + llvm_name: SQRTSSr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[9, ['0', '2']]] + throughput: 4.5 + uops: ~ +- name: sqrtsd + llvm_name: SQRTSDr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[15, ['0', '2']]] + throughput: 7.5 + uops: ~ +- name: sqrtps + llvm_name: SQRTPSr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 14 + port_pressure: [[9, ['0', '2']]] + throughput: 4.5 + uops: ~ +- name: sqrtpd + llvm_name: SQRTPDr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 20 + port_pressure: [[15, ['0', '2']]] + throughput: 7.5 + uops: ~ +- name: shufps + llvm_name: SHUFPSrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: shufpd + llvm_name: SHUFPDrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: shrx + llvm_name: SHRX64rr_EVEX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: shr + llvm_name: SHR8r1 + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: shr + llvm_name: SHR64ri + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: shlx + llvm_name: SHLX64rr_EVEX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: shl + llvm_name: SHL8ri + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: shl + llvm_name: SHL8r1 + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: sha256msg1 + llvm_name: SHA256MSG1rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[2, ['0', '1', '2', '3']], [1, ['1', '2']], [1, ['0', '3']]] + throughput: 1.5 + uops: ~ +- name: sha1msg2 + llvm_name: SHA1MSG2rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[2, ['0', '1', '2', '3']], [1, ['1', '2']], [1, ['0', '3']]] + throughput: 1.5 + uops: ~ +- name: sha1msg1 + llvm_name: SHA1MSG1rr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[2, ['0', '1', '2', '3']], [1, ['1', '2']], [1, ['0', '3']]] + throughput: 1.5 + uops: ~ +- name: set + llvm_name: SETCCr + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: sbb + llvm_name: SBB8rr_REV + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: sbb + llvm_name: SBB8ri8 + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: sarx + llvm_name: SARX64rr_EVEX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: sar + llvm_name: SAR8ri + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: sar + llvm_name: SAR8r1 + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: sahf + llvm_name: SAHF + operands: [] + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: rsqrtss + llvm_name: RSQRTSSr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: rsqrtps + llvm_name: RSQRTPSr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: roundss + llvm_name: ROUNDSSri_Int + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: roundsd + llvm_name: ROUNDSDri_Int + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: roundps + llvm_name: ROUNDPSri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: roundpd + llvm_name: ROUNDPDri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: rorx + llvm_name: RORX64ri_EVEX + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: ror + llvm_name: ROR8ri + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: ror + llvm_name: ROR8r1 + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: rol + llvm_name: ROL8ri + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: rol + llvm_name: ROL8r1 + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: rcr + llvm_name: RCR8r1 + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: rcpss + llvm_name: RCPSSr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: rcpps + llvm_name: RCPPSr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pxor + llvm_name: PXORrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: punpcklwd + llvm_name: PUNPCKLWDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: punpcklqdq + llvm_name: PUNPCKLQDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: punpckldq + llvm_name: PUNPCKLDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: punpcklbw + llvm_name: PUNPCKLBWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: punpckhwd + llvm_name: PUNPCKHWDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: punpckhqdq + llvm_name: PUNPCKHQDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: punpckhdq + llvm_name: PUNPCKHDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: punpckhbw + llvm_name: PUNPCKHBWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: psubw + llvm_name: PSUBWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: psubusw + llvm_name: PSUBUSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: psubusb + llvm_name: PSUBUSBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: psubsw + llvm_name: PSUBSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: psubsb + llvm_name: PSUBSBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: psubq + llvm_name: PSUBQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: psubd + llvm_name: PSUBDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: psubb + llvm_name: PSUBBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: psrlw + llvm_name: PSRLWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: psrlw + llvm_name: PSRLWri + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psrlq + llvm_name: PSRLQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: psrlq + llvm_name: PSRLQri + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psrld + llvm_name: PSRLDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: psrld + llvm_name: PSRLDri + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psrldq + llvm_name: PSRLDQri + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psraw + llvm_name: PSRAWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: psraw + llvm_name: PSRAWri + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psrad + llvm_name: PSRADrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: psrad + llvm_name: PSRADri + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psllw + llvm_name: PSLLWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: psllw + llvm_name: PSLLWri + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psllq + llvm_name: PSLLQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: psllq + llvm_name: PSLLQri + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: pslld + llvm_name: PSLLDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pslld + llvm_name: PSLLDri + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: pslldq + llvm_name: PSLLDQri + operands: + - class: immediate + imd: int + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psignw + llvm_name: PSIGNWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: psignd + llvm_name: PSIGNDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: psignb + llvm_name: PSIGNBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: pshuflw + llvm_name: PSHUFLWri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pshufhw + llvm_name: PSHUFHWri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pshufd + llvm_name: PSHUFDri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pshufb + llvm_name: PSHUFBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: psadbw + llvm_name: PSADBWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: por + llvm_name: PORrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: popcnt + llvm_name: POPCNT64rr + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: pmuludq + llvm_name: PMULUDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pmullw + llvm_name: PMULLWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pmulld + llvm_name: PMULLDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pmulhw + llvm_name: PMULHWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pmulhuw + llvm_name: PMULHUWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pmulhrsw + llvm_name: PMULHRSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pmuldq + llvm_name: PMULDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pmovzxwq + llvm_name: PMOVZXWQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pmovzxwd + llvm_name: PMOVZXWDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pmovzxdq + llvm_name: PMOVZXDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pmovzxbw + llvm_name: PMOVZXBWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pmovzxbq + llvm_name: PMOVZXBQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pmovzxbd + llvm_name: PMOVZXBDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pmovsxwq + llvm_name: PMOVSXWQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pmovsxwd + llvm_name: PMOVSXWDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pmovsxdq + llvm_name: PMOVSXDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pmovsxbw + llvm_name: PMOVSXBWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pmovsxbq + llvm_name: PMOVSXBQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pmovsxbd + llvm_name: PMOVSXBDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pmovmskb + llvm_name: PMOVMSKBrr + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 6 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pminuw + llvm_name: PMINUWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pminud + llvm_name: PMINUDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pminub + llvm_name: PMINUBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: pminsw + llvm_name: PMINSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: pminsd + llvm_name: PMINSDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pminsb + llvm_name: PMINSBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pmaxuw + llvm_name: PMAXUWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pmaxud + llvm_name: PMAXUDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pmaxub + llvm_name: PMAXUBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: pmaxsw + llvm_name: PMAXSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: pmaxsd + llvm_name: PMAXSDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pmaxsb + llvm_name: PMAXSBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pmaddwd + llvm_name: PMADDWDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pmaddubsw + llvm_name: PMADDUBSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pinsrw + llvm_name: PINSRWrri + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + latency: 8 + port_pressure: [[4, ['0', '1', '2', '3']]] + throughput: 1.0 + uops: ~ +- name: pinsrq + llvm_name: PINSRQrri + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + latency: 8 + port_pressure: [[4, ['0', '1', '2', '3']]] + throughput: 1.0 + uops: ~ +- name: pinsrd + llvm_name: PINSRDrri + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + latency: 8 + port_pressure: [[4, ['0', '1', '2', '3']]] + throughput: 1.0 + uops: ~ +- name: pinsrb + llvm_name: PINSRBrri + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: xmm + latency: 8 + port_pressure: [[4, ['0', '1', '2', '3']]] + throughput: 1.0 + uops: ~ +- name: phsubw + llvm_name: PHSUBWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[8, ['0', '1', '2', '3']]] + throughput: 2.0 + uops: ~ +- name: phsubsw + llvm_name: PHSUBSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[8, ['0', '1', '2', '3']]] + throughput: 2.0 + uops: ~ +- name: phsubd + llvm_name: PHSUBDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[8, ['0', '1', '2', '3']]] + throughput: 2.0 + uops: ~ +- name: phminposuw + llvm_name: PHMINPOSUWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: phaddw + llvm_name: PHADDWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[8, ['0', '1', '2', '3']]] + throughput: 2.0 + uops: ~ +- name: phaddsw + llvm_name: PHADDSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[8, ['0', '1', '2', '3']]] + throughput: 2.0 + uops: ~ +- name: phaddd + llvm_name: PHADDDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[8, ['0', '1', '2', '3']]] + throughput: 2.0 + uops: ~ +- name: pextrw + llvm_name: PEXTRWrri_REV + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, ['0', '1', '2', '3']], [1, ['4', '5']]] + throughput: 0.75 + uops: ~ +- name: pextrq + llvm_name: PEXTRQrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, ['0', '1', '2', '3']], [1, ['4', '5']]] + throughput: 0.75 + uops: ~ +- name: pextrd + llvm_name: PEXTRDrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, ['0', '1', '2', '3']], [1, ['4', '5']]] + throughput: 0.75 + uops: ~ +- name: pextrb + llvm_name: PEXTRBrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, ['0', '1', '2', '3']], [1, ['4', '5']]] + throughput: 0.75 + uops: ~ +- name: pext + llvm_name: PEXT64rr_EVEX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: pdep + llvm_name: PDEP64rr_EVEX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: pcmpistrm + llvm_name: PCMPISTRMrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: pcmpgtw + llvm_name: PCMPGTWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: pcmpgtq + llvm_name: PCMPGTQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pcmpgtd + llvm_name: PCMPGTDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: pcmpgtb + llvm_name: PCMPGTBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: pcmpeqw + llvm_name: PCMPEQWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: pcmpeqq + llvm_name: PCMPEQQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pcmpeqd + llvm_name: PCMPEQDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: pcmpeqb + llvm_name: PCMPEQBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: pblendw + llvm_name: PBLENDWrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pblendvb + llvm_name: PBLENDVBrr0 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pavgw + llvm_name: PAVGWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: pavgb + llvm_name: PAVGBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: pand + llvm_name: PANDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: pandn + llvm_name: PANDNrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: palignr + llvm_name: PALIGNRrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: paddw + llvm_name: PADDWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: paddusw + llvm_name: PADDUSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: paddusb + llvm_name: PADDUSBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: paddsw + llvm_name: PADDSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: paddsb + llvm_name: PADDSBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: paddq + llvm_name: PADDQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: paddd + llvm_name: PADDDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: paddb + llvm_name: PADDBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: packuswb + llvm_name: PACKUSWBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: packusdw + llvm_name: PACKUSDWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: packsswb + llvm_name: PACKSSWBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: packssdw + llvm_name: PACKSSDWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pabsw + llvm_name: PABSWrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: pabsd + llvm_name: PABSDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: pabsb + llvm_name: PABSBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: orps + llvm_name: ORPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: orpd + llvm_name: ORPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: or + llvm_name: OR8rr + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: or + llvm_name: OR8ri8 + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: or + llvm_name: OR8i8 + operands: + - class: immediate + imd: int + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: not + llvm_name: NOT8r + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: neg + llvm_name: NEG8r + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: mulx + llvm_name: MULX64rr_EVEX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 7 + port_pressure: [[2, ['6', '7', '8']]] + throughput: 0.6666666666666666 + uops: ~ +- name: mulss + llvm_name: MULSSrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: mulsd + llvm_name: MULSDrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: mulps + llvm_name: MULPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: mulpd + llvm_name: MULPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: mul + llvm_name: MUL16r + operands: + - class: register + name: gpr + latency: 3.6 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: movq + llvm_name: MOVZPQILo2PQIrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: movss + llvm_name: MOVSSrr_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: movd + llvm_name: MOVSS2DIrr + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 6 + port_pressure: [[1, ['4', '5']]] + throughput: 0.5 + uops: ~ +- name: movsldup + llvm_name: MOVSLDUPrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: movshdup + llvm_name: MOVSHDUPrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: movq + llvm_name: MOVSDto64rr + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 6 + port_pressure: [[1, ['4', '5']]] + throughput: 0.5 + uops: ~ +- name: movsd + llvm_name: MOVSDrr_REV + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: movmskps + llvm_name: MOVMSKPSrr + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 6 + port_pressure: [[1, ['4', '5']]] + throughput: 0.5 + uops: ~ +- name: movmskpd + llvm_name: MOVMSKPDrr + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 6 + port_pressure: [[1, ['4', '5']]] + throughput: 0.5 + uops: ~ +- name: movlhps + llvm_name: MOVLHPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: movhlps + llvm_name: MOVHLPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: movddup + llvm_name: MOVDDUPrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [] + throughput: 0 + uops: ~ +- name: mov + llvm_name: MOV64rr_REV + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 0.1 + port_pressure: [] + throughput: 0.09 + uops: ~ +- name: pxor + llvm_name: MMX_PXORrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: punpcklwd + llvm_name: MMX_PUNPCKLWDrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: punpckldq + llvm_name: MMX_PUNPCKLDQrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: punpcklbw + llvm_name: MMX_PUNPCKLBWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: punpckhwd + llvm_name: MMX_PUNPCKHWDrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: punpckhdq + llvm_name: MMX_PUNPCKHDQrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: punpckhbw + llvm_name: MMX_PUNPCKHBWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: psubw + llvm_name: MMX_PSUBWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: psubusw + llvm_name: MMX_PSUBUSWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: psubusb + llvm_name: MMX_PSUBUSBrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: psubsw + llvm_name: MMX_PSUBSWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: psubsb + llvm_name: MMX_PSUBSBrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: psubq + llvm_name: MMX_PSUBQrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: psubd + llvm_name: MMX_PSUBDrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: psubb + llvm_name: MMX_PSUBBrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: psrlw + llvm_name: MMX_PSRLWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psrlw + llvm_name: MMX_PSRLWri + operands: + - class: immediate + imd: int + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psrlq + llvm_name: MMX_PSRLQrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psrlq + llvm_name: MMX_PSRLQri + operands: + - class: immediate + imd: int + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psrld + llvm_name: MMX_PSRLDrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psrld + llvm_name: MMX_PSRLDri + operands: + - class: immediate + imd: int + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psraw + llvm_name: MMX_PSRAWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psraw + llvm_name: MMX_PSRAWri + operands: + - class: immediate + imd: int + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psrad + llvm_name: MMX_PSRADrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: psrad + llvm_name: MMX_PSRADri + operands: + - class: immediate + imd: int + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psllw + llvm_name: MMX_PSLLWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: psllw + llvm_name: MMX_PSLLWri + operands: + - class: immediate + imd: int + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psllq + llvm_name: MMX_PSLLQrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: psllq + llvm_name: MMX_PSLLQri + operands: + - class: immediate + imd: int + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: pslld + llvm_name: MMX_PSLLDrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pslld + llvm_name: MMX_PSLLDri + operands: + - class: immediate + imd: int + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: psignw + llvm_name: MMX_PSIGNWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: psignd + llvm_name: MMX_PSIGNDrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: psignb + llvm_name: MMX_PSIGNBrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pshufw + llvm_name: MMX_PSHUFWri + operands: + - class: immediate + imd: int + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '1', '2', '3']]] + throughput: 0.25 + uops: ~ +- name: pshufb + llvm_name: MMX_PSHUFBrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: psadbw + llvm_name: MMX_PSADBWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: por + llvm_name: MMX_PORrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pmuludq + llvm_name: MMX_PMULUDQrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pmullw + llvm_name: MMX_PMULLWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pmulhw + llvm_name: MMX_PMULHWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pmulhuw + llvm_name: MMX_PMULHUWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pmulhrsw + llvm_name: MMX_PMULHRSWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pmovmskb + llvm_name: MMX_PMOVMSKBrr + operands: + - class: register + name: mmx + - class: register + name: gpr + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pminub + llvm_name: MMX_PMINUBrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pminsw + llvm_name: MMX_PMINSWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pmaxub + llvm_name: MMX_PMAXUBrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pmaxsw + llvm_name: MMX_PMAXSWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pmaddwd + llvm_name: MMX_PMADDWDrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pmaddubsw + llvm_name: MMX_PMADDUBSWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 3 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: pinsrw + llvm_name: MMX_PINSRWrri + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: mmx + latency: 8 + port_pressure: [[4, ['0', '1', '2', '3']]] + throughput: 1.0 + uops: ~ +- name: phsubw + llvm_name: MMX_PHSUBWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[8, ['0', '1', '2', '3']]] + throughput: 2.0 + uops: ~ +- name: phsubsw + llvm_name: MMX_PHSUBSWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 4 + port_pressure: [[8, ['0', '1', '2', '3']]] + throughput: 2.0 + uops: ~ +- name: phsubd + llvm_name: MMX_PHSUBDrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[8, ['0', '1', '2', '3']]] + throughput: 2.0 + uops: ~ +- name: phaddw + llvm_name: MMX_PHADDWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[8, ['0', '1', '2', '3']]] + throughput: 2.0 + uops: ~ +- name: phaddsw + llvm_name: MMX_PHADDSWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 4 + port_pressure: [[8, ['0', '1', '2', '3']]] + throughput: 2.0 + uops: ~ +- name: phaddd + llvm_name: MMX_PHADDDrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[8, ['0', '1', '2', '3']]] + throughput: 2.0 + uops: ~ +- name: pextrw + llvm_name: MMX_PEXTRWrri + operands: + - class: immediate + imd: int + - class: register + name: mmx + - class: register + name: gpr + latency: 10 + port_pressure: [[1, ['0', '1', '2', '3']], [1, ['4', '5']]] + throughput: 0.75 + uops: ~ +- name: pcmpgtw + llvm_name: MMX_PCMPGTWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pcmpgtd + llvm_name: MMX_PCMPGTDrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pcmpgtb + llvm_name: MMX_PCMPGTBrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pcmpeqw + llvm_name: MMX_PCMPEQWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pcmpeqd + llvm_name: MMX_PCMPEQDrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pcmpeqb + llvm_name: MMX_PCMPEQBrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: pavgw + llvm_name: MMX_PAVGWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '1', '2', '3']]] + throughput: 0.25 + uops: ~ +- name: pavgb + llvm_name: MMX_PAVGBrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '1', '2', '3']]] + throughput: 0.25 + uops: ~ +- name: pand + llvm_name: MMX_PANDrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '1', '2', '3']]] + throughput: 0.25 + uops: ~ +- name: pandn + llvm_name: MMX_PANDNrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '1', '2', '3']]] + throughput: 0.25 + uops: ~ +- name: palignr + llvm_name: MMX_PALIGNRrri + operands: + - class: immediate + imd: int + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: paddw + llvm_name: MMX_PADDWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: paddusw + llvm_name: MMX_PADDUSWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: paddusb + llvm_name: MMX_PADDUSBrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: paddsw + llvm_name: MMX_PADDSWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: paddsb + llvm_name: MMX_PADDSBrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: paddq + llvm_name: MMX_PADDQrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: paddd + llvm_name: MMX_PADDDrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: paddb + llvm_name: MMX_PADDBrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '1', '2', '3']]] + throughput: 0.25 + uops: ~ +- name: packuswb + llvm_name: MMX_PACKUSWBrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: packsswb + llvm_name: MMX_PACKSSWBrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: packssdw + llvm_name: MMX_PACKSSDWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: pabsw + llvm_name: MMX_PABSWrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: pabsd + llvm_name: MMX_PABSDrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: pabsb + llvm_name: MMX_PABSBrr + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: movq + llvm_name: MMX_MOVQ64rr_REV + operands: + - class: register + name: mmx + - class: register + name: mmx + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: minss + llvm_name: MINSSrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: minsd + llvm_name: MINSDrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: minps + llvm_name: MINPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: minpd + llvm_name: MINPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: maxss + llvm_name: MAXSSrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: maxsd + llvm_name: MAXSDrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: maxps + llvm_name: MAXPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: maxpd + llvm_name: MAXPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: lzcnt + llvm_name: LZCNT64rr + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: kxorw + llvm_name: KXORWkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kxorq + llvm_name: KXORQkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kxord + llvm_name: KXORDkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kxorb + llvm_name: KXORBkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kxnorw + llvm_name: KXNORWkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kxnorq + llvm_name: KXNORQkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kxnord + llvm_name: KXNORDkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kxnorb + llvm_name: KXNORBkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kshiftrw + llvm_name: KSHIFTRWki + operands: + - class: immediate + imd: int + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kshiftrq + llvm_name: KSHIFTRQki + operands: + - class: immediate + imd: int + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kshiftrd + llvm_name: KSHIFTRDki + operands: + - class: immediate + imd: int + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kshiftrb + llvm_name: KSHIFTRBki + operands: + - class: immediate + imd: int + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kshiftlw + llvm_name: KSHIFTLWki + operands: + - class: immediate + imd: int + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kshiftlq + llvm_name: KSHIFTLQki + operands: + - class: immediate + imd: int + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kshiftld + llvm_name: KSHIFTLDki + operands: + - class: immediate + imd: int + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kshiftlb + llvm_name: KSHIFTLBki + operands: + - class: immediate + imd: int + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: korw + llvm_name: KORWkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: korq + llvm_name: KORQkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kord + llvm_name: KORDkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: korb + llvm_name: KORBkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: knotw + llvm_name: KNOTWkk + operands: + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: knotq + llvm_name: KNOTQkk + operands: + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: knotd + llvm_name: KNOTDkk + operands: + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: knotb + llvm_name: KNOTBkk + operands: + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kmovw + llvm_name: KMOVWrk + operands: + - class: register + name: k + - class: register + name: gpr + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: kmovw + llvm_name: KMOVWkr_EVEX + operands: + - class: register + name: gpr + - class: register + name: k + latency: 8 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: kmovw + llvm_name: KMOVWkk + operands: + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kmovq + llvm_name: KMOVQrk_EVEX + operands: + - class: register + name: k + - class: register + name: gpr + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: kmovq + llvm_name: KMOVQkr_EVEX + operands: + - class: register + name: gpr + - class: register + name: k + latency: 8 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: kmovq + llvm_name: KMOVQkk + operands: + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kmovd + llvm_name: KMOVDrk_EVEX + operands: + - class: register + name: k + - class: register + name: gpr + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: kmovd + llvm_name: KMOVDkr_EVEX + operands: + - class: register + name: gpr + - class: register + name: k + latency: 8 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: kmovd + llvm_name: KMOVDkk + operands: + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kmovb + llvm_name: KMOVBrk_EVEX + operands: + - class: register + name: k + - class: register + name: gpr + latency: 8 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: kmovb + llvm_name: KMOVBkr_EVEX + operands: + - class: register + name: gpr + - class: register + name: k + latency: 8 + port_pressure: [[2, ['1', '2']]] + throughput: 1.0 + uops: ~ +- name: kmovb + llvm_name: KMOVBkk + operands: + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kandw + llvm_name: KANDWkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kandq + llvm_name: KANDQkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kandnw + llvm_name: KANDNWkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kandnq + llvm_name: KANDNQkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kandnd + llvm_name: KANDNDkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kandnb + llvm_name: KANDNBkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kandd + llvm_name: KANDDkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kandb + llvm_name: KANDBkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kaddw + llvm_name: KADDWkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kaddq + llvm_name: KADDQkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kaddd + llvm_name: KADDDkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: kaddb + llvm_name: KADDBkk + operands: + - class: register + name: k + - class: register + name: k + - class: register + name: k + latency: 1 + port_pressure: [[1, ['0', '3']]] + throughput: 0.5 + uops: ~ +- name: insertq + llvm_name: INSERTQI + operands: + - class: immediate + imd: int + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: insertq + llvm_name: INSERTQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: insertps + llvm_name: INSERTPSrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: inc + llvm_name: INC8r + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: imul + llvm_name: IMUL16r + operands: + - class: register + name: gpr + latency: 3.6 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: imul + llvm_name: IMUL64rri8 + operands: + - class: immediate + imd: int + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: imul + llvm_name: IMUL64rr + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: hsubps + llvm_name: HSUBPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: hsubpd + llvm_name: HSUBPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: haddps + llvm_name: HADDPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: haddpd + llvm_name: HADDPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 5 + port_pressure: [[1, ['1', '3']], [7, ['0', '1', '2', '3']]] + throughput: 2.25 + uops: ~ +- name: gf2p8mulb + llvm_name: GF2P8MULBrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: gf2p8affineqb + llvm_name: GF2P8AFFINEQBrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: gf2p8affineinvqb + llvm_name: GF2P8AFFINEINVQBrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['1', '2']]] + throughput: 0.5 + uops: ~ +- name: extrq + llvm_name: EXTRQI + operands: + - class: immediate + imd: int + - class: immediate + imd: int + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['0', '1', '2', '3']], [1, ['4', '5']]] + throughput: 0.75 + uops: ~ +- name: extrq + llvm_name: EXTRQ + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, ['0', '1', '2', '3']], [1, ['4', '5']]] + throughput: 0.75 + uops: ~ +- name: extractps + llvm_name: EXTRACTPSrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: gpr + latency: 8 + port_pressure: [[1, ['0', '1', '2', '3']], [1, ['4', '5']]] + throughput: 0.75 + uops: ~ +- name: divss + llvm_name: DIVSSrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[1, '02'], [5, [0DV, 2DV]]] + throughput: 2.5 + uops: ~ +- name: divsd + llvm_name: DIVSDrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '02'], [8, [0DV, 2DV]]] + throughput: 4.0 + uops: ~ +- name: divps + llvm_name: DIVPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 10 + port_pressure: [[1, '02'], [5, [0DV, 2DV]]] + throughput: 2.5 + uops: ~ +- name: divpd + llvm_name: DIVPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 13 + port_pressure: [[1, '02'], [8, [0DV, 2DV]]] + throughput: 4.0 + uops: ~ +- name: dec + llvm_name: DEC8r + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: cvttss2si + llvm_name: CVTTSS2SIrr_Int + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 9 + port_pressure: [[1, ['1', '3']], [1, ['4', '5']]] + throughput: 1.0 + uops: ~ +- name: cvttsd2si + llvm_name: CVTTSD2SIrr_Int + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 9 + port_pressure: [[1, ['1', '3']], [1, ['4', '5']]] + throughput: 1.0 + uops: ~ +- name: cvttps2dq + llvm_name: CVTTPS2DQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: cvttpd2dq + llvm_name: CVTTPD2DQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: cvtss2si + llvm_name: CVTSS2SIrr + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 9 + port_pressure: [[1, ['1', '3']], [1, ['4', '5']]] + throughput: 1.0 + uops: ~ +- name: cvtss2sd + llvm_name: CVTSS2SDrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: cvtsi2ss + llvm_name: CVTSI642SSrr_Int + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 9 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: cvtsi2sd + llvm_name: CVTSI642SDrr_Int + operands: + - class: register + name: gpr + - class: register + name: xmm + latency: 9 + port_pressure: [[2, ['1', '3']]] + throughput: 1.0 + uops: ~ +- name: cvtsd2ss + llvm_name: CVTSD2SSrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: cvtsd2si + llvm_name: CVTSD2SIrr_Int + operands: + - class: register + name: xmm + - class: register + name: gpr + latency: 9 + port_pressure: [[1, ['1', '3']], [1, ['4', '5']]] + throughput: 1.0 + uops: ~ +- name: cvtps2pd + llvm_name: CVTPS2PDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: cvtps2dq + llvm_name: CVTPS2DQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: cvtpd2ps + llvm_name: CVTPD2PSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: cvtpd2dq + llvm_name: CVTPD2DQrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: cvtdq2ps + llvm_name: CVTDQ2PSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: cvtdq2pd + llvm_name: CVTDQ2PDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 3 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: crc32 + llvm_name: CRC32r64r8_EVEX + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 3 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: cqo + llvm_name: CQO + operands: [] + latency: 0.3 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: cmpss + llvm_name: CMPSSrri_Int + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: cmpsd + llvm_name: CMPSDrri_Int + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: cmpps + llvm_name: CMPPSrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: cmppd + llvm_name: CMPPDrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: cmp + llvm_name: CMP8rr_REV + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: cmp + llvm_name: CMP8ri8 + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: cmp + llvm_name: CMP8i8 + operands: + - class: immediate + imd: int + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: cmov + llvm_name: CMOV64rr + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 2 + port_pressure: [[1, ['9', '10', '11']]] + throughput: 0.3333333333333333 + uops: ~ +- name: cdq + llvm_name: CDQ + operands: [] + latency: 0.3 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: bzhi + llvm_name: BZHI64rr_EVEX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: bswap + llvm_name: BSWAP64r + operands: + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: blendvps + llvm_name: BLENDVPSrr0 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[1, ['0', '2']]] + throughput: 0.5 + uops: ~ +- name: blendvpd + llvm_name: BLENDVPDrr0 + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 8 + port_pressure: [[1, ['0', '2']]] + throughput: 0.5 + uops: ~ +- name: blendps + llvm_name: BLENDPSrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['0', '1', '2', '3']]] + throughput: 0.25 + uops: ~ +- name: blendpd + llvm_name: BLENDPDrri + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: bextr + llvm_name: BEXTR64rr_EVEX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: andps + llvm_name: ANDPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: andpd + llvm_name: ANDPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: andnps + llvm_name: ANDNPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '0123']] + throughput: 0.25 + uops: ~ +- name: andnpd + llvm_name: ANDNPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: andn + llvm_name: ANDN64rr_EVEX + operands: + - class: register + name: gpr + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: and + llvm_name: AND64rr_REV + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: and + llvm_name: AND8ri8 + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: and + llvm_name: AND8i8 + operands: + - class: immediate + imd: int + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: aeskeygenassist + llvm_name: AESKEYGENASSIST128rr + operands: + - class: immediate + imd: int + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: aesimc + llvm_name: AESIMCrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: aesenc + llvm_name: AESENCrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: aesenclast + llvm_name: AESENCLASTrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: aesdec + llvm_name: AESDECrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: aesdeclast + llvm_name: AESDECLASTrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 4 + port_pressure: [[1, '02']] + throughput: 0.5 + uops: ~ +- name: adox + llvm_name: ADOX64rr_EVEX + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8']]] + throughput: 0.3333333333333333 + uops: ~ +- name: addsubps + llvm_name: ADDSUBPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: addsubpd + llvm_name: ADDSUBPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: addss + llvm_name: ADDSSrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: addsd + llvm_name: ADDSDrr_Int + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: addps + llvm_name: ADDPSrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: addpd + llvm_name: ADDPDrr + operands: + - class: register + name: xmm + - class: register + name: xmm + latency: 2 + port_pressure: [[1, '13']] + throughput: 0.5 + uops: ~ +- name: add + llvm_name: ADD8rr_REV + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: add + llvm_name: ADD8ri8 + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: add + llvm_name: ADD8i8 + operands: + - class: immediate + imd: int + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: adc + llvm_name: ADC64rr_REV + operands: + - class: register + name: gpr + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ +- name: adc + llvm_name: ADC8ri8 + operands: + - class: immediate + imd: int + - class: register + name: gpr + latency: 1 + port_pressure: [[1, ['6', '7', '8', '9', '10', '11']]] + throughput: 0.16666666666666666 + uops: ~ diff --git a/osaca/osaca.py b/osaca/osaca.py index 4605d9c..0222e8b 100644 --- a/osaca/osaca.py +++ b/osaca/osaca.py @@ -35,6 +35,7 @@ SUPPORTED_ARCHS = [ "ZEN2", "ZEN3", "ZEN4", + "ZEN5", "TX2", "N1", "A64FX", diff --git a/osaca/parser/instruction_form.py b/osaca/parser/instruction_form.py index 5a04c7a..6dc4cfd 100644 --- a/osaca/parser/instruction_form.py +++ b/osaca/parser/instruction_form.py @@ -5,6 +5,7 @@ class InstructionForm: def __init__( self, mnemonic=None, + llvm_name=None, operands=[], hidden_operands=[], directive_id=None, @@ -22,6 +23,7 @@ class InstructionForm: normalized=False, ): self._mnemonic = mnemonic + self._llvm_name = llvm_name self._operands = operands self._hidden_operands = hidden_operands self._directive_id = directive_id @@ -56,6 +58,10 @@ class InstructionForm: def mnemonic(self): return self._mnemonic + @property + def llvm_name(self): + return self._llvm_name + @property def label(self): return self._label_id @@ -160,6 +166,10 @@ class InstructionForm: def mnemonic(self, mnemonic): self._mnemonic = mnemonic + @llvm_name.setter + def llvm_name(self, llvm_name): + self._llvm_name = llvm_name + @label.setter def label(self, label): self._label_id = label @@ -203,6 +213,7 @@ class InstructionForm: def __str__(self): attributes = { "mnemonic": self.mnemonic, + "llvm_name": self._llvm_name, "operands": self.operands, "hidden_operands": self.hidden_operands, "directive_id": self.directive, @@ -226,13 +237,24 @@ class InstructionForm: def __eq__(self, other): if isinstance(other, InstructionForm): - return ( - self._mnemonic == other._mnemonic - and self._directive_id == other._directive_id - and self._comment_id == other._comment_id - and self._label_id == other._label_id - and self._line == other._line - and self._line_number == other._line_number - and self._semantic_operands == other._semantic_operands - ) + if len(self._semantic_operands["source"] + self._semantic_operands["destination"] + self._semantic_operands["src_dst"]) > 0: + return ( + self._mnemonic == other._mnemonic + and self._directive_id == other._directive_id + and self._comment_id == other._comment_id + and self._label_id == other._label_id + and self._line == other._line + and self._line_number == other._line_number + and self._semantic_operands == other._semantic_operands + ) + else: + return ( + self._mnemonic == other._mnemonic + and self._directive_id == other._directive_id + and self._comment_id == other._comment_id + and self._label_id == other._label_id + and self._line == other._line + and self._line_number == other._line_number + and self._operands == other._operands + ) return False diff --git a/osaca/semantics/hw_model.py b/osaca/semantics/hw_model.py index d298b32..a7b3f8d 100644 --- a/osaca/semantics/hw_model.py +++ b/osaca/semantics/hw_model.py @@ -338,6 +338,7 @@ class MachineModel(object): def set_instruction( self, mnemonic, + llvm_name=None, operands=None, latency=None, port_pressure=None, @@ -353,6 +354,7 @@ class MachineModel(object): self._data["instruction_forms_dict"][mnemonic].append(instr_data) instr_data.mnemonic = mnemonic + instr_data.llvm_name = llvm_name instr_data.operands = operands instr_data.latency = latency instr_data.port_pressure = port_pressure @@ -365,6 +367,7 @@ class MachineModel(object): raise KeyError self.set_instruction( entry.mnemonic, + entry.llvm_name, entry.operands, entry.latency, entry.port_pressure, @@ -456,6 +459,7 @@ class MachineModel(object): "zen2": "x86", "zen3": "x86", "zen4": "x86", + "zen5": "x86", "con": "x86", # Intel Conroe "wol": "x86", # Intel Wolfdale "snb": "x86", @@ -521,15 +525,24 @@ class MachineModel(object): for key, value in instruction_form.__dict__.items() if not callable(value) and not key.startswith("__") ) - if instruction_form["port_pressure"] is not None: - cs = ruamel.yaml.comments.CommentedSeq(instruction_form["port_pressure"]) - cs.fa.set_flow_style() - instruction_form["port_pressure"] = cs + iform = { + "name": instruction_form["name"] if "name" in instruction_form else instruction_form["mnemonic"] + } + if "llvm_name" in instruction_form: + iform["llvm_name"] = instruction_form["llvm_name"] dict_operands = [] for op in instruction_form["operands"]: dict_operands.append(self.class_to_dict(op)) - instruction_form["operands"] = dict_operands - formatted_instruction_forms.append(instruction_form) + iform["operands"] = dict_operands + iform["latency"] = instruction_form["latency"] + if instruction_form["port_pressure"] is not None: + cs = ruamel.yaml.comments.CommentedSeq(instruction_form["port_pressure"]) + cs.fa.set_flow_style() + iform["port_pressure"] = cs + iform["throughput"] = instruction_form["throughput"] + if "uops" in instruction_form: + iform["uops"] = instruction_form["uops"] + formatted_instruction_forms.append(iform) # Replace load_throughput with styled version for RoundtripDumper formatted_load_throughput = []