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fix a bug about orr in tsv110

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Qingcai Jiang
2022-03-20 14:53:34 +08:00
parent 9c966c2359
commit fa06b9ccac
2 changed files with 24 additions and 14 deletions
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3
osaca/parser/parser_AArch64.py
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@@ -104,6 +104,7 @@ class ParserAArch64(BaseParser):
^ pp.CaselessLiteral("ror")
^ pp.CaselessLiteral("sxtw")
^ pp.CaselessLiteral("uxtw")
^ pp.CaselessLiteral("uxtb")
^ pp.CaselessLiteral("mul vl")
)
arith_immediate = pp.Group(
@@ -384,7 +385,7 @@ class ParserAArch64(BaseParser):
base["prefix"] = "x"
if index is not None and "name" in index and index["name"] == "sp":
index["prefix"] = "x"
valid_shift_ops = ["lsl", "uxtw", "sxtw"]
valid_shift_ops = ["lsl", "uxtw", "uxtb", "sxtw"]
if "index" in memory_address:
if "shift" in memory_address["index"]:
if memory_address["index"]["shift_op"].lower() in valid_shift_ops: