diff --git a/osaca/data/vulcan.yml b/osaca/data/vulcan.yml
index a9c354c..783a993 100644
--- a/osaca/data/vulcan.yml
+++ b/osaca/data/vulcan.yml
@@ -161,6 +161,13 @@ instruction_forms:
       throughput: 0.5
       latency: 6.0  #  0   0DV    1   1DV   2    3    4    5
       port_pressure: [0.5, 0.0, 0.5, 0.0, 0.0, 0.0, 0.0, 0.0]
+    - latency: ~
+      name: "fmov"
+      operands:
+      - {class: "register", prefix: "s"}
+      - {class: "immediate", imd: "double"}
+      port_pressure: [0.5, 0.0, 0.5, 0.0, 0.0, 0.0, 0.0, 0.0]
+      throughput: 0.5
     - name: "fmul"
       operands:
         - class: "register"
@@ -366,6 +373,22 @@ instruction_forms:
       throughput: 0.5
       latency: 5.0  #  0   0DV   1   1DV   2    3    4    5
       port_pressure: [0.5, 0.0, 0.5, 0.0, 0.0, 0.0, 0.0, 0.0]
+    - name: "prfm"
+      operands:
+        - class: "prfop"
+          type: "pld"
+          target: "l1"
+          policy: "keep"
+        - class: "memory"
+          base: "x"
+          offset: "imd"
+          index: ~
+          scale: 1
+          pre-indexed: false
+          post-indexed: false
+      throughput: ~
+      latency: ~
+      port_pressure: ~
     - name: "stp"
       operands:
         - class: "register"
diff --git a/tests/test_files/kernel-AArch64.s b/tests/test_files/kernel-AArch64.s
index caed9d2..72c9a16 100644
--- a/tests/test_files/kernel-AArch64.s
+++ b/tests/test_files/kernel-AArch64.s
@@ -1,3 +1,5 @@
+// mov x1, #111
+// .byte 213,3,32,31
 .LBB0_32:
     ldp q4, q5, [x9, #-32]
     ldp q6, q7, [x9], #64
@@ -20,5 +22,6 @@
     fmov    s0, -1.0e+0
     fmov    s1, #2.0f
     prfm    pldl1keep, [x26, #2112]
-
     b.ne    .LBB0_32
+// mov x1, #222
+// .byte 213,3,32,31
diff --git a/tests/test_semantics.py b/tests/test_semantics.py
index a6db1e4..bf8cf73 100755
--- a/tests/test_semantics.py
+++ b/tests/test_semantics.py
@@ -131,24 +131,24 @@ class TestSemanticTools(unittest.TestCase):
     def test_kernelDG_AArch64(self):
         dg = KernelDG(self.kernel_AArch64, self.parser_AArch64, self.machine_model_tx2)
         self.assertTrue(nx.algorithms.dag.is_directed_acyclic_graph(dg.dg))
-        self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=2)), {6, 7})
-        self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=3)), {8, 9})
-        self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=4)), {5, 6, 7})
-        self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=5)), {8, 9})
-        self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=6)), 12)
-        self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=7)), 13)
-        self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=8)), 15)
-        self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=9)), 16)
-        self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=10)), {12, 13})
-        self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=11)), {15, 16})
-        self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=12)), 14)
-        self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=13)), 14)
-        self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=14))), 0)
-        self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=15)), 17)
-        self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=16)), 17)
-        self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=17))), 0)
-        self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=18))), 0)
+        self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=4)), {8, 9})
+        self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=5)), {10, 11})
+        self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=6)), {7, 8, 9})
+        self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=7)), {10, 11})
+        self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=8)), 14)
+        self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=9)), 15)
+        self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=10)), 17)
+        self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=11)), 18)
+        self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=12)), {14, 15})
+        self.assertEqual(set(dg.get_dependent_instruction_forms(line_number=13)), {17, 18})
+        self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=14)), 16)
+        self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=15)), 16)
+        self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=16))), 0)
+        self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=17)), 19)
+        self.assertEqual(next(dg.get_dependent_instruction_forms(line_number=18)), 19)
         self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=19))), 0)
+        self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=20))), 0)
+        self.assertEqual(len(list(dg.get_dependent_instruction_forms(line_number=21))), 0)
 
     def test_is_read_is_written_x86(self):
         # independent form HW model