From fd628a0dde07444bec35ad53cb4373ac1574df13 Mon Sep 17 00:00:00 2001 From: JanLJL Date: Mon, 29 Nov 2021 17:48:16 +0100 Subject: [PATCH] unified LOAD instructions --- osaca/data/tsv110.yml | 276 +++++++++++++++++++++++++++++------------- 1 file changed, 191 insertions(+), 85 deletions(-) diff --git a/osaca/data/tsv110.yml b/osaca/data/tsv110.yml index 4aee1e0..853a824 100644 --- a/osaca/data/tsv110.yml +++ b/osaca/data/tsv110.yml @@ -48,20 +48,6 @@ instruction_forms: throughput: 0.5 latency: 4.0 port_pressure: [[1, '67']] -- name: ldr - operands: - - class: register - prefix: w - - class: memory - base: x - offset: imd - index: '*' - scale: '*' - post-indexed: false - pre-indexed: false - throughput: 0.5 - latency: 4.0 - port_pressure: [[1, '67']] - name: fmla operands: - class: register @@ -92,21 +78,6 @@ instruction_forms: port_pressure: ~ throughput: ~ uops: ~ -- name: ldr - operands: - - class: register - prefix: q - - class: memory - base: x - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ - name: fsqrt operands: - class: register @@ -137,21 +108,6 @@ instruction_forms: port_pressure: ~ throughput: 1.0 uops: ~ -- name: ldr - operands: - - class: register - prefix: x - - class: memory - base: x - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: false - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ - name: add operands: - class: register @@ -474,21 +430,6 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ -- name: ldr - operands: - - class: register - prefix: q - - class: memory - base: x - offset: ~ - index: ~ - scale: 1 - pre-indexed: false - post-indexed: true - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ - name: fmul operands: - class: register @@ -636,21 +577,186 @@ instruction_forms: port_pressure: ~ throughput: 0.5 uops: ~ +- name: ldr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: w + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: d + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 - name: ldr operands: - class: register prefix: q - class: memory base: x - offset: ~ - index: gpr - scale: 1 + offset: '*' + index: '*' + scale: '*' pre-indexed: false post-indexed: false - latency: ~ - port_pressure: ~ - throughput: ~ - uops: ~ + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67']] + uops: 1 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: true + post-indexed: false + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 +- name: ldr + operands: + - class: register + prefix: q + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: true + throughput: 0.5 + latency: 4.0 + port_pressure: [[1, '67'], [1, '012']] + uops: 2 - name: str operands: - class: register @@ -696,6 +802,21 @@ instruction_forms: latency: 0.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 +- name: str + operands: + - class: register + prefix: x + - class: memory + base: x + offset: '*' + index: '*' + scale: '*' + pre-indexed: false + post-indexed: false + throughput: 0.5 + latency: 0.0 + port_pressure: [[1, '67']] + uops: 2 - name: str operands: - class: register @@ -726,21 +847,6 @@ instruction_forms: latency: 0.0 port_pressure: [[1, '67'], [1, '012']] uops: 2 -- name: str - operands: - - class: register - prefix: x - - class: memory - base: x - offset: '*' - index: '*' - scale: '*' - pre-indexed: false - post-indexed: false - throughput: 0.5 - latency: 0.0 - port_pressure: [[1, '67']] - uops: 2 - name: str operands: - class: register @@ -770,7 +876,7 @@ instruction_forms: throughput: 0.5 latency: 0.0 port_pressure: [[1, '67'], [1, '012']] - uops: 1 + uops: 2 - name: str operands: - class: register @@ -785,7 +891,7 @@ instruction_forms: throughput: 0.5 latency: 0.0 port_pressure: [[1, '67'], [1, '012']] - uops: 1 + uops: 2 - name: str operands: - class: register @@ -815,7 +921,7 @@ instruction_forms: throughput: 0.5 latency: 0.0 port_pressure: [[1, '67'], [1, '012']] - uops: 1 + uops: 2 - name: str operands: - class: register @@ -830,4 +936,4 @@ instruction_forms: throughput: 0.5 latency: 0.0 port_pressure: [[1, '67'], [1, '012']] - uops: 1 + uops: 2