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https://github.com/RRZE-HPC/OSACA.git
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add some instructions for tsv110
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@@ -409,6 +409,30 @@ instruction_forms:
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: lsr
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: register
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prefix: w
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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- name: lsr
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operands:
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- class: register
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prefix: w
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- class: register
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prefix: w
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- class: immediate
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imd: int
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throughput: 0.3333
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latency: 1.0
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port_pressure: [[1, '012']]
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uops: 1
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# shift instructions: asr (latency and throughput from asmbench, port data from AArch64SchedTSV110.td)
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- name: asr
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operands:
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@@ -2700,6 +2724,21 @@ instruction_forms:
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latency: 5.0
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port_pressure: [[1, '67'], [1, '012']]
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uops: 2
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# memory instructions: ldur (data from AArch64SchedTSV110.td)
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- name: ldur
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operands:
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- class: register
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prefix: w
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- class: memory
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base: x
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offset: imd
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index: '*'
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scale: '*'
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post-indexed: false
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pre-indexed: false
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throughput: 0.5
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latency: 4.0
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port_pressure: [[1, '67']]
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# memory instructions: ldar[b|xr]? (data from AArch64SchedTSV110.td)
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- name: [ldar, ldarb, ldaxr]
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operands:
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@@ -2912,6 +2951,22 @@ instruction_forms:
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latency: 2.0
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port_pressure: [[1, '67'], [1, '012']]
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uops: 2
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# memory instructions: stlb (data from AArch64SchedTSV110.td)
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- name: strb
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operands:
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- class: register
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prefix: w
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- class: memory
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base: x
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offset: '*'
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index: '*'
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scale: '*'
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pre-indexed: false
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post-indexed: false
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throughput: 0.5
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latency: 1.0
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port_pressure: [[1, '67']]
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uops: 1
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# memory instructions: stlr (data from AArch64SchedTSV110.td)
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- name: stlr
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operands:
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@@ -2944,21 +2999,6 @@ instruction_forms:
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latency: 1.0
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port_pressure: [[1, '67']]
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uops: 1
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# memory instructions: ldur (data from AArch64SchedTSV110.td)
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- name: ldur
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operands:
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- class: register
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prefix: w
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- class: memory
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base: x
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offset: imd
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index: '*'
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scale: '*'
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post-indexed: false
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pre-indexed: false
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throughput: 0.5
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latency: 4.0
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port_pressure: [[1, '67']]
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# memory instructions: stur (data from AArch64SchedTSV110.td)
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- name: stur
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operands:
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