osaca_version: 0.5.0 micro_architecture: Arm Neoverse N1 arch_code: n1 isa: AArch64 ROB_size: 128 # wikichip retired_uOps_per_cycle: 8 # wikichip scheduler_size: 120 # wikichip hidden_loads: false load_latency: {w: 4.0, x: 4.0, b: 4.0, h: 4.0, s: 4.0, d: 5.0, q: 6.0, v: 5.0, z: 4.0} p_index_latency: 1 load_throughput: - {base: x, index: ~, offset: ~, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '67']]} - {base: x, index: ~, offset: imd, scale: 1, pre_indexed: false, post_indexed: true, port_pressure: [[1, '67'], [1, '123']]} - {base: x, index: ~, offset: imd, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '67']]} - {base: x, index: ~, offset: imd, scale: 1, pre_indexed: true, post_indexed: true, port_pressure: [[1, '67'], [1, '123']]} - {base: x, index: ~, offset: imd, scale: 1, pre_indexed: true, post_indexed: false, port_pressure: [[1, '67'], [1, '123']]} - {base: x, index: x, offset: ~, scale: 1, pre_indexed: false, post_indexed: true, port_pressure: [[1, '67'], [1, '123']]} - {base: x, index: x, offset: ~, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '67']]} - {base: x, index: x, offset: ~, scale: 1, pre_indexed: true, post_indexed: true, port_pressure: [[1, '67'], [1, '123']]} - {base: x, index: x, offset: ~, scale: 1, pre_indexed: true, post_indexed: false, port_pressure: [[1, '67'], [1, '123']]} - {base: x, index: x, offset: imd, scale: 1, pre_indexed: false, post_indexed: true, port_pressure: [[1, '67'], [1, '123']]} - {base: x, index: x, offset: imd, scale: 1, pre_indexed: false, post_indexed: false, port_pressure: [[1, '67']]} - {base: x, index: x, offset: imd, scale: 1, pre_indexed: true, post_indexed: true, port_pressure: [[1, '67'], [1, '123']]} - {base: x, index: x, offset: imd, scale: 1, pre_indexed: true, post_indexed: false, port_pressure: [[1, '67'], [1, '123']]} load_throughput_default: [[1, '67']] store_throughput: [] store_throughput_default: [[1, '56'], [1, '67']] ports: ['0', '1', '2', '3', '4', '4DV', '5', '6', '7'] port_model_scheme: | +----------------------------------------------------------------------------+ | 120 entries | +----------------------------------------------------------------------------+ 0 |BR 1 |IS0 2 |IS1 3 |IM0 4 |FP0 5 |FP1 6 |LDST 7 |LDST \/ \/ \/ \/ \/ \/ \/ \/ +------+ +-----+ +-----+ +-----+ +--------+ +--------+ +-------+ +-------+ |Branch| | INT | | INT | | INT | | FP ALU | | FP ALU | | AGU | | AGU | +------+ | ALU | | ALU | | ALU | +--------+ +--------+ +-------+ +-------+ +-----+ +-----+ +-----+ +--------+ +--------+ +-------+ +-------+ +-----+ +-----+ | FP MUL | | FP MUL | |LD DATA| |LD DATA| | ST | | INT | +--------+ +--------+ +-------+ +-------+ | INT | | MUL | +--------+ +---------+ +-----+ +-----+ | FP DIV | |SIMD SHFT| +-----+ +--------+ +---------+ | INT | +--------+ +--------+ | DIV | | FMA | | FMA | +-----+ +--------+ +--------+ +-----+ +--------+ +--------+ |SHIFT| | ST SIMD| | ST SIMD| +-----+ | DATA | | DATA | +-----+ +--------+ +--------+ | ST | | INT | +-----+ instruction_forms: - name: add operands: - class: register prefix: x - class: register prefix: x - class: register prefix: x throughput: 0.33333333 latency: 1.0 # 1*p123 port_pressure: [[1, '123']] - name: add operands: - class: register prefix: x - class: register prefix: x - class: immediate imd: int throughput: 0.33333333 latency: 1.0 # 1*p123 port_pressure: [[1, '123']] - name: adds operands: - class: register prefix: x - class: register prefix: x - class: immediate imd: int throughput: 0.33333333 latency: 1.0 # 1*p123 port_pressure: [[1, '132']] - name: b.ne operands: - class: identifier throughput: 1.0 latency: 0.0 port_pressure: [[1, '0']] - name: b.gt operands: - class: identifier throughput: 1.0 latency: 0.0 port_pressure: [[1, '0']] - name: bne operands: - class: identifier throughput: 1.0 latency: 0.0 port_pressure: [[1, '0']] - name: cmp operands: - class: register prefix: w - class: immediate imd: int throughput: 0.33333333 latency: 1.0 # 1*p123 port_pressure: [[1, '123']] - name: cmp operands: - class: register prefix: x - class: register prefix: x throughput: 0.3333333 latency: 1.0 # 1*p123 port_pressure: [[1, '123']] - name: dup operands: - class: register prefix: d - class: register prefix: v shape: d width: '*' throughput: 0.5 latency: 2.0 # 1*p45 port_pressure: [[1, '45']] - name: fadd operands: - class: register prefix: v shape: s width: '*' - class: register prefix: v shape: s width: '*' - class: register prefix: v shape: s width: '*' throughput: 0.5 latency: 2.0 # 1*p45 port_pressure: [[1, '45']] - name: fadd operands: - class: register prefix: d width: '*' - class: register prefix: d width: '*' - class: register prefix: d width: '*' throughput: 0.5 latency: 2.0 # 1*p45 port_pressure: [[1, '45']] - name: fadd operands: - class: register prefix: v shape: d width: '*' - class: register prefix: v shape: d width: '*' - class: register prefix: v shape: d width: '*' throughput: 0.5 latency: 2.0 # 1*p45 port_pressure: [[1, '45']] - name: fdiv operands: - class: register prefix: v shape: s width: 128 - class: register prefix: v shape: s width: 128 - class: register prefix: v shape: s width: 128 throughput: 6.0 latency: 8.0 # 1*p4+6*p4DV port_pressure: [[1, '4'], [6, [4DV]]] - name: fdiv operands: - class: register prefix: v shape: d width: 128 - class: register prefix: v shape: d width: 128 - class: register prefix: v shape: d width: 128 throughput: 10.0 latency: 12.0 # 1*p4+10*p4DV port_pressure: [[4, '0'], [10, [4DV]]] - name: fmla operands: - class: register prefix: v shape: s width: '*' - class: register prefix: v shape: s width: '*' - class: register prefix: v shape: s width: '*' throughput: 0.5 latency: 2.0 # 1*p45 port_pressure: [[1, '45']] - name: fmla operands: - class: register prefix: v shape: d width: '*' - class: register prefix: v shape: d width: '*' - class: register prefix: v shape: d width: '*' throughput: 0.5 latency: 2.0 # 1*p45 port_pressure: [[1, '45']] - name: fmov operands: - {class: register, prefix: s} - {class: immediate, imd: double} latency: ~ # 1*p45 port_pressure: [[1, '45']] throughput: 0.5 - name: fmul operands: - class: register prefix: v shape: s width: '*' - class: register prefix: v shape: s width: '*' - class: register prefix: v shape: s width: '*' throughput: 0.5 latency: 3.0 # 1*p45 port_pressure: [[1, '45']] - name: fmul operands: - class: register prefix: v shape: d width: '*' - class: register prefix: v shape: d width: '*' - class: register prefix: v shape: d width: '*' throughput: 0.5 latency: 3.0 # 1*p45 port_pressure: [[1, '45']] - name: fmul operands: - class: register prefix: d - class: register prefix: d - class: register prefix: d throughput: 0.5 latency: 3.0 # 1*p45 port_pressure: [[1, '45']] - name: frecpe operands: - class: register prefix: v shape: s width: '*' - class: register prefix: v shape: s width: '*' - class: register prefix: v shape: s width: '*' throughput: 2.0 latency: 4.0 # 1*p4 port_pressure: [[2, '4']] - name: frecpe operands: - class: register prefix: v shape: d width: '*' - class: register prefix: v shape: d width: '*' - class: register prefix: v shape: d width: '*' throughput: 1.0 latency: 3.0 # 1*p4 port_pressure: [[1, '4']] - name: fsub operands: - class: register prefix: v shape: s width: '*' - class: register prefix: v shape: s width: '*' - class: register prefix: v shape: s width: '*' throughput: 0.5 latency: 2.0 # 1*p45 port_pressure: [[1, '45']] - name: fsub operands: - class: register prefix: v shape: d width: '*' - class: register prefix: v shape: d width: '*' - class: register prefix: v shape: d width: '*' throughput: 0.5 latency: 2.0 # 1*p45 port_pressure: [[1, '45']] - name: ldp operands: - class: register prefix: d - class: register prefix: d - class: memory base: x offset: imd index: ~ scale: 1 pre_indexed: false post_indexed: false throughput: 1.0 latency: 5.0 # 2*p67, from n1 opt guide port_pressure: [[2, '67']] - name: ldp operands: - class: register prefix: d - class: register prefix: d - class: memory base: x offset: imd index: ~ scale: 1 pre_indexed: false post_indexed: true throughput: 1.0 latency: 5.0 # 2*p67+1*p123, from n1 opt guide port_pressure: [[2, '67'], [1, '123']] - name: ldp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: '*' index: '*' scale: 1 pre_indexed: false post_indexed: false throughput: 1.0 latency: 7.0 # 2*p67, from n1 opt guide port_pressure: [[2, '67']] - name: ldp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: ~ index: ~ scale: 1 pre_indexed: false post_indexed: true throughput: 1.0 latency: 7.0 # 2*p67+1*p123, from n1 opt guide port_pressure: [[2, '56'], [1, '123']] - name: ldp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: '*' index: '*' scale: '*' pre_indexed: false post_indexed: false throughput: 1.0 latency: 7.0 # 2*p67 port_pressure: [[2, '67']] - name: ldp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: '*' index: '*' scale: '*' pre_indexed: true post_indexed: false throughput: 1.0 latency: 7.0 # 2*p67+1*p123 port_pressure: [[2, '67'], [1, '123']] - name: ldp operands: - class: register prefix: d - class: register prefix: d - class: memory base: x offset: '*' index: '*' scale: '*' pre_indexed: false post_indexed: true throughput: 1.0 latency: 5.0 # 2*p67+1*p123 port_pressure: [[2, '67'], [1, '123']] - name: ldur # JL: assumed from n1 opt guide operands: - class: register prefix: q - class: memory base: x offset: '*' index: '*' scale: '*' post_indexed: false pre_indexed: false throughput: 0.5 latency: 6.0 # 1*p67 port_pressure: [[1, '67']] - name: ldr operands: - class: register prefix: q - class: memory base: x offset: '*' index: '*' scale: '*' post_indexed: false pre_indexed: false throughput: 0.5 latency: 6.0 # 1*p67 port_pressure: [[1, '67']] - name: ldr operands: - class: register prefix: d - class: memory base: x offset: '*' index: '*' scale: '*' post_indexed: false pre_indexed: false throughput: 0.5 latency: 5.0 # 1*p67 port_pressure: [[1, '67']] - name: ldr operands: - class: register prefix: d - class: memory base: x offset: imd index: '*' scale: '*' post_indexed: false pre_indexed: false throughput: 0.5 latency: 5.0 # 1*p67 port_pressure: [[1, '67']] - name: ldr operands: - class: register prefix: d - class: memory base: x offset: '*' index: '*' scale: '*' post_indexed: false pre_indexed: false throughput: 0.5 latency: 5.0 # 1*p67 port_pressure: [[1, '67']] - name: ldr operands: - class: register prefix: x - class: register prefix: x throughput: 0.0 latency: 0.0 port_pressure: [] - name: ldr operands: - class: register prefix: q - class: register prefix: q throughput: 0.0 latency: 0.0 port_pressure: [] - name: ldr operands: - class: register prefix: d - class: register prefix: d throughput: 0.0 latency: 0.0 port_pressure: [] - name: mov operands: - class: register prefix: x - class: register prefix: x throughput: 0.25 latency: 1.0 # 1*p3456 port_pressure: [[1, '3456']] - name: mov operands: - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' throughput: 0.5 latency: 2.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: d - class: register prefix: d - class: memory base: x offset: '*' index: '*' scale: '*' pre_indexed: false post_indexed: false throughput: 1.0 latency: 0 # 2*p45+1*p67 port_pressure: [[2, '45'], [1, '67']] - name: stp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: '*' index: '*' scale: '*' pre_indexed: false post_indexed: true throughput: 1.0 latency: 0 # 2*p45+2*p67+1*123 port_pressure: [[2, '45'], [2, '67'], [1, '123']] - name: stp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: '*' index: '*' scale: '*' pre_indexed: false post_indexed: false throughput: 1.0 latency: 0 # 2*p45+2*p67 port_pressure: [[2, '45'], [2, '67']] - name: stur # JL: assumed from n1 opt guide operands: - class: register prefix: d - class: memory base: x offset: '*' index: '*' scale: '*' pre_indexed: false post_indexed: false throughput: 0.5 latency: 0 # 1*p67+1*p23 port_pressure: [[1, '56'], [1, '23']] - name: stur # JL: assumed from n1 opt guide operands: - class: register prefix: q - class: memory base: x offset: '*' index: '*' scale: '*' pre_indexed: false post_indexed: false throughput: 1.0 latency: 0 # 2*p67+1*p45 port_pressure: [[2, '67'], [1, '45']] - name: str operands: - class: register prefix: x - class: memory base: x offset: '*' index: '*' scale: '*' pre_indexed: false post_indexed: false throughput: 0.5 latency: 0 # 1*p67+1*p23 port_pressure: [[1, '56'], [1, '23']] - name: str operands: - class: register prefix: d - class: memory base: x offset: '*' index: '*' scale: '*' pre_indexed: false post_indexed: false throughput: 0.5 latency: 0 # 1*p67+1*p45 port_pressure: [[1, '67'], [1, '45']] - name: str operands: - class: register prefix: d - class: memory base: x offset: '*' index: '*' scale: '*' pre_indexed: false post_indexed: true throughput: 0.5 latency: 0 # 1*p67+1*p45+1*p123 port_pressure: [[1, '67'], [1, '45'], [1, '123']] - name: str operands: - class: register prefix: q - class: memory base: x offset: '*' index: '*' scale: 1 pre_indexed: false post_indexed: false throughput: 1.0 latency: 0 # 2*p67+1*p45 port_pressure: [[1, '67'], [1, '45']] - name: str operands: - class: register prefix: q - class: memory base: x offset: '*' index: '*' scale: '*' pre_indexed: false post_indexed: true throughput: 1.0 latency: 0 # 1*p67+1*p45+1*123 port_pressure: [[1, '67'], [1, '45'], [1, '123']] - name: str operands: - class: register prefix: x - class: memory base: x offset: '*' index: '*' scale: '*' pre_indexed: false post_indexed: true throughput: 1.0 latency: 0 # 1*p67+1*p23+1*p123 port_pressure: [[1, '67'], [1, '23'], [1, '123']] - name: sub operands: - class: register prefix: w - class: register prefix: w - class: immediate imd: int throughput: 0.33333333 latency: 1.0 # 1*p123 port_pressure: [[1, '123']]