osaca_version: 0.5.2 micro_architecture: Apple M1 Firestorm arch_code: m1 isa: AArch64 ROB_size: 623 #https://dougallj.github.io/applecpu/firestorm.html retired_uOps_per_cycle: 8 scheduler_size: 326 #https://dougallj.github.io/applecpu/firestorm.html hidden_loads: false load_latency: {w: 3.0, x: 3.0, b: 3.0, h: 3.0, s: 3.0, d: 3.0, q: 3.0, v: 3.0} p_index_latency: 1 load_throughput: - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, '467']]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '467'], [1, ['8', '9', '10', '12', '13']]]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '467'], [1, ['8', '9', '10', '12', '13']]]} load_throughput_default: [[1, '467']] store_throughput: - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, '45']]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '45'], [1, ['8', '9', '10', '12', '13']]]} - {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '45'], [1, ['8', '9', '10', '12', '13']]]} store_throughput_default: [[1, '45']] ports: ['0', '1', '2', '3', '3DV', '4', '5', '6', '7', '8', '9', '10', '11', '12', '13'] port_model_scheme: | +------+ +------+ +------+ +-------------+ +-----------------------------+ +------+ +------+ +------+ +------+ +-------------+ +------+ | 36 | | 36 | | 36 | | 36 | | 48 | | 24 | | 26 | | 16 | | 12 | | 28 | | 28 | +------+ +------+ +------+ +-------------+ +-----------------------------+ +------+ +------+ +------+ +------+ +-------------+ +------+ 0 |FP0 1 |FP1 2 |FP2 3 |FP3 4 |D0 5 |D1 6 |D2 7 |D3 8 |INT0 9 |INT1 10 |INT2 11 |INT3 12 |INT4 13 |INT5 \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ +------+ +------+ +------+ +------+ +----+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ | ALU | | ALU | | ALU | | ALU | | DV | | LD | | ST | | LD | | LD | | ALU | | ALU | | ALU | | ALU | | ALU | | DV | | ALU | +------+ +------+ +------+ +------+ +----+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+ +------+ +------+ +------+ +------+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +------+ | MUL | | MUL | | MUL | | MUL | | ST | | AGU | | AGU | | AGU | | SHIFT| | SHIFT| | SHIFT| | SHIFT| | SHIFT| | SHIFT| +------+ +------+ +------+ +------+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +------+ +------+ +------+ +------+ +------+ +-----+ +------+ +------+ +------+ +------+ +------+ +------+ | FMA | | FMA | | FMA | | FMA | | AGU | | BR | | BR | | FLAGS| |MOV FP| | MUL | | MUL | +------+ +------+ +------+ +------+ +-----+ +------+ +------+ +------+ +------+ +------+ +------+ +------+ +------+ +------+ +------+ +------+ +------+ | FCSEL| | FCSEL| | FLAGS| | FLAGS| |MOV FP| silly | FMA | +------+ +------+ +------+ +------+ +------+ +------+ +------+ +------+ | 2INT | | 2INT | +------+ +------+ +------+ | RCP | +------+ +------+ | SHA | +------+ instruction_forms: - name: [adc, adcs] operands: - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' throughput: 0.33333333 latency: 1.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: add operands: - class: register prefix: x - class: register prefix: x - class: register prefix: x throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: add operands: - class: register prefix: x - class: register prefix: x - class: immediate imd: int throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: add operands: - class: register prefix: w - class: register prefix: w - class: register prefix: w throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: add operands: - class: register prefix: w - class: register prefix: w - class: immediate imd: int throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: adds operands: - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' throughput: 0.33333333 latency: 1.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: adds operands: - class: register prefix: '*' - class: register prefix: '*' - class: immediate imd: int throughput: 0.33333333 latency: 1.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: adr operands: - class: register prefix: '*' - class: identifier throughput: 0.5 latency: ~ # 1*p89 port_pressure: [[1, '89']] - name: and operands: - class: register prefix: x - class: register prefix: x - class: register prefix: x throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: and operands: - class: register prefix: x - class: register prefix: x - class: immediate imd: int throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: and operands: - class: register prefix: w - class: register prefix: w - class: register prefix: w throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: and operands: - class: register prefix: w - class: register prefix: w - class: immediate imd: int throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: ands operands: - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' throughput: 0.3333333 latency: 1.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: ands operands: - class: register prefix: '*' - class: register prefix: '*' - class: immediate imd: int throughput: 0.3333333 latency: 1.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: asr operands: - class: register prefix: x - class: register prefix: x - class: immediate imd: int throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: asr operands: - class: register prefix: w - class: register prefix: w - class: immediate imd: int throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: [asr, asrv] operands: - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: asr operands: - class: register prefix: '*' - class: register prefix: '*' - class: immediate imd: int throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: [b, bl, bcc, bcs, bgt, bhi, b.lo, b.ne, b.any, b.none, bal, b.al, b.lt, b.eq, b.hs, b.gt, b.hi, bne, beq] operands: - class: identifier throughput: 0.5 latency: 0.0 port_pressure: [[1, '89']] - name: bfc operands: - class: register prefix: '*' - class: immediate imd: int - class: immediate imd: int throughput: 1.0 latency: 1.0 # 1*p13 port_pressure: [[1, ['13']]] - name: [bfi, bfm] operands: - class: register prefix: '*' - class: register prefix: '*' - class: immediate imd: int - class: immediate imd: int throughput: 1.0 latency: 1.0 # 1*p13 port_pressure: [[1, ['13']]] - name: bic operands: - class: register prefix: x - class: register prefix: x - class: register prefix: x throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: bics operands: - class: register prefix: x - class: register prefix: x - class: register prefix: x throughput: 0.33333333 latency: 1.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: bic operands: - class: register prefix: w - class: register prefix: w - class: register prefix: w throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: bics operands: - class: register prefix: w - class: register prefix: w - class: register prefix: w throughput: 0.33333333 latency: 1.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: [cls, clz] operands: - class: register prefix: w - class: register prefix: w throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: [cls, clz] operands: - class: register prefix: x - class: register prefix: x throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: cmp operands: - class: register prefix: '*' - class: immediate imd: int throughput: 0.33333333 latency: 1.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: cmp operands: - class: register prefix: '*' - class: register prefix: '*' throughput: 0.3333333 latency: 1.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: [eon, eor] operands: - class: register prefix: x - class: register prefix: x - class: register prefix: x throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: eor operands: - class: register prefix: x - class: register prefix: x - class: immediate imd: int throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: [eon, eor] operands: - class: register prefix: w - class: register prefix: w - class: register prefix: w throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: eor operands: - class: register prefix: w - class: register prefix: w - class: immediate imd: int throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: [ldr, ldur] operands: - class: register prefix: "*" - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] - name: [ldr, ldur] operands: - class: register prefix: "*" - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] - name: [ldr, ldur] operands: - class: register prefix: "*" - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: [ldr, ldur] operands: - class: register prefix: "*" - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: [ldr, ldur] operands: - class: register prefix: "*" - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: [ldr, ldur] operands: - class: register prefix: "*" - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: x - class: register prefix: x - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] - name: ldp operands: - class: register prefix: x - class: register prefix: x - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] - name: ldp operands: - class: register prefix: x - class: register prefix: x - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: x - class: register prefix: x - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: x - class: register prefix: x - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: x - class: register prefix: x - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: w - class: register prefix: w - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] - name: ldp operands: - class: register prefix: w - class: register prefix: w - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] - name: ldp operands: - class: register prefix: w - class: register prefix: w - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: w - class: register prefix: w - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: w - class: register prefix: w - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: w - class: register prefix: w - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: d - class: register prefix: d - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] - name: ldp operands: - class: register prefix: d - class: register prefix: d - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] - name: ldp operands: - class: register prefix: d - class: register prefix: d - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: d - class: register prefix: d - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: d - class: register prefix: d - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: d - class: register prefix: d - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 3.0 # 2*p467 port_pressure: [[2, '467']] - name: ldp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 4.0 # 2*p467 port_pressure: [[2, '467']] - name: ldp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 3.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 4.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 3.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: q - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 4.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: s - class: register prefix: s - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] - name: ldp operands: - class: register prefix: s - class: register prefix: s - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] - name: ldp operands: - class: register prefix: s - class: register prefix: s - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: s - class: register prefix: s - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: s - class: register prefix: s - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: s - class: register prefix: s - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: [ldr, ldur] operands: - class: register prefix: "*" - class: identifier post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] - name: [ldr, ldur] operands: - class: register prefix: "*" - class: identifier post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] - name: [ldr, ldur] operands: - class: register prefix: "*" - class: identifier post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: [ldr, ldur] operands: - class: register prefix: "*" - class: identifier post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: [ldr, ldur] operands: - class: register prefix: "*" - class: identifier post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: [ldr, ldur] operands: - class: register prefix: "*" - class: identifier post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: x - class: register prefix: x - class: identifier post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] - name: ldp operands: - class: register prefix: x - class: register prefix: x - class: identifier post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] - name: ldp operands: - class: register prefix: x - class: register prefix: x - class: identifier post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: x - class: register prefix: x - class: identifier post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: x - class: register prefix: x - class: identifier post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: x - class: register prefix: x - class: identifier post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: w - class: register prefix: w - class: identifier post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] - name: ldp operands: - class: register prefix: w - class: register prefix: w - class: identifier post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] - name: ldp operands: - class: register prefix: w - class: register prefix: w - class: identifier post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: w - class: register prefix: w - class: identifier post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: w - class: register prefix: w - class: identifier post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: w - class: register prefix: w - class: identifier post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: d - class: register prefix: d - class: identifier post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] - name: ldp operands: - class: register prefix: d - class: register prefix: d - class: identifier post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] - name: ldp operands: - class: register prefix: d - class: register prefix: d - class: identifier post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: d - class: register prefix: d - class: identifier post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: d - class: register prefix: d - class: identifier post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: d - class: register prefix: d - class: identifier post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: q - class: register prefix: q - class: identifier post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 3.0 # 2*p467 port_pressure: [[2, '467']] - name: ldp operands: - class: register prefix: q - class: register prefix: q - class: identifier post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 4.0 # 2*p467 port_pressure: [[2, '467']] - name: ldp operands: - class: register prefix: q - class: register prefix: q - class: identifier post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 3.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: q - class: register prefix: q - class: identifier post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 4.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: q - class: register prefix: q - class: identifier post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 3.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: q - class: identifier post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 4.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: s - class: register prefix: s - class: identifier post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467']] - name: ldp operands: - class: register prefix: s - class: register prefix: s - class: identifier post-indexed: false pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467']] - name: ldp operands: - class: register prefix: s - class: register prefix: s - class: identifier post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: s - class: register prefix: s - class: identifier post-indexed: true pre-indexed: false throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: s - class: register prefix: s - class: identifier post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 3.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: ldp operands: - class: register prefix: s - class: register prefix: s - class: identifier post-indexed: false pre-indexed: true throughput: 0.3333333 latency: 4.0 # 1*p467 port_pressure: [[1, '467'], [1, ['8', '9', '10']]] - name: [lsl, lslv, lsr, lsrv] operands: - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: [lsl, lslv, lsr, lsrv] operands: - class: register prefix: '*' - class: register prefix: '*' - class: immediate imd: int throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: [madd, msub] # NOTE: if the dependency is via the addend (fourth operand), the latency is only 1cy !!! operands: - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' throughput: 1.0 latency: 3.0 # 1*,13 NOTE: if the dependency is via the addend (fourth operand), the latency is only 1cy !!! port_pressure: [[1, ['13']]] - name: mneg operands: - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' throughput: 0.5 latency: 3.0 # 1*p12,13 port_pressure: [[1, ['12', '13']]] - name: [mov, movk, movn, movz] operands: - class: register prefix: x - class: immediate imd: int throughput: 0.16666666 latency: 0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: [mov, movk, movn, movz] operands: - class: register prefix: w - class: immediate imd: int throughput: 0.16666666 latency: 0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: [mov, movk, movn, movz] operands: - class: register prefix: x - class: register prefix: x throughput: 0.16666666 latency: 0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: [mov, movk, movn, movz] operands: - class: register prefix: w - class: register prefix: w throughput: 0.16666666 latency: 0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: mul operands: - class: register prefix: w - class: register prefix: w - class: register prefix: w throughput: 0.5 latency: 3.0 # 1*p12,13 port_pressure: [[1, ['12', '13']]] - name: mul operands: - class: register prefix: x - class: register prefix: x - class: register prefix: x throughput: 0.5 latency: 3.0 # 1*p12,13 port_pressure: [[1, ['12', '13']]] - name: mvn operands: - class: register prefix: x - class: register prefix: x throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: neg operands: - class: register prefix: x - class: register prefix: x throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: neg operands: - class: register prefix: w - class: register prefix: w throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: [negs, ngc, ngcs] operands: - class: register prefix: '*' - class: register prefix: '*' throughput: 0.33333333 latency: 1.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: nop operands: [] throughput: 0.16666666 latency: ~ # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: [orn, orr] operands: - class: register prefix: x - class: register prefix: x - class: register prefix: x throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: [orn, orr] operands: - class: register prefix: x - class: register prefix: x - class: immediate imd: int throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: [orn, orr] operands: - class: register prefix: w - class: register prefix: w - class: register prefix: w throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: [orn, orr] operands: - class: register prefix: w - class: register prefix: w - class: immediate imd: int throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: [rbit, rev, rev16, rev32] operands: - class: register prefix: x - class: register prefix: x throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: [rbit, rev, rev16, rev32] operands: - class: register prefix: w - class: register prefix: w throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: ret operands: [] throughput: 0.0 latency: ~ port_pressure: [] - name: ret operands: - class: immediate imd: int throughput: 0.0 latency: ~ port_pressure: [] - name: ret operands: - class: identifier throughput: 0.0 latency: ~ port_pressure: [] - name: ror operands: - class: register prefix: '*' - class: register prefix: '*' - class: immediate imd: int throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: [ror, rorv] operands: - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: [sbc, sbcs] operands: - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' throughput: 0.33333333 latency: 1.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: [sbfiz, sbfm, sbfx] operands: - class: register prefix: '*' - class: register prefix: '*' - class: immediate imd: int - class: immediate imd: int throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: [scvtf, ucvtf] operands: - class: register prefix: s - class: register prefix: w throughput: 0.33333333 latency: 4.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: [scvtf, ucvtf] operands: - class: register prefix: d - class: register prefix: x throughput: 0.33333333 latency: 4.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: [scvtf, ucvtf] operands: - class: register prefix: d - class: register prefix: x - class: immediate imd: int throughput: 0.33333333 latency: 4.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: [scvtf, ucvtf] operands: - class: register prefix: s - class: register prefix: w - class: immediate imd: int throughput: 0.33333333 latency: 4.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: sdiv operands: - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' throughput: 7.0 latency: 2.0 # 2*p12DV port_pressure: [[2, ['12']]] - name: [smaddl, smsubl, umaddl, umsubl] operands: - class: register prefix: x - class: register prefix: w - class: register prefix: w - class: register prefix: x throughput: 1.0 latency: 3.0 # 1*p13 port_pressure: [[1, ['13']]] - name: [smnegl, umnegl] operands: - class: register prefix: x - class: register prefix: w - class: register prefix: w throughput: 0.5 latency: 3.0 # 1*p12,13 port_pressure: [[1, ['12', '13']]] - name: [smulh, umulh] operands: - class: register prefix: x - class: register prefix: x - class: register prefix: x throughput: 0.5 latency: 3.0 # 1*p12,13 port_pressure: [[1, ['12', '13']]] - name: [smull, umull] operands: - class: register prefix: x - class: register prefix: w - class: register prefix: w throughput: 0.5 latency: 3.0 # 1*p12,13 port_pressure: [[1, ['12', '13']]] - name: [str, stur] operands: - class: register prefix: "*" - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: [str, stur] operands: - class: register prefix: "*" - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: [str, stur] operands: - class: register prefix: "*" - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: [str, stur] operands: - class: register prefix: "*" - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: [str, stur] operands: - class: register prefix: "*" - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: [str, stur] operands: - class: register prefix: "*" - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: x - class: register prefix: x - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: x - class: register prefix: x - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: x - class: register prefix: x - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: x - class: register prefix: x - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: x - class: register prefix: x - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: x - class: register prefix: x - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: w - class: register prefix: w - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: w - class: register prefix: w - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: w - class: register prefix: w - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: w - class: register prefix: w - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: w - class: register prefix: w - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: w - class: register prefix: w - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: d - class: register prefix: d - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: d - class: register prefix: d - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: d - class: register prefix: d - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: d - class: register prefix: d - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: d - class: register prefix: d - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: d - class: register prefix: d - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45']] - name: stp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45']] - name: stp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: q - class: register prefix: q - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: true throughput: 0.5 latency: 4.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: s - class: register prefix: s - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: s - class: register prefix: s - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: s - class: register prefix: s - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: s - class: register prefix: s - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: s - class: register prefix: s - class: memory base: x offset: '*' index: ~ scale: ~ post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: [str, stur] operands: - class: register prefix: "*" - class: identifier post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: [str, stur] operands: - class: register prefix: "*" - class: identifier post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: [str, stur] operands: - class: register prefix: "*" - class: identifier post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: [str, stur] operands: - class: register prefix: "*" - class: identifier post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: [str, stur] operands: - class: register prefix: "*" - class: identifier post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: [str, stur] operands: - class: register prefix: "*" - class: identifier post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: x - class: register prefix: x - class: identifier post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: x - class: register prefix: x - class: identifier post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: x - class: register prefix: x - class: identifier post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: x - class: register prefix: x - class: identifier post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: x - class: register prefix: x - class: identifier post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: x - class: register prefix: x - class: identifier post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: w - class: register prefix: w - class: identifier post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: w - class: register prefix: w - class: identifier post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: w - class: register prefix: w - class: identifier post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: w - class: register prefix: w - class: identifier post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: w - class: register prefix: w - class: identifier post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: w - class: register prefix: w - class: identifier post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: d - class: register prefix: d - class: identifier post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: d - class: register prefix: d - class: identifier post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: d - class: register prefix: d - class: identifier post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: d - class: register prefix: d - class: identifier post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: d - class: register prefix: d - class: identifier post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: d - class: register prefix: d - class: identifier post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: q - class: register prefix: q - class: identifier post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45']] - name: stp operands: - class: register prefix: q - class: register prefix: q - class: identifier post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45']] - name: stp operands: - class: register prefix: q - class: register prefix: q - class: identifier post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: q - class: register prefix: q - class: identifier post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: q - class: register prefix: q - class: identifier post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 2*p45 port_pressure: [[2, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: q - class: register prefix: q - class: identifier post-indexed: false pre-indexed: true throughput: 0.5 latency: 4.0 # 2*p467 port_pressure: [[2, '467'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: s - class: register prefix: s - class: identifier post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: s - class: register prefix: s - class: identifier post-indexed: false pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45']] - name: stp operands: - class: register prefix: s - class: register prefix: s - class: identifier post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: s - class: register prefix: s - class: identifier post-indexed: true pre-indexed: false throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: s - class: register prefix: s - class: identifier post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: s - class: register prefix: s - class: identifier post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: stp operands: - class: register prefix: s - class: register prefix: s - class: memory base: x offset: '*' index: '*' scale: '*' post-indexed: false pre-indexed: true throughput: 0.5 latency: 0.0 # 1*p45 port_pressure: [[1, '45'], [1, ['8', '9', '10']]] - name: sub operands: - class: register prefix: w - class: register prefix: w - class: immediate imd: int throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: sub operands: - class: register prefix: x - class: register prefix: x - class: immediate imd: int throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: sub operands: - class: register prefix: w - class: register prefix: w - class: register prefix: w throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: sub operands: - class: register prefix: x - class: register prefix: x - class: register prefix: x throughput: 0.2 latency: 1.0 # 1*p89,10,12,13 port_pressure: [[1, ['8', '9', '10', '12', '13']]] - name: subs operands: - class: register prefix: w - class: register prefix: w - class: immediate imd: int throughput: 0.33333333 latency: 1.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: subs operands: - class: register prefix: x - class: register prefix: x - class: immediate imd: int throughput: 0.33333333 latency: 1.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: subs operands: - class: register prefix: w - class: register prefix: w - class: register prefix: w throughput: 0.33333333 latency: 1.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: subs operands: - class: register prefix: x - class: register prefix: x - class: register prefix: x throughput: 0.33333333 latency: 1.0 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] - name: sxtb operands: - class: register prefix: x - class: register prefix: w throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: [ubfiz, ubfm, ubfx] operands: - class: register prefix: "*" - class: register prefix: "*" - class: immediate imd: int - class: immediate imd: int throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: udiv operands: - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' throughput: 7.0 latency: 2.0 # 2*p12DV port_pressure: [[2, ['12']]] - name: [uxtb, uxth] operands: - class: register prefix: w - class: register prefix: w throughput: 0.16666666 latency: 1.0 # 1*p89,10,11,12,13 port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]] - name: fabs operands: - class: register prefix: '*' - class: register prefix: '*' throughput: 0.25 latency: 1.0 # 1*p0123 port_pressure: [[1, '0123']] - name: fabs operands: - class: register prefix: '*' shape: '*' width: '*' - class: immediate imd: int throughput: 0.25 latency: 1.0 # 1*p0123 port_pressure: [[1, '0123']] - name: fadd operands: - class: register prefix: '*' shape: '*' width: '*' - class: register prefix: '*' shape: '*' width: '*' - class: register prefix: '*' shape: '*' width: '*' throughput: 0.25 latency: 3.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [fcmp, fcmpe] operands: - class: register prefix: '*' - class: register prefix: '*' throughput: 1.0 latency: 1.0 # 1*p3 port_pressure: [[1, '3']] - name: [fccmp, fccmpe] # LT assumed from fcmp operands: - class: register prefix: s - class: register prefix: s - class: immediate imd: int - class: condition ccode: "*" throughput: 1.0 latency: 1.0 # 1*p3 port_pressure: [[1, '3']] - name: fcvt operands: - class: register prefix: '*' - class: register prefix: '*' throughput: 0.25 latency: 4.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] operands: - class: register prefix: h - class: register prefix: h throughput: 0.25 latency: 4.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] operands: - class: register prefix: s - class: register prefix: s throughput: 0.25 latency: 4.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] operands: - class: register prefix: d - class: register prefix: d throughput: 0.25 latency: 4.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] operands: - class: register prefix: '*' - class: register prefix: '*' throughput: 0.5 latency: 4.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [fcvtzs, fcvtzu] operands: - class: register prefix: '*' - class: register prefix: '*' - class: immediate imd: int throughput: 0.5 latency: 4.0 # 1*p0123 port_pressure: [[1, '0123']] - name: fdiv operands: - class: register prefix: v shape: d width: '*' - class: register prefix: v shape: d width: '*' - class: register prefix: v shape: d width: '*' throughput: 1.0 latency: 10.0 # 1*p3 port_pressure: [[1, '3'], [1, ['3DV']]] - name: fdiv operands: - class: register prefix: d - class: register prefix: d - class: register prefix: d throughput: 1.0 latency: 10.0 # 1*p3 port_pressure: [[1, '3'], [1, ['3DV']]] - name: fdiv operands: - class: register prefix: v shape: s width: '*' - class: register prefix: v shape: s width: '*' - class: register prefix: v shape: s width: '*' throughput: 1.0 latency: 8.0 # 1*p3 port_pressure: [[1, '3'], [1, ['3DV']]] - name: fdiv operands: - class: register prefix: s - class: register prefix: s - class: register prefix: s throughput: 1.0 latency: 8.0 # 1*p3 port_pressure: [[1, '3'], [1, ['3DV']]] - name: [fmadd, fnmadd] operands: - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' throughput: 0.25 latency: 4.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [fmax, fmaxnm, fmin, fminnm] operands: - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: fmov operands: - class: register prefix: '*' - class: immediate imd: '*' latency: ~ # 1*p0123 port_pressure: [[1, '0123']] throughput: 0.25 - name: fmov operands: - class: register prefix: x - class: register prefix: d latency: 2.5 # 1*p23 port_pressure: [[1, '23']] throughput: 0.5 - name: fmov operands: - class: register prefix: w - class: register prefix: s latency: 2.5 # 1*p23 port_pressure: [[1, '23']] throughput: 0.5 - name: fmov operands: - class: register prefix: d - class: register prefix: x latency: 2.5 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] throughput: 0.33333333 - name: fmov operands: - class: register prefix: s - class: register prefix: w latency: 2.5 # 1*p89,10 port_pressure: [[1, ['8', '9', '10']]] throughput: 0.33333333 - name: fmov operands: - class: register prefix: '*' - class: register prefix: '*' latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] throughput: 0.25 - name: [fmsub, fnmsub] operands: - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' latency: 4.0 # 1*p0123 port_pressure: [[1, '0123']] throughput: 0.25 - name: [fmul, fnmul] operands: - class: register prefix: '*' - class: register prefix: '*' - class: register prefix: '*' throughput: 0.25 latency: 4.0 # 1*p0123 port_pressure: [[1, '0123']] - name: fneg operands: - class: register prefix: '*' - class: register prefix: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [frinta, frinti, frintm, frintn, frintp, frintx, frintz] operands: - class: register prefix: '*' - class: register prefix: '*' throughput: 0.25 latency: 3.0 # 1*p0123 port_pressure: [[1, '0123']] - name: fsqrt operands: - class: register prefix: s - class: register prefix: s throughput: 2 latency: 10.0 # 1*p3+2*p3DV port_pressure: [[1, '3'], [2, ['3DV']]] - name: fsqrt operands: - class: register prefix: d - class: register prefix: d throughput: 2 latency: 13.0 # 1*p3+2*p3DV port_pressure: [[1, '3'], [2, ['3DV']]] - name: fsub operands: - class: register prefix: '*' shape: '*' width: '*' - class: register prefix: '*' shape: '*' width: '*' - class: register prefix: '*' shape: '*' width: '*' throughput: 0.25 latency: 3.0 # 1*p0123 port_pressure: [[1, '0123']] - name: abs operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 3.0 # 1*p0123 port_pressure: [[1, '0123']] - name: add operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: addp operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: and operands: - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: bic operands: - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: bic operands: - class: register prefix: v shape: s width: '*' - class: immediate imd: int throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [bif, bit, bsl] operands: - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' throughput: 0.5 latency: 2.0 # 1*p23 port_pressure: [[1, '23']] - name: [cls, clz] operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [cmeq, cmge, cmgt, cmhi, cmhs, cmle, cmlt, cmtst] operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [cmeq, cmge, cmgt, cmhi, cmhs, cmle, cmlt, cmtst] operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: immediate imd: int throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: cnt operands: - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: eor operands: - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: dup operands: - class: register prefix: d - class: register prefix: v shape: d width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: dup operands: - class: register prefix: v shape: d width: '*' - class: register prefix: v shape: d width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: dup # LT from scvt operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: x throughput: 0.33333333 latency: 4.0 # 1*p0123+1*p89,10 port_pressure: [[1, '0123'], [1, ['8', '9', '10']]] - name: ext operands: - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' - class: immediate imd: int throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: fabd operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 3.0 # 1*p0123 port_pressure: [[1, '0123']] - name: fabs operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [facge, facgt] operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: faddp operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 3.0 # 1*p0123 port_pressure: [[1, '0123']] - name: fcadd operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: immediate imd: int throughput: 0.25 latency: 3.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [fcmeq, fcmge, fcmgt, fcmle, fcmlt] operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: immediate imd: int throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [fcmeq, fcmge, fcmgt, fcmle, fcmlt] operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: fcmla operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: immediate imd: int throughput: 0.5 latency: 4.0 # 1*p0123 port_pressure: [[1, '23']] - name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 3.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [fcvtas, fcvtau, fcvtms, fcvtmu, fcvtns, fcvtnu, fcvtps, fcvtpu, fcvtzs, fcvtzu] operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: immediate imd: int throughput: 0.25 latency: 3.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [fmax, fmaxnm, fmaxnmp, fmaxp] operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [fmin, fminnm, fminnmp, fminp] operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [fmla, fmls] operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 4.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [fmul, fmulx] operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 4.0 # 1*p0123 port_pressure: [[1, '0123']] - name: fneg operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: frecpe operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 1.0 latency: 3.0 # 1*p3 port_pressure: [[1, '3']] - name: frecps operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 4.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [frinta, frinti, frintm, frintn, frintp, frintx, frintz] operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 3.0 # 1*p0123 port_pressure: [[1, '0123']] - name: fsqrt operands: - class: register prefix: v shape: d width: '*' - class: register prefix: v shape: d width: '*' throughput: 2.0 latency: 13.0 # 1*p3+2*p3DV port_pressure: [[1, '3'], [2, ['3DV']]] - name: fsqrt operands: - class: register prefix: v shape: s width: '*' - class: register prefix: v shape: s width: '*' throughput: 2.0 latency: 10.0 # 1*p3+2*p3DV port_pressure: [[1, '3'], [2, ['3DV']]] - name: frsqrte operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 1.0 latency: 3.0 # 1*p3 port_pressure: [[1, '3']] - name: frsqrts operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 4.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [mla, mls] operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 3.0 # 1*p0123 port_pressure: [[1, '0123']] - name: mov operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.0 latency: 0.0 port_pressure: [] - name: mul operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 3.0 # 1*p0123 port_pressure: [[1, '0123']] - name: mvn operands: - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: neg operands: - class: register prefix: v shape: '*' width: '*' - class: register prefix: v shape: '*' width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: not operands: - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [orn, orr] operands: - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: pmul operands: - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' throughput: 0.25 latency: 3.0 # 1*p0123 port_pressure: [[1, '0123']] - name: rbit operands: - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: [rev16, rev32, rev64] operands: - class: register prefix: v shape: b width: '*' - class: register prefix: v shape: b width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: rev64 operands: - class: register prefix: v shape: s width: '*' - class: register prefix: v shape: s width: '*' throughput: 0.25 latency: 2.0 # 1*p0123 port_pressure: [[1, '0123']] - name: saba operands: - class: register prefix: v shape: s width: '*' - class: register prefix: v shape: s width: '*' - class: register prefix: v shape: s width: '*' throughput: 0.25 latency: 3.0 # 1*p0123 port_pressure: [[1, '0123']]