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OSACA/osaca/data/spr.yml
2024-12-31 13:46:44 +01:00

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osaca_version: 0.5.3
micro_architecture: Sapphire Rapids
arch_code: SPR
isa: x86
ROB_size: ~
retired_uOps_per_cycle: ~
scheduler_size: ~
hidden_loads: false
load_latency: {gpr: 5.0, mm: 5.0, xmm: 5.0, ymm: 5.0, zmm: 5.0}
load_throughput:
- {dst: zmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '23'], [0.5, ['11']]]}
- {dst: ymm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['2', '3', '11']]]}
- {dst: xmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['2', '3', '11']]]}
- {dst: gpr, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['2', '3', '11']]]}
load_throughput_default: [[1, ['2', '3', '11']]]
store_throughput:
- {src: zmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '78'], [1, '4'], [1, '9']]}
- {src: ymm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '78'], [1, '49']]}
- {src: xmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '78'], [1, '49']]}
- {src: gpr, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '78'], [1, '49']]}
store_throughput_default: [[1, '78'], [1, '49']]
ports: ['0', 0DV, '1', 1DV, '2', '3', '4', '5', '6', '7', '8', '9', '10', '11']
port_model_scheme: |
+--------------------------------------------------------------------------------------------------------+
| scheduler |
+--------------------------------------------------------------------------------------------------------+
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
\/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/
+-------+ +-------+ +-----+ +-----+ +-----+ +-------+ +-------+ +------+ +------+ +-----+ +-----+ +-----+
| ALU | | ALU | | LD | | LD | | ST | | ALU | | ALU | |ST AGU| |ST AGU| | ST | | ALU | | LD |
+-------+ +-------+ +-----+ +-----+ +-----+ +-------+ +-------+ +------+ +------+ +-----+ +-----+ +-----+
+-------+ +-------+ +-----+ +-----+ +-------+ +-------+ +-----+ +-----+
| BRANCH| | LEA | | AGU | | AGU | | LEA | | SHIFT | | LEA | | AGU |
+-------+ +-------+ +-----+ +-----+ +-------+ +-------+ +-----+ +-----+
+-------+ +-------+ +-------+ +-------+
| LEA | |INT MUL| | MUL Hi| | BRANCH|
+-------+ +-------+ +-------+ +-------+
+-------+ +-------+ +-------+ +-------+
| SHIFT | |INT DIV| |AVX ALU| | LEA |
+-------+ +-------+ +-------+ +-------+
+-------+ +-------+ +-------+
|AVX ALU| |AVX*ALU| | AVX |
+-------+ +-------+ | SHUF |
+-------+ +-------+ +-------+
|AVX DIV| |AVX*FMA| +-------+
+-------+ +-------+ |AVX FMA|
+-------+ +-------+ +-------+
|AVX FMA| | AVX* |
+-------+ | SHUF |
+--------+ +-------+
|AVX SHFT| +-------+
+--------+ | AVX* |
| SHFT |
+-------+ * = no AVX-512
instruction_forms:
##########################################
# assume all jmp instruction 0
- name: [jo, jno, js, jns, jp, jpe, jnp, jpo]
operands:
- class: identifier
throughput: 0.0
latency: 0.0
port_pressure: []
- name: [jc, jb, jae, jnb, jna, jbe, ja, jnbe]
operands:
- class: identifier
throughput: 0.0
latency: 0.0
port_pressure: []
- name: [je, jz, jne, jnz, jl, jnge]
operands:
- class: identifier
throughput: 0.0
latency: 0.0
port_pressure: []
- name: [jge, jnl, jle, jng, jg, jnle]
operands:
- class: identifier
throughput: 0.0
latency: 0.0
port_pressure: []
- name: jmp
operands:
- class: identifier
throughput: 0.0
latency: 0.0
port_pressure: []
##########################################
# assume all cmp's equal for now
# TODO add cmp instructions
- name: [cmp, cmpeqpd, cmpltpd, cmplepd, cmpunordpd, cmpneqpd, cmpnltpd, cmpnlepd, cmpordpd, cmpltps, cmpleps, cmpunordps, cmpneqps, cmpnltps, cmpnleps, cmpordps]
operands:
- class: register
name: '*'
- class: register
name: '*'
latency: 1.0
port_pressure: [[1, ['0','1','5','6','10']]]
throughput: 0.20
uops: 1
- name: [cmp, cmpeqpd, cmpltpd, cmplepd, cmpunordpd, cmpneqpd, cmpnltpd, cmpnlepd, cmpordpd, cmpltps, cmpleps, cmpunordps, cmpneqps, cmpnltps, cmpnleps, cmpordps]
operands:
- class: immediate
imd: int
- class: register
name: '*'
latency: 1.0
port_pressure: [[1, ['0','1','5','6','10']]]
throughput: 0.20
uops: 1
##########################################
- name: push
operands:
- class: immediate
imd: int
latency: 0
port_pressure: [[1, '78'], [1, '49']]
throughput: 0.5
uops: 2
- name: push
operands:
- class: register
name: gpr
latency: 12
port_pressure: [[1, '78'], [1, '49']]
throughput: 0.5
uops: 2
- name: push
operands:
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
latency: 0
port_pressure: [[1, '78'], [1, '49']]
throughput: 0.5
uops: 2
- name: pop
operands:
- class: immediate
imd: int
latency: 5
port_pressure: [[1, ['2', '3', '11']]]
throughput: 0.3333333333333333
uops: 2
- name: pop
operands:
- class: register
name: gpr
latency: 5
port_pressure: [[1, ['2', '3', '11']]]
throughput: 0.3333333333333333
uops: 2
- name: pop
operands:
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
latency: 5
port_pressure: [[1, ['2', '3', '11']]]
throughput: 0.3333333333333333
uops: 2
##########################################
- name: mov # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: mov # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: mov # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: mov # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: immediate # ./generate_mov_entries.py spr
imd: int # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: mov # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: immediate # ./generate_mov_entries.py spr
imd: int # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: movabs # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: immediate # ./generate_mov_entries.py spr
imd: int # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: movapd # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: movapd # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: movapd # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovapd # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovapd # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovapd # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovapd # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovapd # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovapd # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovapd # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovapd # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr
throughput: 1.0 # ./generate_mov_entries.py spr
uops: 4 # ./generate_mov_entries.py spr
- name: vmovapd # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3']], [0.5, ['11']]] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 1.5 # ./generate_mov_entries.py spr
- name: movaps # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: movaps # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: movaps # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovaps # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovaps # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovaps # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovaps # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovaps # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovaps # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovaps # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovaps # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr
throughput: 1.0 # ./generate_mov_entries.py spr
uops: 4 # ./generate_mov_entries.py spr
- name: vmovaps # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3']], [0.5, ['11']]] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 1.5 # ./generate_mov_entries.py spr
- name: movdqa # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: movdqa # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: movdqa # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqa # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqa # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovdqa # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqa # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqa # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovdqa # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqa32 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqa32 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovdqa32 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqa32 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqa32 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovdqa32 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqa32 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqa32 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3']], [0.5, ['11']]] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 1.5 # ./generate_mov_entries.py spr
- name: vmovdqa32 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr
throughput: 1.0 # ./generate_mov_entries.py spr
uops: 4 # ./generate_mov_entries.py spr
- name: vmovdqa64 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqa64 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovdqa64 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqa64 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqa64 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovdqa64 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqa64 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqa64 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3']], [0.5, ['11']]] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 1.5 # ./generate_mov_entries.py spr
- name: vmovdqa64 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr
throughput: 1.0 # ./generate_mov_entries.py spr
uops: 4 # ./generate_mov_entries.py spr
- name: movdqu # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: movdqu # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: movdqu # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqu # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqu # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovdqu # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqu # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqu # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovdqu # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqu8 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqu8 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovdqu8 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqu8 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqu8 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovdqu8 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqu8 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqu8 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3']], [0.5, ['11']]] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 1.5 # ./generate_mov_entries.py spr
- name: vmovdqu8 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr
throughput: 1.0 # ./generate_mov_entries.py spr
uops: 4 # ./generate_mov_entries.py spr
- name: vmovdqu16 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqu16 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovdqu16 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqu16 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqu16 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovdqu16 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqu16 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqu16 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3']], [0.5, ['11']]] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 1.5 # ./generate_mov_entries.py spr
- name: vmovdqu16 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr
throughput: 1.0 # ./generate_mov_entries.py spr
uops: 4 # ./generate_mov_entries.py spr
- name: vmovdqu32 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqu32 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovdqu32 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqu32 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqu32 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovdqu32 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqu32 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqu32 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3']], [0.5, ['11']]] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 1.5 # ./generate_mov_entries.py spr
- name: vmovdqu32 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr
throughput: 1.0 # ./generate_mov_entries.py spr
uops: 4 # ./generate_mov_entries.py spr
- name: vmovdqu64 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqu64 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovdqu64 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqu64 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqu64 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovdqu64 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovdqu64 # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovdqu64 # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3']], [0.5, ['11']]] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 1.5 # ./generate_mov_entries.py spr
- name: vmovdqu64 # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr
throughput: 1.0 # ./generate_mov_entries.py spr
uops: 4 # ./generate_mov_entries.py spr
- name: movntdq # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovntdq # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovntdq # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovntdq # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr
throughput: 1.0 # ./generate_mov_entries.py spr
uops: 4 # ./generate_mov_entries.py spr
- name: movntdqa # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovntdqa # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovntdqa # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovntdqa # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3']], [0.5, ['11']]] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 1.5 # ./generate_mov_entries.py spr
- name: movnti # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: movntpd # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovntpd # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovntpd # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovntpd # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr
throughput: 1.0 # ./generate_mov_entries.py spr
uops: 4 # ./generate_mov_entries.py spr
- name: movntps # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovntps # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovntps # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovntps # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr
throughput: 1.0 # ./generate_mov_entries.py spr
uops: 4 # ./generate_mov_entries.py spr
- name: movntq # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: mm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: movq # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: mm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: mm # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [] # ./generate_mov_entries.py spr
throughput: 0.0 # ./generate_mov_entries.py spr
uops: 0 # ./generate_mov_entries.py spr
- name: movq # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: mm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: movq # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: mm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: movq # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: movq # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: movq # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovq # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 3 # ./generate_mov_entries.py spr
port_pressure: [[1, '0']] # ./generate_mov_entries.py spr
throughput: 1.0 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovq # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 3 # ./generate_mov_entries.py spr
port_pressure: [[1, '5']] # ./generate_mov_entries.py spr
throughput: 1.0 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovq # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovq # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovq # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: movsd # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: movsd # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: movsd # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovsd # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovsd # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovsd # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: movss # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: movss # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovss # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovss # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovss # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovss # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: movss # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: movsx # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: movsx # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: movsxd # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [] # ./generate_mov_entries.py spr
throughput: 0.0 # ./generate_mov_entries.py spr
uops: 0 # ./generate_mov_entries.py spr
- name: movsxd # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: movsb # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: movsb # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: movsw # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: movsw # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: movsl # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: movsl # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: movsq # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: movsq # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: gpr # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: movupd # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: movupd # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: movupd # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovupd # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovupd # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovupd # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovupd # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovupd # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovupd # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovupd # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovupd # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3']], [0.5, ['11']]] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 1.5 # ./generate_mov_entries.py spr
- name: vmovupd # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr
throughput: 1.0 # ./generate_mov_entries.py spr
uops: 4 # ./generate_mov_entries.py spr
- name: movups # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: movups # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: movups # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovups # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovups # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovups # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: xmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovups # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovups # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3', '11']]] # ./generate_mov_entries.py spr
throughput: 0.3333333333333333 # ./generate_mov_entries.py spr
uops: 1 # ./generate_mov_entries.py spr
- name: vmovups # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: ymm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[1, '78'], [1, '49']] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 2 # ./generate_mov_entries.py spr
- name: vmovups # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 1 # ./generate_mov_entries.py spr
port_pressure: [[1.0, ['0', '1', '5', '6', '10']]] # ./generate_mov_entries.py spr
throughput: 0.2 # ./generate_mov_entries.py spr
uops: 1.0 # ./generate_mov_entries.py spr
- name: vmovups # with load # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
latency: 5 # ./generate_mov_entries.py spr
port_pressure: [[1, ['2', '3']], [0.5, ['11']]] # ./generate_mov_entries.py spr
throughput: 0.5 # ./generate_mov_entries.py spr
uops: 1.5 # ./generate_mov_entries.py spr
- name: vmovups # with store # ./generate_mov_entries.py spr
operands: # ./generate_mov_entries.py spr
- class: register # ./generate_mov_entries.py spr
name: zmm # ./generate_mov_entries.py spr
- class: memory # ./generate_mov_entries.py spr
base: "*" # ./generate_mov_entries.py spr
offset: "*" # ./generate_mov_entries.py spr
index: "*" # ./generate_mov_entries.py spr
scale: "*" # ./generate_mov_entries.py spr
latency: 0 # ./generate_mov_entries.py spr
port_pressure: [[2, '78'], [2, '49']] # ./generate_mov_entries.py spr
throughput: 1.0 # ./generate_mov_entries.py spr
uops: 4 # ./generate_mov_entries.py spr
##########################################
- name: adc # ibench
operands: # ibench
- class: register # ibench
name: gpr # ibench
- class: register # ibench
name: gpr # ibench
latency: 1 # ibench
port_pressure: [[1, '06']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: add # ibench
operands: # ibench
- class: register # ibench
name: gpr # ibench
- class: register # ibench
name: gpr # ibench
latency: 1 # ibench
port_pressure: [[1, ['0','1','5','6','10']]] # ibench
throughput: 0.20 # ibench
uops: 1 # ibench
- name: add # ibench
operands: # ibench
- class: immediate # ibench
imd: int # ibench
- class: register # ibench
name: gpr # ibench
latency: 1 # ibench
port_pressure: [[1, ['0','1','5','6','10']]] # ibench
throughput: 0.20 # ibench
uops: 1 # ibench
- name: neg # ibench
operands: # ibench
- class: register # ibench
name: gpr # ibench
latency: 1 # ibench
port_pressure: [[1, ['0','1','5','6','10']]] # ibench
throughput: 0.2 # ibench
uops: 1 # ibench
- name: pdep
operands:
- class: register
name: gpr
- class: register
name: gpr
- class: register
name: gpr
latency: 3
port_pressure: [[1, '1']]
throughput: 1.0
uops: 1
- name: addpd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 2 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: addsd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 2 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: mulsd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: mulpd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: mulss # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: mulps # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: addps # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 2 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: addss # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 2 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: rcpss # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '0']] # ibench
throughput: 1.0 # ibench
uops: 1 # ibench
- name: rcpps # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '0']] # ibench
throughput: 1.0 # ibench
uops: 1 # ibench
- name: vrcpps # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '0']] # ibench
throughput: 1.0 # ibench
uops: 1 # ibench
- name: vrcpps # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
latency: 4 # ibench
port_pressure: [[1, '0']] # ibench
throughput: 1.0 # ibench
uops: 1 # ibench
- name: vrcpss # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '0']] # ibench
throughput: 1.0 # ibench
uops: 1 # ibench
- name: sqrtsd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 13 # ibench
port_pressure: [[6, ['0DV']], [1, '0']] # ibench
throughput: 6.0 # ibench
uops: 7 # ibench
- name: sqrtss # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 12 # ibench
port_pressure: [[3, ['0DV']], [1, '0']] # ibench
throughput: 3.0 # ibench
uops: 4 # ibench
- name: vsqrtsd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 13 # ibench
port_pressure: [[6, ['0DV']], [1, '0']] # ibench
throughput: 6.0 # ibench
uops: 7 # ibench
- name: vsqrtss # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 12 # ibench
port_pressure: [[3, ['0DV']], [1, '0']] # ibench
throughput: 3.0 # ibench
uops: 4 # ibench
- name: sub # ibench
operands: # ibench
- class: immediate # ibench
imd: int # ibench
- class: register # ibench
name: gpr # ibench
latency: 1 # ibench
port_pressure: [[1, ['0','1','5','6','10']]] # ibench
throughput: 0.20 # ibench
uops: 1 # ibench
- name: sub # ibench
operands: # ibench
- class: register # ibench
name: gpr # ibench
- class: register # ibench
name: gpr # ibench
latency: 1 # ibench
port_pressure: [[1, ['0','1','5','6','10']]] # ibench
throughput: 0.20 # ibench
uops: 1 # ibench
- name: imul # ibench
operands: # ibench
- class: register # ibench
name: gpr # ibench
- class: register # ibench
name: gpr # ibench
latency: 3 # ibench
port_pressure: [[1, '1']] # ibench
throughput: 1.00 # ibench
uops: 1 # ibench
- name: vaddpd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 2 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vaddpd # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
latency: 2 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vaddpd # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
latency: 3 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vaddpd # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
mask: True # ibench
latency: 3 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vaddpd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 3 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vaddpd # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
mask: True # ibench
latency: 3 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vaddps # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
mask: True # ibench
latency: 3 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vaddps # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
mask: True # ibench
latency: 3 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vaddps # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 3 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vaddps # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 3 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vaddps # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
latency: 3 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vaddps # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
latency: 3 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vaddsd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 2 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vaddsd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 3 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vaddss # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 3 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vaddss # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 2 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vdivpd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 14 # ibench
port_pressure: [[1, '0'], [4, ['0DV']]] # ibench
throughput: 4.0 # ibench
uops: 4 # ibench
- name: vdivpd # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
latency: 14 # asmbench
port_pressure: [[1, '0'], [8, ['0DV']]] # asmbench
throughput: 8.0 # asmbench
uops: 8 # asmbench
- name: vdivpd # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
latency: 23 # ibench
port_pressure: [[1, '0'], [16, ['0DV']]] # ibench
throughput: 16.0 # ibench
uops: 16 # ibench
- name: vdivpd # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
mask: True # ibench
latency: 23 # ibench
port_pressure: [[1, '0'], [16, ['0DV']]] # ibench
throughput: 16.0 # ibench
uops: 16 # ibench
- name: vdivpd # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
mask: True # ibench
latency: 14 # ibench
port_pressure: [[1, '0'], [8, ['0DV']]] # ibench
throughput: 8.0 # ibench
uops: 8 # ibench
- name: vdivpd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 13 # ibench
port_pressure: [[1, '0'], [4, ['0DV']]] # ibench
throughput: 4.0 # ibench
uops: 4 # ibench
- name: vdivps # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
latency: 18 # ibench
port_pressure: [[1, '0'], [10, ['0DV']]] # ibench
throughput: 10.0 # ibench
uops: 10 # ibench
- name: vdivps # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
mask: True # ibench
latency: 18 # ibench
port_pressure: [[1, '0'], [10, ['0DV']]] # ibench
throughput: 10.0 # ibench
uops: 10 # ibench
- name: vdivps # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
mask: True # ibench
latency: 11 # ibench
port_pressure: [[1, '0'], [5, ['0DV']]] # ibench
throughput: 5.0 # ibench
uops: 5 # ibench
- name: vdivps # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
latency: 11 # ibench
port_pressure: [[1, '0'], [5, ['0DV']]] # ibench
throughput: 5.0 # ibench
uops: 5 # ibench
- name: vdivps # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 11 # ibench
port_pressure: [[1, '0'], [3, ['0DV']]] # ibench
throughput: 3.0 # ibench
uops: 3 # ibench
- name: vdivps # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 11 # ibench
port_pressure: [[1, '0'], [3, ['0DV']]] # ibench
throughput: 3.0 # ibench
uops: 3 # ibench
- name: vdivss # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 11 # ibench
port_pressure: [[1, '0'], [3, ['0DV']]] # ibench
throughput: 3.0 # ibench
uops: 4 # ibench
- name: vdivss # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 11 # ibench
port_pressure: [[1, '0'], [3, ['0DV']]] # ibench
throughput: 3.0 # ibench
uops: 3 # ibench
- name: vdivsd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 14 # ibench
port_pressure: [[1, '0'], [4, ['0DV']]] # ibench
throughput: 4.0 # ibench
uops: 4 # ibench
- name: vdivsd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 14 # ibench
port_pressure: [[1, '0'], [4, ['0DV']]] # ibench
throughput: 4.0 # ibench
uops: 4 # ibench
- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd, vfmaddsub213pd, vfmaddsub132pd, vfmaddsub231pd] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd, vfmaddsub213pd, vfmaddsub132pd, vfmaddsub231pd] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd, vfmaddsub213pd, vfmaddsub132pd, vfmaddsub231pd] # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd, vfmaddsub213pd, vfmaddsub132pd, vfmaddsub231pd] # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd, vfmaddsub213pd, vfmaddsub132pd, vfmaddsub231pd] # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
latency: 4 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd, vfmaddsub213pd, vfmaddsub132pd, vfmaddsub231pd] # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps, vfmaddsub213ps, vfmaddsub132ps, vfmaddsub231ps] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps, vfmaddsub213ps, vfmaddsub132ps, vfmaddsub231ps] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps, vfmaddsub213ps, vfmaddsub132ps, vfmaddsub231ps] # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps, vfmaddsub213ps, vfmaddsub132ps, vfmaddsub231ps] # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps, vfmaddsub213ps, vfmaddsub132ps, vfmaddsub231ps] # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
latency: 4 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps, vfmaddsub213ps, vfmaddsub132ps, vfmaddsub231ps] # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmadd213sd, vfmadd132sd, vfmadd231sd, vfnmadd213sd, vfnmadd132sd, vfnmadd231sd, vfmaddsub213sd, vfmaddsub132sd, vfmaddsub231sd] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmadd213sd, vfmadd132sd, vfmadd231sd, vfnmadd213sd, vfnmadd132sd, vfnmadd231sd, vfmaddsub213sd, vfmaddsub132sd, vfmaddsub231sd] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmadd213ss, vfmadd132ss, vfmadd231ss, vfnmadd213ss, vfnmadd132ss, vfnmadd231ss, vfmaddsub213ss, vfmaddsub132ss, vfmaddsub231ss] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmadd213ss, vfmadd132ss, vfmadd231ss, vfnmadd213ss, vfnmadd132ss, vfnmadd231ss, vfmaddsub213ss, vfmaddsub132ss, vfmaddsub231ss] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd, vfmaddsub213pd, vfmaddsub132pd, vfmaddsub231pd] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd, vfmaddsub213pd, vfmaddsub132pd, vfmaddsub231pd] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd, vfmaddsub213pd, vfmaddsub132pd, vfmaddsub231pd] # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd, vfmaddsub213pd, vfmaddsub132pd, vfmaddsub231pd] # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd, vfmaddsub213pd, vfmaddsub132pd, vfmaddsub231pd] # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
latency: 4 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd, vfmaddsub213pd, vfmaddsub132pd, vfmaddsub231pd] # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps, vfmaddsub213ps, vfmaddsub132ps, vfmaddsub231ps] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps, vfmaddsub213ps, vfmaddsub132ps, vfmaddsub231ps] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps, vfmaddsub213ps, vfmaddsub132ps, vfmaddsub231ps] # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps, vfmaddsub213ps, vfmaddsub132ps, vfmaddsub231ps] # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps, vfmaddsub213ps, vfmaddsub132ps, vfmaddsub231ps] # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
latency: 4 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps, vfmaddsub213ps, vfmaddsub132ps, vfmaddsub231ps] # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmsub213sd, vfmsub132sd, vfmsub231sd, vfnmsub213sd, vfnmsub132sd, vfnmsub231sd, vfmaddsub213sd, vfmaddsub132sd, vfmaddsub231sd] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmsub213sd, vfmsub132sd, vfmsub231sd, vfnmsub213sd, vfnmsub132sd, vfnmsub231sd, vfmaddsub213sd, vfmaddsub132sd, vfmaddsub231sd] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmsub213ss, vfmsub132ss, vfmsub231ss, vfnmsub213ss, vfnmsub132ss, vfnmsub231ss, vfmaddsub213ss, vfmaddsub132ss, vfmaddsub231ss] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vfmsub213ss, vfmsub132ss, vfmsub231ss, vfnmsub213ss, vfnmsub132ss, vfnmsub231ss, vfmaddsub213ss, vfmaddsub132ss, vfmaddsub231ss] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vgatherdpd, vgatherqpd] # with load # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: memory # ibench
base: "*" # ibench
offset: "*" # ibench
index: "*" # ibench
scale: "*" # ibench
- class: register # ibench
name: xmm # ibench
latency: 20 # ibench
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [3, ['2','3','11']]] # ibench
throughput: 1.0 # ibench
uops: 9 # ibench
- name: [vgatherdpd, vgatherqpd] # with load # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: memory # ibench
base: "*" # ibench
offset: "*" # ibench
index: "*" # ibench
scale: "*" # ibench
- class: register # ibench
name: ymm # ibench
latency: 22 # ibench
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [6, ['2','3','11']]] # ibench
throughput: 2.0 # ibench
uops: 16 # ibench
- name: [vgatherdpd, vgatherqpd] # with load # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: memory # ibench
base: "*" # ibench
offset: "*" # ibench
index: "*" # ibench
scale: "*" # ibench
- class: register # ibench
name: zmm # ibench
latency: 26 # ibench
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [9, ['2','3','11']]] # ibench
throughput: 3.0 # ibench
uops: 31 # ibench
- name: [vgatherdpd, vgatherqpd] # with load # ibench
operands: # ibench
- class: memory # ibench
base: "*" # ibench
offset: "*" # ibench
index: "*" # ibench
scale: "*" # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 20 # ibench
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [3, ['2','3','11']]] # ibench
throughput: 1.0 # ibench
uops: 9 # ibench
- name: [vgatherdpd, vgatherqpd] # with load # ibench
operands: # ibench
- class: memory # ibench
base: "*" # ibench
offset: "*" # ibench
index: "*" # ibench
scale: "*" # ibench
- class: register # ibench
name: ymm # ibench
mask: True # ibench
latency: 22 # ibench
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [6, ['2','3','11']]] # ibench
throughput: 2.0 # ibench
uops: 16 # ibench
- name: [vgatherdpd, vgatherqpd] # with load # ibench
operands: # ibench
- class: memory # ibench
base: "*" # ibench
offset: "*" # ibench
index: "*" # ibench
scale: "*" # ibench
- class: register # ibench
name: zmm # ibench
mask: True # ibench
latency: 26 # ibench
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [9, ['2','3','11']]] # ibench
throughput: 3.0 # ibench
uops: 31 # ibench
- name: vgatherdps # with load # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: memory # ibench
base: "*" # ibench
offset: "*" # ibench
index: "*" # ibench
scale: "*" # ibench
- class: register # ibench
name: xmm # ibench
latency: 21 # ibench
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [6, ['2','3','11']]] # ibench
throughput: 2.0 # ibench
uops: 15 # ibench
- name: vgatherdps # with load # ibench
operands: # ibench
- class: memory # ibench
base: "*" # ibench
offset: "*" # ibench
index: "*" # ibench
scale: "*" # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 21 # ibench
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [6, ['2','3','11']]] # ibench
throughput: 2.0 # ibench
uops: 15 # ibench
- name: vgatherdps # with load # uops.info
operands: # uops.info
- class: register # uops.info
name: ymm # uops.info
- class: memory # uops.info
base: "*" # uops.info
offset: "*" # uops.info
index: "*" # uops.info
scale: "*" # uops.info
- class: register # uops.info
name: ymm # uops.info
latency: 23 # uops.info
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [9, ['2','3','11']]] # ibench
throughput: 3.0 # uops.info
uops: 23 # uops.info
- name: vgatherdps # with load # uops.info
operands: # uops.info
- class: memory # uops.info
base: "*" # uops.info
offset: "*" # uops.info
index: "*" # uops.info
scale: "*" # uops.info
- class: register # uops.info
name: ymm # uops.info
mask: True # ibench
latency: 23 # uops.info
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [9, ['2','3','11']]] # ibench
throughput: 3.0 # uops.info
uops: 23 #uops.info
- name: vgatherdps # with load # uops.info
operands: # uops.info
- class: register # uops.info
name: zmm # uops.info
- class: memory # uops.info
base: "*" # uops.info
offset: "*" # uops.info
index: "*" # uops.info
scale: "*" # uops.info
- class: register # uops.info
name: zmm # uops.info
latency: 26 # uops.info
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [15, ['2','3','11']]] # ibench
throughput: 5.0 # uops.info
uops: 39 #uops.info
- name: vgatherdps # with load # uops.info
operands: # uops.info
- class: memory # uops.info
base: "*" # uops.info
offset: "*" # uops.info
index: "*" # uops.info
scale: "*" # uops.info
- class: register # uops.info
name: zmm # uops.info
mask: True # ibench
latency: 26 # uops.info
port_pressure: [[1, '015'], [1, '15'], [1, '0'], [15, ['2','3','11']]] # ibench
throughput: 5.0 # uops.info
uops: 39 #uops.info
- name: [vscatterdpd, vscatterqpd] # with store # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: memory # ibench
base: "*" # ibench
offset: "*" # ibench
index: "*" # ibench
scale: "*" # ibench
latency: 0 # ibench
port_pressure: [[1, '0'], [1, '01'], [1, ['0','1','5','6','10']], [8, '78'], [8, '49']] # ibench
throughput: 4.0 # ibench
uops: 8 # ibench
- name: [vscatterdpd, vscatterqpd] # with store # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: memory # ibench
base: "*" # ibench
offset: "*" # ibench
index: "*" # ibench
scale: "*" # ibench
latency: 0 # ibench
port_pressure: [[1, '0'], [1, '01'], [1, ['0','1','5','6','10']], [10, '78'], [10, '49']] # ibench
throughput: 5.0 # ibench
uops: 12 # ibench
- name: [vscatterdpd, vscatterqpd] # with store # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: memory # ibench
base: "*" # ibench
offset: "*" # ibench
index: "*" # ibench
scale: "*" # ibench
latency: 0 # ibench
port_pressure: [[2, '0'], [1, ['0','1','5','6','10']], [14, '78'], [14, '49']] # ibench
throughput: 7.0 # ibench
uops: 20 # ibench
- name: vscatterdps # with store # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: memory # ibench
base: "*" # ibench
offset: "*" # ibench
index: "*" # ibench
scale: "*" # ibench
latency: 0 # ibench
port_pressure: [[1, '0'], [1, '01'], [1, ['0','1','5','6','10']], [10, '78'], [10, '49']] # ibench
throughput: 5.0 # ibench
uops: 12 # ibench
- name: vscatterdps # with store # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: memory # ibench
base: "*" # ibench
offset: "*" # ibench
index: "*" # ibench
scale: "*" # ibench
latency: 0 # ibench
port_pressure: [[1, '0'], [1, '01'], [1, ['0','1','5','6','10']], [14, '78'], [14, '49']] # ibench
throughput: 7.0 # ibench
uops: 20 # ibench
- name: vscatterdps # with store # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: memory # ibench
base: "*" # ibench
offset: "*" # ibench
index: "*" # ibench
scale: "*" # ibench
latency: 0 # ibench
port_pressure: [[2, '0'], [1, ['0','1','5','6','10']], [22, '78'], [22, '49']] # ibench
throughput: 11.0 # ibench
uops: 36 # ibench
- name: vmulpd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vmulpd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vmulpd # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vmulpd # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vmulpd # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
latency: 4 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vmulpd # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vmulps # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vmulps # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vmulps # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vmulps # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vmulps # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
latency: 4 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vmulps # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vmulsd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vmulsd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vmulss # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vmulss # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 4 # ibench
port_pressure: [[1, '01']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vpaddd, vpaddq] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 1 # ibench
port_pressure: [[1, '015']] # ibench
throughput: 0.3333333333333333 # ibench
uops: 1 # ibench
- name: [vpaddd, vpaddq] # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
latency: 1 # ibench
port_pressure: [[1, '015']] # ibench
throughput: 0.3333333333333333 # ibench
uops: 1 # ibench
- name: [vpaddd, vpaddq] # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
latency: 1 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vpaddd, vpaddq] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 1 # ibench
port_pressure: [[1, '015']] # ibench
throughput: 0.3333333333333333 # ibench
uops: 1 # ibench
- name: [vpaddd, vpaddq] # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
mask: True # ibench
latency: 1 # ibench
port_pressure: [[1, '015']] # ibench
throughput: 0.3333333333333333 # ibench
uops: 1 # ibench
- name: [vpaddd, vpaddq] # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
mask: True # ibench
latency: 1 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vrcp14pd, vrcp14ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vrcp14pd, vrcp14ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vrcp14pd, vrcp14ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
latency: 6 # asmbench
port_pressure: [[4, '05']] # asmbench
throughput: 2.0 # asmbench
uops: 3 # asmbench
- name: [vrcp14pd, vrcp14ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
mask: True # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vrcp14pd, vrcp14ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
mask: True # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vrcp14pd, vrcp14ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
mask: True # asmbench
latency: 6 # asmbench
port_pressure: [[4, '05']] # asmbench
throughput: 2.0 # asmbench
uops: 3 # asmbench
- name: vrcpss # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vrcpps # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vrcpps # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vrsqrt14pd, vrsqrt14ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vrsqrt14pd, vrsqrt14ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vrsqrt14pd, vrsqrt14ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
latency: 6 # asmbench
port_pressure: [[4, '05']] # asmbench
throughput: 2.0 # asmbench
uops: 3 # asmbench
- name: [vrsqrt14pd, vrsqrt14ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
mask: True # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vrsqrt14pd, vrsqrt14ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
mask: True # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vrsqrt14pd, vrsqrt14ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
mask: True # asmbench
latency: 6 # asmbench
port_pressure: [[4, '05']] # asmbench
throughput: 2.0 # asmbench
uops: 3 # asmbench
- name: vrsqrtpd # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vrsqrtpd # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vrsqrtps # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vrsqrtps # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vrsqrtpd # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
mask: True # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vrsqrtpd # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
mask: True # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vrsqrtps # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
mask: True # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vrsqrtps # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
mask: True # asmbench
latency: 4 # asmbench
port_pressure: [[1, '0']] # asmbench
throughput: 1.0 # asmbench
uops: 7 # asmbench
- name: vrsqrtpd # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
latency: 10 # asmbench
port_pressure: [[2, '0']] # asmbench
throughput: 2.0 # asmbench
uops: 19 # asmbench
- name: vrsqrtpd # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
mask: True # asmbench
latency: 10 # asmbench
port_pressure: [[2, '0']] # asmbench
throughput: 2.0 # asmbench
uops: 2 # asmbench
- name: vrsqrtps # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
latency: 10 # asmbench
port_pressure: [[2, '0']] # asmbench
throughput: 2.0 # asmbench
uops: 2 # asmbench
- name: vrsqrtps # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
mask: True # asmbench
latency: 10 # asmbench
port_pressure: [[2, '0']] # asmbench
throughput: 2.0 # asmbench
uops: 2 # asmbench
- name: [inc, dec]
operands:
- class: register
name: gpr
latency: 1
port_pressure: [[1, ['0','1','5','6','10']]]
throughput: 0.20
uops: 1
- name: vcvtdq2pd # uops.info
operands: # uops.info
- class: register # uops.info
name: ymm # uops.info
- class: register # uops.info
name: zmm # uops.info
latency: 7 # uops.info
port_pressure: [[1, '0'], [1, '5']] # uops.info
throughput: 1 # uops.info
- name: vcvtss2si # uops.info
operands: # uops.info
- class: register # uops.info
name: xmm # uops.info
- class: register # uops.info
name: gpr # uops.info
latency: 8 # uops.info
port_pressure: [[1, '01'], [1, '5']] # uops.info
throughput: 1 # uops.info
uops: 3 # uops.info
- name: vcvtss2sd # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
latency: 5 # asmbench
port_pressure: [[1, '01'], [1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 2 # asmbench
- name: [vsubpd, vsubps] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 2 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vsubpd, vsubps] # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 3 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vsubpd, vsubps] # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
latency: 2 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vsubpd, vsubps] # ibench
operands: # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
- class: register # ibench
name: ymm # ibench
mask: True # ibench
latency: 3 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vsubpd, vsubps] # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
latency: 3 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: [vsubpd, vsubps] # ibench
operands: # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
- class: register # ibench
name: zmm # ibench
mask: True # ibench
latency: 3 # ibench
port_pressure: [[1, '05']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vsubsd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 2 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vsubsd # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 3 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vsubss # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
mask: True # ibench
latency: 3 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: vsubss # ibench
operands: # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
- class: register # ibench
name: xmm # ibench
latency: 2 # ibench
port_pressure: [[1, '15']] # ibench
throughput: 0.5 # ibench
uops: 1 # ibench
- name: lea # uops.info
operands: # uops.info
- class: memory # uops.info
base: "*" # uops.info
offset: "*" # uops.info
index: "*" # uops.info
scale: "*" # uops.info
- class: register # uops.info
name: gpr # uops.info
latency: 1 # uops.info
port_pressure: [[1, ['0','1','5','6','10']]] # uops.info
throughput: 0.2 # uops.info
uops: 1 # uops.info
- name: [shl, shr, sal, sar] # uops.info
operands: # uops.info
- class: immediate # uops.info
imd: int # uops.info
- class: register # uops.info
name: gpr # uops.info
latency: 1 # uops.info
port_pressure: [[1, '06']] # uops.info
throughput: 0.5 # uops.info
uops: 1 # uops.info
- name: [shl, shr, sal, sar]
operands:
- class: register
name: gpr
latency: 1 # uops.info
port_pressure: [[1, '06']] # uops.info
throughput: 0.5 # uops.info
uops: 1 # uops.info
############## || #################
############## \/ assumed from ICX #################
- name: vinsertf128
operands:
- class: immediate
imd: int
- class: register
name: xmm
- class: register
name: ymm
- class: register
name: ymm
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vinserti128
operands:
- class: immediate
imd: int
- class: register
name: xmm
- class: register
name: ymm
- class: register
name: ymm
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vinsertf32x4
operands:
- class: immediate
imd: int
- class: register
name: xmm
- class: register
name: ymm
- class: register
name: ymm
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vinsertf32x8
operands:
- class: immediate
imd: int
- class: register
name: ymm
- class: register
name: zmm
- class: register
name: zmm
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vinsertf64x2
operands:
- class: immediate
imd: int
- class: register
name: xmm
- class: register
name: ymm
- class: register
name: ymm
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vinsertf64x4
operands:
- class: immediate
imd: int
- class: register
name: ymm
- class: register
name: zmm
- class: register
name: zmm
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vinsertps
operands:
- class: immediate
imd: int
- class: register
name: xmm
- class: register
name: xmm
- class: register
name: xmm
latency: 1
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vinserti64x4
operands:
- class: immediate
imd: int
- class: register
name: ymm
- class: register
name: zmm
- class: register
name: zmm
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vinserti64x2
operands:
- class: immediate
imd: int
- class: register
name: xmm
- class: register
name: ymm
- class: register
name: ymm
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vinserti32x8
operands:
- class: immediate
imd: int
- class: register
name: ymm
- class: register
name: zmm
- class: register
name: zmm
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vinsertf32x4
operands:
- class: immediate
imd: int
- class: register
name: xmm
- class: register
name: ymm
- class: register
name: ymm
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vcvtsi2sd
operands:
- class: register
name: gpr
- class: register
name: xmm
- class: register
name: xmm
latency: 4
port_pressure: [[1, '01'], [1, '5']]
throughput: 1.0
uops: 3
- name: vcvtdq2pd
operands:
- class: register
name: xmm
- class: register
name: ymm
latency: 7
port_pressure: [[1, '01'], [1, '5']]
throughput: 1.0
uops: 2
- name: vcvtsi2ss
operands:
- class: register
name: gpr
- class: register
name: xmm
- class: register
name: xmm
latency: 4
port_pressure: [[1, '01'], [1, '5']]
throughput: 1.0
uops: 3
- name: [vextractf128, vextracti128]
operands:
- class: immediate
imd: int
- class: register
name: ymm
- class: register
name: xmm
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vextractps
operands:
- class: immediate
imd: int
- class: register
name: xmm
- class: register
name: gpr
latency: 4
port_pressure: [[1, '0'], [1, '5']]
throughput: 1.0
uops: 2
- name: [vextractf32x4, vextracti32x4] # uops.info
operands: # uops.info
- class: immediate # uops.info
imd: int # uops.info
- class: register # uops.info
name: ymm # uops.info
- class: register # uops.info
name: xmm # uops.info
latency: 3 # uops.info
port_pressure: [[1, '5']] # uops.info
throughput: 1.0 # uops.info
uops: 1 # uops.info
- name: [vextractf32x4, vextracti32x4] # uops.info
operands: # uops.info
- class: immediate # uops.info
imd: int # uops.info
- class: register # uops.info
name: zmm # uops.info
- class: register # uops.info
name: xmm # uops.info
latency: 3 # uops.info
port_pressure: [[1, '5']] # uops.info
throughput: 1.0 # uops.info
uops: 1 # uops.info
- name: [vextractf32x4, vextracti32x4] # uops.info
operands: # uops.info
- class: immediate # uops.info
imd: int # uops.info
- class: register # uops.info
name: zmm # uops.info
- class: register # uops.info
name: xmm # uops.info
mask: True # uops.info
latency: 3 # uops.info
port_pressure: [[1, '5']] # uops.info
throughput: 1.0 # uops.info
uops: 1 # uops.info
- name: [vextractf32x4, vextracti32x4] # uops.info
operands: # uops.info
- class: immediate # uops.info
imd: int # uops.info
- class: register # uops.info
name: ymm # uops.info
- class: register # uops.info
name: xmm # uops.info
mask: True # uops.info
latency: 3 # uops.info
port_pressure: [[1, '5']] # uops.info
throughput: 1.0 # uops.info
uops: 1 # uops.info
- name: [vextractf32x8, vextracti32x8] # uops.info
operands: # uops.info
- class: immediate # uops.info
imd: int # uops.info
- class: register # uops.info
name: zmm # uops.info
- class: register # uops.info
name: ymm # uops.info
mask: True # uops.info
latency: 3 # uops.info
port_pressure: [[1, '5']] # uops.info
throughput: 1.0 # uops.info
uops: 1 # uops.info
- name: [vextractf32x8, vextracti32x8] # uops.info
operands: # uops.info
- class: immediate # uops.info
imd: int # uops.info
- class: register # uops.info
name: zmm # uops.info
- class: register # uops.info
name: ymm # uops.info
latency: 3 # uops.info
port_pressure: [[1, '5']] # uops.info
throughput: 1.0 # uops.info
uops: 1 # uops.info
- name: [vextractf64x2, vextracti64x2] # uops.info
operands: # uops.info
- class: immediate # uops.info
imd: int # uops.info
- class: register # uops.info
name: ymm # uops.info
- class: register # uops.info
name: xmm # uops.info
latency: 3 # uops.info
port_pressure: [[1, '5']] # uops.info
throughput: 1.0 # uops.info
uops: 1 # uops.info
- name: [vextractf64x2, vextracti64x2] # uops.info
operands: # uops.info
- class: immediate # uops.info
imd: int # uops.info
- class: register # uops.info
name: ymm # uops.info
- class: register # uops.info
name: xmm # uops.info
mask: True # uops.info
latency: 3 # uops.info
port_pressure: [[1, '5']] # uops.info
throughput: 1.0 # uops.info
uops: 1 # uops.info
- name: [vextractf64x2, vextracti64x2] # uops.info
operands: # uops.info
- class: immediate # uops.info
imd: int # uops.info
- class: register # uops.info
name: zmm # uops.info
- class: register # uops.info
name: xmm # uops.info
mask: True # uops.info
latency: 3 # uops.info
port_pressure: [[1, '5']] # uops.info
throughput: 1.0 # uops.info
uops: 1 # uops.info
- name: [vextractf64x2, vextracti64x2] # uops.info
operands: # uops.info
- class: immediate # uops.info
imd: int # uops.info
- class: register # uops.info
name: zmm # uops.info
- class: register # uops.info
name: xmm # uops.info
latency: 3 # uops.info
port_pressure: [[1, '5']] # uops.info
throughput: 1.0 # uops.info
uops: 1 # uops.info
- name: [vextractf64x4, vextracti64x4] # uops.info
operands: # uops.info
- class: immediate # uops.info
imd: int # uops.info
- class: register # uops.info
name: zmm # uops.info
- class: register # uops.info
name: ymm # uops.info
latency: 3 # uops.info
port_pressure: [[1, '5']] # uops.info
throughput: 1.0 # uops.info
uops: 1 # uops.info
- name: [vextractf64x4, vextracti64x4] # uops.info
operands: # uops.info
- class: immediate # uops.info
imd: int # uops.info
- class: register # uops.info
name: zmm # uops.info
- class: register # uops.info
name: ymm # uops.info
mask: True # uops.info
latency: 3 # uops.info
port_pressure: [[1, '5']] # uops.info
throughput: 1.0 # uops.info
uops: 1 # uops.info
- name: vpinsrd # asmbench
operands: # asmbench
- class: immediate # asmbench
imd: int # asmbench
- class: register # asmbench
name: gpr # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '15'], [1, '1']] # asmbench
throughput: 1.0 # asmbench
uops: 2 # asmbench
- name: vpalignr # asmbench
operands: # asmbench
- class: immediate # asmbench
imd: int # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vpalignr # asmbench
operands: # asmbench
- class: immediate # asmbench
imd: int # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vpalignr # asmbench
operands: # asmbench
- class: immediate # asmbench
imd: int # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vpalignr # asmbench
operands: # asmbench
- class: immediate # asmbench
imd: int # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vpalignr # asmbench
operands: # asmbench
- class: immediate # asmbench
imd: int # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vpalignr # asmbench
operands: # asmbench
- class: immediate # asmbench
imd: int # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vperm2f128, vperm2i128] # asmbench
operands: # asmbench
- class: immediate # asmbench
imd: int # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
latency: 3 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vpermd # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
latency: 3 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: vpermd # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
mask: True # asmbench
latency: 3 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermd, vpermt2q] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
latency: 3 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermd, vpermt2q] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
mask: True # asmbench
latency: 3 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermpd, vpermps] # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
latency: 3 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermpd, vpermps] # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
mask: True # asmbench
latency: 3 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermpd, vpermps] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
latency: 3 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermpd, vpermps] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
mask: True # asmbench
latency: 3 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: immediate
imd: int
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: immediate
imd: int
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: immediate
imd: int
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: immediate
imd: int
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: immediate
imd: int
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermilpd, vpermilps] # asmbench
operands: # asmbench
- class: immediate
imd: int
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermt2ps, vpermi2ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
latency: 3 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermt2ps, vpermi2ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
mask: True # asmbench
latency: 3 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermt2ps, vpermi2ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
latency: 3 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermt2ps, vpermi2ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
mask: True # asmbench
latency: 3 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermt2ps, vpermi2ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
latency: 3 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpermt2ps, vpermi2ps] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
mask: True # asmbench
latency: 3 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench
operands: # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
- class: register # asmbench
name: xmm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench
operands: # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
- class: register # asmbench
name: ymm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench
operands: # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
- class: register # asmbench
name: zmm # asmbench
mask: True # asmbench
latency: 1 # asmbench
port_pressure: [[1, '5']] # asmbench
throughput: 1.0 # asmbench
uops: 1 # asmbench
- name: [vpcmpgtb, vpcmpgtw, vpcmpgtd, vpcmpgtq]
operands:
- class: register
name: xmm
- class: register
name: xmm
- class: register
name: k
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: [vpcmpgtb, vpcmpgtw, vpcmpgtd, vpcmpgtq]
operands:
- class: register
name: ymm
- class: register
name: ymm
- class: register
name: k
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: [vpcmpgtb, vpcmpgtw, vpcmpgtd, vpcmpgtq, vpcmpeqb, vpcmpeqw, vpcmpeqd, vpcmpeqq]
operands:
- class: register
name: zmm
- class: register
name: zmm
- class: register
name: k
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vpcmpd
operands:
- class: immediate
imd: int
- class: register
name: xmm
- class: register
name: xmm
- class: register
name: k
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vpcmpd
operands:
- class: immediate
imd: int
- class: register
name: ymm
- class: register
name: ymm
- class: register
name: k
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vpcmpd
operands:
- class: immediate
imd: int
- class: register
name: zmm
- class: register
name: zmm
- class: register
name: k
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: [vpcmpeqb, vpcmpeqw, vpcmpeqd, vpcmpeqq]
operands:
- class: register
name: xmm
- class: register
name: xmm
- class: register
name: xmm
latency: 1
port_pressure: [[1, '01']]
throughput: 0.5
uops: 1
- name: [vpcmpeqb, vpcmpeqw, vpcmpeqd, vpcmpeqq]
operands:
- class: register
name: ymm
- class: register
name: ymm
- class: register
name: ymm
latency: 1
port_pressure: [[1, '01']]
throughput: 0.5
uops: 1
- name: [vcmpltpd, vcmpltps] # uops.info
operands: # uops.info
- class: register # uops.info
name: zmm # uops.info
- class: register # uops.info
name: zmm # uops.info
- class: register # uops.info
name: k # uops.info
mask: True # uops.info
latency: 4 # uops.info
port_pressure: [[1, '05']] # uops.info
throughput: 0.5 # uops.info
uops: 1 # uops.info
- name: [vcmpltpd, vcmpltps] # uops.info
operands: # uops.info
- class: register # uops.info
name: ymm # uops.info
- class: register # uops.info
name: ymm # uops.info
- class: register # uops.info
name: ymm # uops.info
latency: 4 # uops.info
port_pressure: [[1, '05']] # uops.info
throughput: 0.5 # uops.info
uops: 1 # uops.info
- name: VCMPPS
operands:
- class: immediate
imd: int
- class: register
name: xmm
- class: register
name: xmm
- class: register
name: xmm
latency: 4
port_pressure: [[1, '01']]
throughput: 0.5
uops: 1
- name: VCMPPS
operands:
- class: immediate
imd: int
- class: register
name: ymm
- class: register
name: ymm
- class: register
name: ymm
latency: 4
port_pressure: [[1, '01']]
throughput: 0.5
uops: 1
- name: VCMPPD
operands:
- class: immediate
imd: int
- class: register
name: xmm
- class: register
name: xmm
- class: register
name: xmm
latency: 4
port_pressure: [[1, '01']]
throughput: 0.5
uops: 1
- name: VCMPPD
operands:
- class: immediate
imd: int
- class: register
name: ymm
- class: register
name: ymm
- class: register
name: ymm
latency: 4
port_pressure: [[1, '01']]
throughput: 0.5
uops: 1
- name: VCMPPS
operands:
- class: immediate
imd: int
- class: register
name: zmm
- class: register
name: zmm
- class: register
name: k
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: VCMPPS
operands:
- class: immediate
imd: int
- class: register
name: zmm
- class: register
name: zmm
- class: register
name: k
mask: True
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: VCMPPS
operands:
- class: immediate
imd: int
- class: register
name: xmm
- class: register
name: xmm
- class: register
name: k
mask: True
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: VCMPPS
operands:
- class: immediate
imd: int
- class: register
name: ymm
- class: register
name: ymm
- class: register
name: k
mask: True
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: VCMPPD
operands:
- class: immediate
imd: int
- class: register
name: zmm
- class: register
name: zmm
- class: register
name: k
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: VCMPPD
operands:
- class: immediate
imd: int
- class: register
name: zmm
- class: register
name: zmm
- class: register
name: k
mask: True
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: VCMPPD
operands:
- class: immediate
imd: int
- class: register
name: xmm
- class: register
name: xmm
- class: register
name: k
mask: True
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: VCMPPD
operands:
- class: immediate
imd: int
- class: register
name: ymm
- class: register
name: ymm
- class: register
name: k
mask: True
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vpunpckhqdq
operands:
- class: register
name: xmm
- class: register
name: xmm
- class: register
name: xmm
latency: 1
port_pressure: [[1, '15']]
throughput: 0.5
uops: 1
- name: vpunpckhqdq
operands:
- class: register
name: ymm
- class: register
name: ymm
- class: register
name: ymm
latency: 1
port_pressure: [[1, '15']]
throughput: 0.5
uops: 1
- name: vpunpckhqdq
operands:
- class: register
name: zmm
- class: register
name: zmm
- class: register
name: zmm
latency: 1
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
########### /\ ##########
########### || assumed from ICX ##########
- name: [AND, OR, XOR, TEST]
operands:
- class: immediate
imd: int
- class: register
name: gpr
latency: 1
port_pressure: [[1, ['0','1','5','6','10']]]
throughput: 0.20
uops: 1
- name: [AND, OR, XOR, TEST]
operands:
- class: register
name: gpr
- class: register
name: gpr
latency: 1
port_pressure: [[1, ['0','1','5','6','10']]]
throughput: 0.20
uops: 1
- name: NOT
operands:
- class: register
name: gpr
latency: 1
port_pressure: [[1, ['0','1','5','6','10']]]
throughput: 0.20
uops: 1
- name: RET
operands: []
latency: 0
port_pressure: [[1, '49'], [1, '78']]
throughput: 0.5
uops: 2
- name: CALL
operands:
- class: identifier
latency: 0
port_pressure: [[1, '49'], [1, '78']]
throughput: 0.5
uops: 2
- name: PTEST
operands:
- class: register
name: xmm
- class: register
name: xmm
latency: 4
port_pressure: [[1, '0'], [1, '5']]
throughput: 1.0
uops: 2
- name: VPTEST
operands:
- class: register
name: xmm
- class: register
name: xmm
latency: 4
port_pressure: [[1, '0'], [1, '5']]
throughput: 1.0
uops: 2
- name: VPTEST
operands:
- class: register
name: ymm
- class: register
name: ymm
latency: 6
port_pressure: [[1, '0'], [1, '5']]
throughput: 1.0
uops: 2
- name: [VTESTPD, VTESTPS]
operands:
- class: register
name: xmm
- class: register
name: xmm
latency: 3
port_pressure: [[1, '0']]
throughput: 1.0
uops: 1
- name: [VTESTPD, VTESTPS]
operands:
- class: register
name: ymm
- class: register
name: ymm
latency: 5
port_pressure: [[1, '0']]
throughput: 1.0
uops: 1
- name: VXORPD
operands:
- class: register
name: xmm
- class: register
name: xmm
- class: register
name: xmm
latency: 1
port_pressure: [[1, ['0','1','5','6','10']]]
throughput: 0.20
uops: 1
- name: VXORPD
operands:
- class: register
name: ymm
- class: register
name: ymm
- class: register
name: ymm
latency: 1
port_pressure: [[1, ['0','1','5','6','10']]]
throughput: 0.20
uops: 1
- name: VXORPS
operands:
- class: register
name: xmm
- class: register
name: xmm
- class: register
name: xmm
latency: 1
port_pressure: [[1, ['0','1','5','6','10']]]
throughput: 0.20
uops: 1
- name: VXORPS
operands:
- class: register
name: ymm
- class: register
name: ymm
- class: register
name: ymm
latency: 1
port_pressure: [[1, ['0','1','5','6','10']]]
throughput: 0.20
uops: 1
- name: VPBROADCASTD
operands:
- class: register
name: gpr
- class: register
name: zmm
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: [VBROADCASTSS, VBROADCASTI32X2]
operands:
- class: register
name: xmm
- class: register
name: xmm
latency: 1
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: [VBROADCASTSD, VBROADCASTSS, VBROADCASTI32X2]
operands:
- class: register
name: xmm
- class: register
name: ymm
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: [VBROADCASTSD, VBROADCASTSS, VBROADCASTI32X2]
operands:
- class: register
name: xmm
- class: register
name: zmm
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: VBROADCASTI32X2 # with load
operands:
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
- class: register
name: xmm
latency: 4
port_pressure: [[1, ['2', '3', '11']]]
throughput: 0.33333333
uops: 1
- name: [VBROADCASTSD, VBROADCASTSS, VBROADCASTI64X2, VBROADCASTI32X4] # with load
operands:
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
- class: register
name: ymm
latency: 5
port_pressure: [[1, ['2', '3', '11']]]
throughput: 0.333333
uops: 1
- name: [VBROADCASTSD, VBROADCASTSS, VBROADCASTI32X4, VBROADCASTI32X8, VBROADCASTI64X2, VBROADCASTI64X4] # with load
operands:
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
- class: register
name: zmm
latency: 5
port_pressure: [[1, '23'], [0.5, ['11']]]
throughput: 1.0
uops: 1
- name: vandpd
operands:
- class: register
name: xmm
- class: register
name: xmm
- class: register
name: xmm
latency: 1
port_pressure: [[1, '015']]
throughput: 0.33333
uops: 1
- name: vandpd
operands:
- class: register
name: ymm
- class: register
name: ymm
- class: register
name: ymm
latency: 1
port_pressure: [[1, '015']]
throughput: 0.33333
uops: 1
- name: vandpd
operands:
- class: register
name: zmm
- class: register
name: zmm
- class: register
name: zmm
latency: 1
port_pressure: [[1, '05']]
throughput: 0.5
uops: 1
- name: vshuff64x2
operands:
- class: immediate
imd: int
- class: register
name: zmm
- class: register
name: zmm
- class: register
name: zmm
latency: 3
port_pressure: [[1, '5']]
throughput: 1.0
uops: 1
- name: vmovd
operands:
- class: register
name: gpr
- class: register
name: xmm
latency: 1
port_pressure: [[1, ['0', '1', '5', '6', '10']]]
throughput: 0.2
uops: 1.0
- name: vmov
operands:
- class: register
name: gpr
- class: register
name: xmm
latency: 1
port_pressure: [[1, ['0', '1', '5', '6', '10']]]
throughput: 0.2
uops: 1.0
- name: [vpor, vpxor, vpord, vpxord]
operands:
- class: register
name: xmm
- class: register
name: xmm
- class: register
name: xmm
latency: 1
port_pressure: [[1, '015']]
throughput: 0.3333333
uops: 1
- name: [vpor, vpxor, vpord, vpxord]
operands:
- class: register
name: ymm
- class: register
name: ymm
- class: register
name: ymm
latency: 1
port_pressure: [[1, '015']]
throughput: 0.3333333
uops: 1
- name: [vpor, vpxor, vpord, vpxord]
operands:
- class: register
name: zmm
- class: register
name: zmm
- class: register
name: zmm
latency: 1
port_pressure: [[1, '05']]
throughput: 0.5
uops: 1
- name: [kxorb, kxorw, kxord, kxorq, kxnorb, kxnorw, kxnord, kxnorq]
operands:
- class: register
name: k
- class: register
name: k
- class: register
name: k
latency: 1
port_pressure: [[1, '0']]
throughput: 1.0
uops: 1
- name: [knotb, knotw, knotd, knotq]
operands:
- class: register
name: k
- class: register
name: k
latency: 1
port_pressure: [[1, '0']]
throughput: 1.0
uops: 1
- name: [korb, korw, kord, korq, kandb, kandw, kand, kandq, kandnb, kandnw, kandnd, kandnq]
operands:
- class: register
name: k
- class: register
name: k
- class: register
name: k
latency: 1
port_pressure: [[1, '0']]
throughput: 1.0
uops: 1
- name: [ktestb, ktestw, ktestd, ktestq, kortestb, kortestw, kortestd, kortestq]
operands:
- class: register
name: k
- class: register
name: k
latency: 1
port_pressure: [[1, '0']]
throughput: 1.0
uops: 1
- name: [vfpclasspd]
operands:
- class: immediate
imd: int
- class: register
name: "*"
- class: register
name: k
latency: 3 # uops.info
port_pressure: [[1, '5']] # uops.info
throughput: 1.0 # ibench
uops: 1
- name: [cltq, cdq, cdqe]
operands: []
latency: 1 # uops.info
port_pressure: [[1, '06']] # uops.info
throughput: 0.5 # uops.info
uops: 1