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https://github.com/RRZE-HPC/OSACA.git
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228 lines
10 KiB
Python
Executable File
228 lines
10 KiB
Python
Executable File
#!/usr/bin/env python3
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import copy
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from itertools import chain, product
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import networkx as nx
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from osaca.parser import AttrDict
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from osaca.semantics import MachineModel
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class KernelDG(nx.DiGraph):
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def __init__(self, parsed_kernel, parser, hw_model: MachineModel):
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self.kernel = parsed_kernel
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self.parser = parser
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self.model = hw_model
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self.dg = self.create_DG(self.kernel)
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self.loopcarried_deps = self.check_for_loopcarried_dep(self.kernel)
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import pdb
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pdb.set_trace()
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def create_DG(self, kernel):
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# 1. go through kernel instruction forms and add them as node attribute
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# 2. find edges (to dependend further instruction)
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# 3. get LT value and set as edge weight
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dg = nx.DiGraph()
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for i, instruction_form in enumerate(kernel):
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dg.add_node(instruction_form['line_number'])
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dg.nodes[instruction_form['line_number']]['instruction_form'] = instruction_form
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# add load as separate node if existent
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if 'performs_load' in instruction_form['flags']:
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regs = [
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op for op in instruction_form['operands']['destination'] if 'register' in op
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]
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if (
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len(regs) > 1
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and len(set([self.parser.get_reg_type(x['register']) for x in regs])) != 1
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):
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load_lat = max(self.model['load_latency'].values())
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else:
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load_lat = self.model['load_latency'][
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self.parser.get_reg_type(regs[0]['register'])
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]
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# add new node
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dg.add_node(instruction_form['line_number'] + 0.1)
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dg.nodes[instruction_form['line_number'] + 0.1][
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'instruction_form'
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] = instruction_form
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# and set LD latency as edge weight
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dg.add_edge(
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instruction_form['line_number'] + 0.1,
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instruction_form['line_number'],
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latency=load_lat,
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)
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for dep in self.find_depending(instruction_form, kernel[i + 1 :]):
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dg.add_edge(
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instruction_form['line_number'],
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dep['line_number'],
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latency=instruction_form['latency'],
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)
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dg.nodes[dep['line_number']]['instruction_form'] = dep
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return dg
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def check_for_loopcarried_dep(self, kernel):
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multiplier = len(kernel) + 1
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# increase line number for second kernel loop
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kernel_length = len(kernel)
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first_line_no = kernel[0].line_number
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kernel_copy = [AttrDict.convert_dict(d) for d in copy.deepcopy(kernel)]
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tmp_kernel = kernel + kernel_copy
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for i, instruction_form in enumerate(tmp_kernel[kernel_length:]):
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tmp_kernel[i + kernel_length].line_number = instruction_form.line_number * multiplier
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# get dependency graph
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dg = self.create_DG(tmp_kernel)
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# build cyclic loop-carried dependencies
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loopcarried_deps = [
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(node, list(nx.algorithms.simple_paths.all_simple_paths(dg, node, node * multiplier)))
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for node in dg.nodes
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if node < first_line_no * multiplier and node == int(node)
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]
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# filter others and create graph
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loopcarried_deps = list(
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chain.from_iterable(
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[list(product([dep_chain[0]], dep_chain[1])) for dep_chain in loopcarried_deps]
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)
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)
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# adjust line numbers, filter duplicates
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# and add reference to kernel again
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loopcarried_deps_dict = {}
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tmp_list = []
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for i, dep in enumerate(loopcarried_deps):
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nodes = [int(n / multiplier) for n in dep[1] if n >= first_line_no * multiplier]
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loopcarried_deps[i] = (dep[0], nodes)
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for dep in loopcarried_deps:
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is_subset = False
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for other_dep in [x for x in loopcarried_deps if x[0] != dep[0]]:
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if set(dep[1]).issubset(set(other_dep[1])) and dep[0] in other_dep[1]:
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is_subset = True
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if not is_subset:
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tmp_list.append(dep)
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loopcarried_deps = tmp_list
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for dep in loopcarried_deps:
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nodes = [self._get_node_by_lineno(n) for n in dep[1]]
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loopcarried_deps_dict[dep[0]] = {
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'root': self._get_node_by_lineno(dep[0]),
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'dependencies': nodes,
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}
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return loopcarried_deps_dict
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def _get_node_by_lineno(self, lineno):
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return [instr for instr in self.kernel if instr.line_number == lineno][0]
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def get_critical_path(self):
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if nx.algorithms.dag.is_directed_acyclic_graph(self.dg):
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longest_path = nx.algorithms.dag.dag_longest_path(self.dg, weight='latency')
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# add LD latency to instruction
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for line_number in longest_path:
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if line_number != int(line_number) and int(line_number) in longest_path:
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self._get_node_by_lineno(int(line_number))['latency'] += self.dg.edges[
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(line_number, int(line_number))
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]['latency']
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return [x for x in self.kernel if x['line_number'] in longest_path]
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else:
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# split to DAG
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raise NotImplementedError('Kernel is cyclic.')
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def get_loopcarried_dependencies(self):
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if nx.algorithms.dag.is_directed_acyclic_graph(self.dg):
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return self.loopcarried_deps
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else:
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# split to DAG
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raise NotImplementedError('Kernel is cyclic.')
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def find_depending(self, instruction_form, kernel, include_write=False):
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if instruction_form.operands is None:
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return
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for dst in instruction_form.operands.destination + instruction_form.operands.src_dst:
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if 'register' in dst:
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# Check for read of register until overwrite
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for instr_form in kernel:
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if self.is_read(dst.register, instr_form):
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yield instr_form
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if self.is_written(dst.register, instr_form):
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# operand in src_dst list
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if include_write:
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yield instr_form
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break
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elif self.is_written(dst.register, instr_form):
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if include_write:
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yield instr_form
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break
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elif 'memory' in dst:
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# Check if base register is altered during memory access
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if 'pre_indexed' in dst.memory or 'post_indexed' in dst.memory:
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# Check for read of base register until overwrite
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for instr_form in kernel:
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if self.is_read(dst.memory.base, instr_form):
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yield instr_form
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if self.is_written(dst.memory.base, instr_form):
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# operand in src_dst list
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if include_write:
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yield instr_form
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break
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elif self.is_written(dst.memory.base, instr_form):
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if include_write:
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yield instr_form
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break
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def get_dependent_instruction_forms(self, instr_form=None, line_number=None):
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"""
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Returns iterator
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"""
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if not instr_form and not line_number:
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raise ValueError('Either instruction form or line_number required.')
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line_number = line_number if line_number else instr_form['line_number']
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if self.dg.has_node(line_number):
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return self.dg.successors(line_number)
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return iter([])
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def is_read(self, register, instruction_form):
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is_read = False
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if instruction_form.operands is None:
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return is_read
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for src in instruction_form.operands.source + instruction_form.operands.src_dst:
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if 'register' in src:
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is_read = self.parser.is_reg_dependend_of(register, src.register) or is_read
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if 'memory' in src:
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if src.memory.base is not None:
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is_read = self.parser.is_reg_dependend_of(register, src.memory.base) or is_read
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if src.memory.index is not None:
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is_read = (
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self.parser.is_reg_dependend_of(register, src.memory.index) or is_read
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)
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# Check also if read in destination memory address
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for dst in instruction_form.operands.destination + instruction_form.operands.src_dst:
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if 'memory' in dst:
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if dst.memory.base is not None:
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is_read = self.parser.is_reg_dependend_of(register, dst.memory.base) or is_read
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if dst.memory.index is not None:
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is_read = (
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self.parser.is_reg_dependend_of(register, dst.memory.index) or is_read
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)
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return is_read
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def is_written(self, register, instruction_form):
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is_written = False
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if instruction_form.operands is None:
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return is_written
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for dst in instruction_form.operands.destination + instruction_form.operands.src_dst:
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if 'register' in dst:
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is_written = self.parser.is_reg_dependend_of(register, dst.register) or is_written
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if 'memory' in dst:
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if 'pre_indexed' in dst.memory or 'post_indexed' in dst.memory:
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is_written = (
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self.parser.is_reg_dependend_of(register, dst.memory.base) or is_written
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)
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# Check also for possible pre- or post-indexing in memory addresses
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for src in instruction_form.operands.source + instruction_form.operands.src_dst:
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if 'memory' in src:
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if 'pre_indexed' in src.memory or 'post_indexed' in src.memory:
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is_written = (
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self.parser.is_reg_dependend_of(register, src.memory.base) or is_written
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)
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return is_written
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