mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2025-12-16 00:50:06 +01:00
074118dee0
- Modified RISC-V parser to use x-register names instead of ABI names - Added new vector instructions (vsetvli, vle8.v, vse8.v, vfmacc.vv, vfmul.vf) - Added floating point instructions (fmul.d) - Added unconditional jump instruction (j) - Updated tests to match new register naming convention - Added new RISC-V example files - Updated .gitignore to exclude test environment and old examples
16 lines
242 B
ArmAsm
16 lines
242 B
ArmAsm
gs_riscv:
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.L5:
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fld fa2,0(a3)
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fld fa3,0(a5)
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fld fa4,0(a4)
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fadd.d fa5,fa5,fa2
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addi a5,a5,8
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addi a3,a3,8
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addi a4,a4,8
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fadd.d fa5,fa5,fa3
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fadd.d fa5,fa5,fa4
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fmul.d fa5,fa5,fa0
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fsd fa5,-16(a5)
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bne a2,a5,.L5
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addi a0,a0,8
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bne a6,a0,.L4 |