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https://github.com/RRZE-HPC/OSACA.git
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074118dee0
- Modified RISC-V parser to use x-register names instead of ABI names - Added new vector instructions (vsetvli, vle8.v, vse8.v, vfmacc.vv, vfmul.vf) - Added floating point instructions (fmul.d) - Added unconditional jump instruction (j) - Updated tests to match new register naming convention - Added new RISC-V example files - Updated .gitignore to exclude test environment and old examples
7 lines
94 B
ArmAsm
7 lines
94 B
ArmAsm
sum_reduction_riscv:
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.L3:
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fld fa5,0(a0)
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addi a0,a0,8
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fadd.d fa0,fa0,fa5
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bne a1,a0,.L3
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ret |