mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2025-12-16 00:50:06 +01:00
074118dee0
- Modified RISC-V parser to use x-register names instead of ABI names - Added new vector instructions (vsetvli, vle8.v, vse8.v, vfmacc.vv, vfmul.vf) - Added floating point instructions (fmul.d) - Added unconditional jump instruction (j) - Updated tests to match new register naming convention - Added new RISC-V example files - Updated .gitignore to exclude test environment and old examples
11 lines
175 B
ArmAsm
11 lines
175 B
ArmAsm
update_riscv:
|
|
.L3:
|
|
vsetvli a5,a1,e64,m1,ta,ma
|
|
vle64.v v1,0(a0)
|
|
slli a3,a5,3
|
|
sub a1,a1,a5
|
|
add a0,a0,a3
|
|
vfmul.vf v1,v1,fa0
|
|
vse64.v v1,0(a4)
|
|
add a4,a4,a3
|
|
bne a1,zero,.L3 |