Metehan Dundar 074118dee0 RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests ...

- Modified RISC-V parser to use x-register names instead of ABI names
- Added new vector instructions (vsetvli, vle8.v, vse8.v, vfmacc.vv, vfmul.vf)
- Added floating point instructions (fmul.d)
- Added unconditional jump instruction (j)
- Updated tests to match new register naming convention
- Added new RISC-V example files
- Updated .gitignore to exclude test environment and old examples

2025-06-30 00:28:52 +02:00

..

data

RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests

2025-06-30 00:28:52 +02:00

parser

RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests

2025-06-30 00:28:52 +02:00

semantics

RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests

2025-06-30 00:28:52 +02:00

__init__.py

Add RISC-V support and update version to 0.6.2

2025-03-21 17:16:39 +01:00

__main__.py

added __main__.py

2020-11-09 08:27:31 +01:00

db_interface.py

Add RISC-V support and update version to 0.6.2

2025-03-21 17:16:39 +01:00

frontend.py

Black formatting

2024-05-02 17:04:56 +02:00

osaca.py

RISC-V: Update parser to use x-register names, add vector and FP instructions, fix tests

2025-06-30 00:28:52 +02:00

utils.py

applied flake8 and black rules

2021-08-26 16:58:19 +02:00