mirror of
https://github.com/RRZE-HPC/OSACA.git
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08440ed5e1
Validating of OSACA predictions for IVB, SKX, ZEN1, ZEN2, A64FX and TX2 with different kernels. build_and_run.py contains the configuration used at RRZE's testcluster and UR's qpace4, Analysis.ipynb contains the analysis script and results. Raw data from measurements (122MB) will be attached to next OSACA release. For now, find the raw data here: https://hawo.net/~sijuhamm/d/UPIhBOtz/validation-data.tar.gz The analysis report can be viewed at https://nbviewer.jupyter.org/github/RRZE-HPC/OSACA/blob/validation/validation/Analysis.ipynb Quite a few changes on OSACA included: Feature: register change tracking via semantic understanding of operations Feature: recording LCD latency along path and exposing this to frontend Feature: support for memory reference aliases Feature: store throughput scaling (similar to load throughput scaling) Fix: model importer works with latest uops.info export Fix: immediate type tracking on ARM now preserves type in internal representaion Removed unused KerncraftAPI
433 lines
18 KiB
Python
Executable File
433 lines
18 KiB
Python
Executable File
#!/usr/bin/env python3
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"""
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Unit tests for ARMv8 AArch64 assembly parser
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"""
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import os
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import unittest
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from pyparsing import ParseException
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from osaca.parser import AttrDict, ParserAArch64
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class TestParserAArch64(unittest.TestCase):
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@classmethod
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def setUpClass(self):
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self.parser = ParserAArch64()
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with open(self._find_file("triad_arm_iaca.s")) as f:
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self.triad_code = f.read()
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##################
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# Test
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##################
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def test_comment_parser(self):
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self.assertEqual(self._get_comment(self.parser, "// some comments"), "some comments")
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self.assertEqual(self._get_comment(self.parser, "\t\t//AA BB CC \t end \t"), "AA BB CC end")
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self.assertEqual(
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self._get_comment(self.parser, "\t//// comment //// comment"),
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"// comment //// comment",
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)
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def test_label_parser(self):
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self.assertEqual(self._get_label(self.parser, "main:").name, "main")
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self.assertEqual(self._get_label(self.parser, "..B1.10:").name, "..B1.10")
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self.assertEqual(self._get_label(self.parser, ".2.3_2_pack.3:").name, ".2.3_2_pack.3")
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self.assertEqual(self._get_label(self.parser, ".L1:\t\t\t//label1").name, ".L1")
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self.assertEqual(
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" ".join(self._get_label(self.parser, ".L1:\t\t\t//label1").comment), "label1"
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)
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with self.assertRaises(ParseException):
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self._get_label(self.parser, "\t.cfi_startproc")
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def test_directive_parser(self):
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self.assertEqual(self._get_directive(self.parser, "\t.text").name, "text")
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self.assertEqual(len(self._get_directive(self.parser, "\t.text").parameters), 0)
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self.assertEqual(self._get_directive(self.parser, "\t.align\t16,0x90").name, "align")
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self.assertEqual(len(self._get_directive(self.parser, "\t.align\t16,0x90").parameters), 2)
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self.assertEqual(
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self._get_directive(self.parser, "\t.align\t16,0x90").parameters[1], "0x90"
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)
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self.assertEqual(
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self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[
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"name"
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],
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"byte",
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)
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self.assertEqual(
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self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[
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"parameters"
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][2],
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"144",
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)
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self.assertEqual(
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" ".join(
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self._get_directive(self.parser, " .byte 100,103,144 //IACA START")[
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"comment"
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]
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),
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"IACA START",
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)
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def test_parse_instruction(self):
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instr1 = "\t\tvcvt.F32.S32 w1, w2\t\t\t//12.27"
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instr2 = "b.lo ..B1.4 \t"
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instr3 = " mov x2,#0x222 //NOT IACA END"
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instr4 = "str x28, [sp, x1, lsl #4] //12.9"
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instr5 = "ldr x0, [x0, #:got_lo12:q2c]"
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instr6 = "adrp x0, :got:visited"
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instr7 = "fadd v17.2d, v16.2d, v1.2d"
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parsed_1 = self.parser.parse_instruction(instr1)
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parsed_2 = self.parser.parse_instruction(instr2)
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parsed_3 = self.parser.parse_instruction(instr3)
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parsed_4 = self.parser.parse_instruction(instr4)
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parsed_5 = self.parser.parse_instruction(instr5)
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parsed_6 = self.parser.parse_instruction(instr6)
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parsed_7 = self.parser.parse_instruction(instr7)
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self.assertEqual(parsed_1.instruction, "vcvt.F32.S32")
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self.assertEqual(parsed_1.operands[0].register.name, "1")
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self.assertEqual(parsed_1.operands[0].register.prefix, "w")
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self.assertEqual(parsed_1.operands[1].register.name, "2")
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self.assertEqual(parsed_1.operands[1].register.prefix, "w")
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self.assertEqual(parsed_1.comment, "12.27")
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self.assertEqual(parsed_2.instruction, "b.lo")
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self.assertEqual(parsed_2.operands[0].identifier.name, "..B1.4")
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self.assertEqual(len(parsed_2.operands), 1)
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self.assertIsNone(parsed_2.comment)
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self.assertEqual(parsed_3.instruction, "mov")
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self.assertEqual(parsed_3.operands[0].register.name, "2")
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self.assertEqual(parsed_3.operands[0].register.prefix, "x")
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self.assertEqual(parsed_3.operands[1].immediate.value, "0x222")
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self.assertEqual(parsed_3.comment, "NOT IACA END")
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self.assertEqual(parsed_4.instruction, "str")
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self.assertIsNone(parsed_4.operands[1].memory.offset)
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self.assertEqual(parsed_4.operands[1].memory.base.name, "sp")
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self.assertEqual(parsed_4.operands[1].memory.base.prefix, "x")
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self.assertEqual(parsed_4.operands[1].memory.index.name, "1")
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self.assertEqual(parsed_4.operands[1].memory.index.prefix, "x")
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self.assertEqual(parsed_4.operands[1].memory.scale, 16)
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self.assertEqual(parsed_4.operands[0].register.name, "28")
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self.assertEqual(parsed_4.operands[0].register.prefix, "x")
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self.assertEqual(parsed_4.comment, "12.9")
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self.assertEqual(parsed_5.instruction, "ldr")
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self.assertEqual(parsed_5.operands[0].register.name, "0")
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self.assertEqual(parsed_5.operands[0].register.prefix, "x")
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self.assertEqual(parsed_5.operands[1].memory.offset.identifier.name, "q2c")
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self.assertEqual(parsed_5.operands[1].memory.offset.identifier.relocation, ":got_lo12:")
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self.assertEqual(parsed_5.operands[1].memory.base.name, "0")
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self.assertEqual(parsed_5.operands[1].memory.base.prefix, "x")
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self.assertIsNone(parsed_5.operands[1].memory.index)
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self.assertEqual(parsed_5.operands[1].memory.scale, 1)
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self.assertEqual(parsed_6.instruction, "adrp")
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self.assertEqual(parsed_6.operands[0].register.name, "0")
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self.assertEqual(parsed_6.operands[0].register.prefix, "x")
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self.assertEqual(parsed_6.operands[1].identifier.relocation, ":got:")
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self.assertEqual(parsed_6.operands[1].identifier.name, "visited")
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self.assertEqual(parsed_7.instruction, "fadd")
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self.assertEqual(parsed_7.operands[0].register.name, "17")
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self.assertEqual(parsed_7.operands[0].register.prefix, "v")
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self.assertEqual(parsed_7.operands[0].register.lanes, "2")
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self.assertEqual(parsed_7.operands[0].register.shape, "d")
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self.assertEqual(self.parser.get_full_reg_name(parsed_7.operands[2].register), "v1.2d")
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def test_parse_line(self):
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line_comment = "// -- Begin main"
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line_label = ".LBB0_1: // =>This Inner Loop Header: Depth=1"
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line_directive = ".cfi_def_cfa w29, -16"
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line_instruction = "ldr s0, [x11, w10, sxtw #2] // = <<2"
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line_prefetch = "prfm pldl1keep, [x26, #2048] //HPL"
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line_preindexed = "stp x29, x30, [sp, #-16]!"
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line_postindexed = "ldp q2, q3, [x11], #64"
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line_5_operands = "fcmla z26.d, p0/m, z29.d, z21.d, #90"
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instruction_form_1 = {
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"instruction": None,
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"operands": [],
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"directive": None,
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"comment": "-- Begin main",
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"label": None,
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"line": "// -- Begin main",
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"line_number": 1,
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}
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instruction_form_2 = {
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"instruction": None,
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"operands": [],
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"directive": None,
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"comment": "=>This Inner Loop Header: Depth=1",
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"label": ".LBB0_1",
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"line": ".LBB0_1: // =>This Inner Loop Header: Depth=1",
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"line_number": 2,
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}
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instruction_form_3 = {
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"instruction": None,
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"operands": [],
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"directive": {"name": "cfi_def_cfa", "parameters": ["w29", "-16"]},
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"comment": None,
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"label": None,
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"line": ".cfi_def_cfa w29, -16",
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"line_number": 3,
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}
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instruction_form_4 = {
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"instruction": "ldr",
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"operands": [
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{"register": {"prefix": "s", "name": "0"}},
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{
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"memory": {
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"offset": None,
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"base": {"prefix": "x", "name": "11"},
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"index": {
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"prefix": "w",
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"name": "10",
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"shift_op": "sxtw",
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"immediate": {"value": "2"},
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"shift": [{"value": "2"}],
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},
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"scale": 4,
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}
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},
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],
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"directive": None,
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"comment": "= <<2",
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"label": None,
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"line": "ldr s0, [x11, w10, sxtw #2] // = <<2",
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"line_number": 4,
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}
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instruction_form_5 = {
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"instruction": "prfm",
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"operands": [
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{"prfop": {"type": ["PLD"], "target": ["L1"], "policy": ["KEEP"]}},
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{
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"memory": {
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"offset": {"value": "2048"},
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"base": {"prefix": "x", "name": "26"},
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"index": None,
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"scale": 1,
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}
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},
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],
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"directive": None,
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"comment": "HPL",
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"label": None,
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"line": "prfm pldl1keep, [x26, #2048] //HPL",
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"line_number": 5,
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}
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instruction_form_6 = {
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"instruction": "stp",
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"operands": [
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{"register": {"prefix": "x", "name": "29"}},
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{"register": {"prefix": "x", "name": "30"}},
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{
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"memory": {
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"offset": {"value": "-16"},
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"base": {"name": "sp", "prefix": "x"},
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"index": None,
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"scale": 1,
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"pre_indexed": True,
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}
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},
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],
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"directive": None,
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"comment": None,
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"label": None,
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"line": "stp x29, x30, [sp, #-16]!",
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"line_number": 6,
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}
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instruction_form_7 = {
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"instruction": "ldp",
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"operands": [
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{"register": {"prefix": "q", "name": "2"}},
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{"register": {"prefix": "q", "name": "3"}},
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{
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"memory": {
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"offset": None,
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"base": {"prefix": "x", "name": "11"},
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"index": None,
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"scale": 1,
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"post_indexed": {"value": "64"},
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}
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},
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],
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"directive": None,
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"comment": None,
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"label": None,
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"line": "ldp q2, q3, [x11], #64",
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"line_number": 7,
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}
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instruction_form_8 = {
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"instruction": "fcmla",
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"operands": [
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{"register": {"prefix": "z", "name": "26", "shape": "d"}},
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{"register": {"prefix": "p", "name": "0", "predication": "m"}},
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{"register": {"prefix": "z", "name": "29", "shape": "d"}},
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{"register": {"prefix": "z", "name": "21", "shape": "d"}},
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{"immediate": {"value": "90", "type": "int"}},
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],
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"directive": None,
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"comment": None,
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"label": None,
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"line": "fcmla z26.d, p0/m, z29.d, z21.d, #90",
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"line_number": 8,
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}
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parsed_1 = self.parser.parse_line(line_comment, 1)
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parsed_2 = self.parser.parse_line(line_label, 2)
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parsed_3 = self.parser.parse_line(line_directive, 3)
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parsed_4 = self.parser.parse_line(line_instruction, 4)
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parsed_5 = self.parser.parse_line(line_prefetch, 5)
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parsed_6 = self.parser.parse_line(line_preindexed, 6)
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parsed_7 = self.parser.parse_line(line_postindexed, 7)
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parsed_8 = self.parser.parse_line(line_5_operands, 8)
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self.assertEqual(parsed_1, instruction_form_1)
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self.assertEqual(parsed_2, instruction_form_2)
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self.assertEqual(parsed_3, instruction_form_3)
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self.assertEqual(parsed_4, instruction_form_4)
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self.assertEqual(parsed_5, instruction_form_5)
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self.assertEqual(parsed_6, instruction_form_6)
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self.assertEqual(parsed_7, instruction_form_7)
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self.assertEqual(parsed_8, instruction_form_8)
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def test_parse_file(self):
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parsed = self.parser.parse_file(self.triad_code)
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self.assertEqual(parsed[0].line_number, 1)
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self.assertEqual(len(parsed), 645)
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def test_normalize_imd(self):
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imd_decimal_1 = {"value": "79"}
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imd_hex_1 = {"value": "0x4f"}
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imd_decimal_2 = {"value": "8"}
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imd_hex_2 = {"value": "0x8"}
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imd_float_11 = {"float": {"mantissa": "0.79", "e_sign": "+", "exponent": "2"}}
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imd_float_12 = {"float": {"mantissa": "790.0", "e_sign": "-", "exponent": "1"}}
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imd_double_11 = {"double": {"mantissa": "0.79", "e_sign": "+", "exponent": "2"}}
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imd_double_12 = {"double": {"mantissa": "790.0", "e_sign": "-", "exponent": "1"}}
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identifier = {"identifier": {"name": "..B1.4"}}
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value1 = self.parser.normalize_imd(imd_decimal_1)
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self.assertEqual(value1, self.parser.normalize_imd(imd_hex_1))
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self.assertEqual(
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self.parser.normalize_imd(imd_decimal_2), self.parser.normalize_imd(imd_hex_2)
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)
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self.assertEqual(self.parser.normalize_imd(imd_float_11), value1)
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self.assertEqual(self.parser.normalize_imd(imd_float_12), value1)
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self.assertEqual(self.parser.normalize_imd(imd_double_11), value1)
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self.assertEqual(self.parser.normalize_imd(imd_double_12), value1)
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self.assertEqual(self.parser.normalize_imd(identifier), identifier)
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def test_multiple_regs(self):
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instr_range = "PUSH {x5-x7}"
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reg_range = AttrDict(
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{
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"register": {
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"range": [{"prefix": "x", "name": "5"}, {"prefix": "x", "name": "7"}],
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"index": None,
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}
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}
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)
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instr_list = "POP {x5, x7, x9}"
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reg_list = AttrDict(
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{
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"register": {
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"list": [
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{"prefix": "x", "name": "5"},
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{"prefix": "x", "name": "7"},
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{"prefix": "x", "name": "9"},
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],
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"index": None,
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}
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}
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)
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prange = self.parser.parse_line(instr_range)
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plist = self.parser.parse_line(instr_list)
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self.assertEqual(prange.operands[0], reg_range)
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self.assertEqual(plist.operands[0], reg_list)
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def test_reg_dependency(self):
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reg_1_1 = AttrDict({"prefix": "b", "name": "1"})
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reg_1_2 = AttrDict({"prefix": "h", "name": "1"})
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reg_1_3 = AttrDict({"prefix": "s", "name": "1"})
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reg_1_4 = AttrDict({"prefix": "d", "name": "1"})
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reg_1_4 = AttrDict({"prefix": "q", "name": "1"})
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reg_2_1 = AttrDict({"prefix": "w", "name": "2"})
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reg_2_2 = AttrDict({"prefix": "x", "name": "2"})
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reg_v1_1 = AttrDict({"prefix": "v", "name": "11", "lanes": "16", "shape": "b"})
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reg_v1_2 = AttrDict({"prefix": "v", "name": "11", "lanes": "8", "shape": "h"})
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reg_v1_3 = AttrDict({"prefix": "v", "name": "11", "lanes": "4", "shape": "s"})
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reg_v1_4 = AttrDict({"prefix": "v", "name": "11", "lanes": "2", "shape": "d"})
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reg_b5 = AttrDict({"prefix": "b", "name": "5"})
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reg_q15 = AttrDict({"prefix": "q", "name": "15"})
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reg_v10 = AttrDict({"prefix": "v", "name": "10", "lanes": "2", "shape": "s"})
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reg_v20 = AttrDict({"prefix": "v", "name": "20", "lanes": "2", "shape": "d"})
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reg_1 = [reg_1_1, reg_1_2, reg_1_3, reg_1_4]
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reg_2 = [reg_2_1, reg_2_2]
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reg_v = [reg_v1_1, reg_v1_2, reg_v1_3, reg_v1_4]
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reg_others = [reg_b5, reg_q15, reg_v10, reg_v20]
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regs = reg_1 + reg_2 + reg_v + reg_others
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# test each register against each other
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for ri in reg_1:
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for rj in regs:
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assert_value = True if rj in reg_1 else False
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with self.subTest(reg_a=ri, reg_b=rj, assert_val=assert_value):
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self.assertEqual(self.parser.is_reg_dependend_of(ri, rj), assert_value)
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for ri in reg_2:
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for rj in regs:
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assert_value = True if rj in reg_2 else False
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with self.subTest(reg_a=ri, reg_b=rj, assert_val=assert_value):
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self.assertEqual(self.parser.is_reg_dependend_of(ri, rj), assert_value)
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for ri in reg_v:
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for rj in regs:
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assert_value = True if rj in reg_v else False
|
|
with self.subTest(reg_a=ri, reg_b=rj, assert_val=assert_value):
|
|
self.assertEqual(self.parser.is_reg_dependend_of(ri, rj), assert_value)
|
|
for ri in reg_others:
|
|
for rj in regs:
|
|
assert_value = True if rj == ri else False
|
|
with self.subTest(reg_a=ri, reg_b=rj, assert_val=assert_value):
|
|
self.assertEqual(self.parser.is_reg_dependend_of(ri, rj), assert_value)
|
|
|
|
##################
|
|
# Helper functions
|
|
##################
|
|
def _get_comment(self, parser, comment):
|
|
return " ".join(
|
|
AttrDict.convert_dict(
|
|
parser.process_operand(parser.comment.parseString(comment, parseAll=True).asDict())
|
|
).comment
|
|
)
|
|
|
|
def _get_label(self, parser, label):
|
|
return AttrDict.convert_dict(
|
|
parser.process_operand(parser.label.parseString(label, parseAll=True).asDict())
|
|
).label
|
|
|
|
def _get_directive(self, parser, directive):
|
|
return AttrDict.convert_dict(
|
|
parser.process_operand(parser.directive.parseString(directive, parseAll=True).asDict())
|
|
).directive
|
|
|
|
@staticmethod
|
|
def _find_file(name):
|
|
testdir = os.path.dirname(__file__)
|
|
name = os.path.join(testdir, "test_files", name)
|
|
assert os.path.exists(name)
|
|
return name
|
|
|
|
|
|
if __name__ == "__main__":
|
|
suite = unittest.TestLoader().loadTestsFromTestCase(TestParserAArch64)
|
|
unittest.TextTestRunner(verbosity=2).run(suite)
|