mirror of
https://github.com/RRZE-HPC/OSACA.git
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473 lines
23 KiB
Python
473 lines
23 KiB
Python
#!/usr/bin/env python3
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"""Semantics opbject responsible for architecture specific semantic operations"""
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from dis import Instruction
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import sys
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import warnings
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from itertools import chain
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from operator import itemgetter
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from copy import deepcopy
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from .hw_model import MachineModel
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from .isa_semantics import INSTR_FLAGS, ISASemantics
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from osaca.parser.memory import MemoryOperand
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from osaca.parser.register import RegisterOperand
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class ArchSemantics(ISASemantics):
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def __init__(self, parser, machine_model: MachineModel, path_to_yaml=None):
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super().__init__(parser, path_to_yaml=path_to_yaml)
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self._machine_model = machine_model
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def normalize_instruction_form(self, instruction_form):
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self.parser.normalize_instruction_form(
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instruction_form,
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self.isa_model,
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self._machine_model
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)
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def normalize_instruction_forms(self, instruction_forms):
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for instruction_form in instruction_forms:
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self.normalize_instruction_form(instruction_form)
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def _check_normalized(self, instruction_forms):
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for instruction_form in instruction_forms:
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instruction_form.check_normalized()
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# SUMMARY FUNCTION
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def add_semantics(self, kernel):
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"""
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Applies performance data (throughput, latency, port pressure) and source/destination
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distribution to each instruction of a given kernel.
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:param list kernel: kernel to apply semantics
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"""
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self._check_normalized(kernel)
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for instruction_form in kernel:
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self.assign_src_dst(instruction_form)
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self.assign_tp_lt(instruction_form)
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if self._machine_model.has_hidden_loads():
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self.set_hidden_loads(kernel)
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def assign_optimal_throughput(self, kernel, start=0):
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"""
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Assign optimal throughput port pressure to a kernel. This is done in steps of ``0.01cy``.
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:param list kernel: kernel to apply optimal port utilization
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"""
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self._check_normalized(kernel)
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INC = 0.01
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kernel.reverse()
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port_list = self._machine_model.get_ports()
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multiple_assignments = False
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for idx, instruction_form in enumerate(kernel[start:], start):
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multiple_assignments = False
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# if iform has multiple possible port assignments, check all in a DFS manner and take the best
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if isinstance(instruction_form.port_uops, dict):
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best_kernel = None
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best_kernel_tp = sys.maxsize
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for port_util_alt in list(instruction_form.port_uops.values())[1:]:
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k_tmp = deepcopy(kernel)
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k_tmp[idx].port_uops = deepcopy(port_util_alt)
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k_tmp[idx].port_pressure = self._machine_model.average_port_pressure(
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k_tmp[idx].port_uops
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)
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k_tmp.reverse()
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self.assign_optimal_throughput(k_tmp, idx)
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if max(self.get_throughput_sum(k_tmp)) < best_kernel_tp:
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best_kernel = k_tmp
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best_kernel_tp = max(self.get_throughput_sum(best_kernel))
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# check the first option in the main branch and compare against the best option later
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multiple_assignments = True
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kernel[idx].port_uops = list(instruction_form.port_uops.values())[0]
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for uop in instruction_form.port_uops:
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cycles = uop[0]
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ports = list(uop[1])
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indices = [port_list.index(p) for p in ports]
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# check if port sum of used ports for uop are unbalanced
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port_sums = self._to_list(itemgetter(*indices)(self.get_throughput_sum(kernel)))
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instr_ports = self._to_list(itemgetter(*indices)(instruction_form.port_pressure))
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if len(set(port_sums)) > 1:
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# balance ports
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# init list for keeping track of the current change
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differences = [cycles / len(ports) for p in ports]
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for _ in range(int(cycles * (1 / INC))):
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if len(instr_ports) == 1:
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# no balancing possible anymore
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break
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max_port_idx = port_sums.index(max(port_sums))
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min_port_idx = port_sums.index(min(port_sums))
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instr_ports[max_port_idx] -= INC
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instr_ports[min_port_idx] += INC
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differences[max_port_idx] -= INC
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differences[min_port_idx] += INC
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# instr_ports = [round(p, 2) for p in instr_ports]
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self._itemsetter(*indices)(instruction_form.port_pressure, *instr_ports)
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# check if min port is zero
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if round(min(instr_ports), 2) <= 0:
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# if port_pressure is not exactly 0.00, add the residual to
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# the former port
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if min(instr_ports) != 0.0:
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min_port_idx = port_sums.index(min(port_sums))
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instr_ports[min_port_idx] += min(instr_ports)
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differences[min_port_idx] += min(instr_ports)
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# we don't need to decrease difference for other port, just
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# delete it
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del differences[instr_ports.index(min(instr_ports))]
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self._itemsetter(*indices)(
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instruction_form.port_pressure, *instr_ports
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)
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zero_index = [
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p
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for p in indices
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if round(instruction_form.port_pressure[p], 2) == 0
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or instruction_form.port_pressure[p] < 0.00
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][0]
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instruction_form.port_pressure[zero_index] = 0.0
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# Remove from further balancing
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indices = [p for p in indices if instruction_form.port_pressure[p] > 0]
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instr_ports = self._to_list(
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itemgetter(*indices)(instruction_form.port_pressure)
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)
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# never remove more than the fixed utilization per uop and port, i.e.,
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# cycles/len(ports)
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if round(min(differences), 2) <= 0:
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# don't worry if port_pressure isn't exactly 0 and just
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# remove from further balancing by deleting index since
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# pressure is not 0
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del indices[differences.index(min(differences))]
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instr_ports = self._to_list(
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itemgetter(*indices)(instruction_form.port_pressure)
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)
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del differences[differences.index(min(differences))]
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port_sums = self._to_list(
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itemgetter(*indices)(self.get_throughput_sum(kernel))
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)
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kernel.reverse()
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if multiple_assignments:
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if max(self.get_throughput_sum(kernel)) > best_kernel_tp:
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for i, instr in enumerate(best_kernel):
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kernel[i].port_uops = best_kernel[i].port_uops
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kernel[i].port_pressure = best_kernel[i].port_pressure
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def set_hidden_loads(self, kernel):
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"""Hide loads behind stores if architecture supports hidden loads (depricated)"""
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self._check_normalized(kernel)
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loads = [instr for instr in kernel if INSTR_FLAGS.HAS_LD in instr.flags]
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stores = [instr for instr in kernel if INSTR_FLAGS.HAS_ST in instr.flags]
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# Filter instructions including load and store
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load_ids = [instr.line_number for instr in loads]
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store_ids = [instr.line_number for instr in stores]
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shared_ldst = list(set(load_ids).intersection(set(store_ids)))
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loads = [instr for instr in loads if instr.line_number not in shared_ldst]
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stores = [instr for instr in stores if instr.line_number not in shared_ldst]
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if len(stores) == 0 or len(loads) == 0:
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# nothing to do
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return
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if len(loads) <= len(stores):
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# Hide all loads
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for load in loads:
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load.flags += [INSTR_FLAGS.HIDDEN_LD]
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load.port_pressure = self._nullify_data_ports(load.port_pressure)
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else:
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for store in stores:
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# Get 'closest' load instruction
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min_distance_load = min(
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[
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(
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abs(load_instr.line_number - store.line_number),
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load_instr.line_number,
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)
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for load_instr in loads
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if INSTR_FLAGS.HIDDEN_LD not in load_instr.flags
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]
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)
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load = [instr for instr in kernel if instr.line_number == min_distance_load[1]][0]
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# Hide load
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load.flags += [INSTR_FLAGS.HIDDEN_LD]
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load.port_pressure = self._nullify_data_ports(load.port_pressure)
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# get parser result and assign throughput and latency value to instruction form
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# mark instruction form with semantic flags
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def assign_tp_lt(self, instruction_form):
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"""Assign throughput and latency to an instruction form."""
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instruction_form.check_normalized()
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flags = []
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port_number = len(self._machine_model["ports"])
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if instruction_form.mnemonic is None:
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# No instruction (label, comment, ...) --> ignore
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throughput = 0.0
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latency = 0.0
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latency_wo_load = latency
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instruction_form.port_pressure = [0.0 for i in range(port_number)]
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instruction_form.port_uops = []
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else:
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instruction_data = self._machine_model.get_instruction(
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instruction_form.mnemonic, instruction_form.operands
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)
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if instruction_data:
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# instruction form in DB
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(
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throughput,
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port_pressure,
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latency,
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latency_wo_load,
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) = self._handle_instruction_found(
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instruction_data, port_number, instruction_form, flags
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)
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else:
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# instruction could not be found in DB
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assign_unknown = True
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# check for equivalent register-operands DB entry if LD
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if (
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INSTR_FLAGS.HAS_LD in instruction_form.flags
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or INSTR_FLAGS.HAS_ST in instruction_form.flags
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):
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# dynamically combine LD/ST and reg form of instruction form
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# substitute mem and look for reg-only variant
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operands = self.substitute_mem_address(instruction_form.operands)
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instruction_data_reg = self._machine_model.get_instruction(
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instruction_form.mnemonic, operands
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)
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if instruction_data_reg:
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assign_unknown = False
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reg_type = self._parser.get_reg_type(
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instruction_data_reg.operands[
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operands.index(self._create_reg_wildcard())
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]
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)
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# dummy_reg = {"class": "register", "name": reg_type}
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dummy_reg = RegisterOperand(name=reg_type)
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data_port_pressure = [0.0 for _ in range(port_number)]
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data_port_uops = []
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if INSTR_FLAGS.HAS_LD in instruction_form.flags:
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# LOAD performance data
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load_perf_data = self._machine_model.get_load_throughput(
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[
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x
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for x in instruction_form.semantic_operands["source"]
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+ instruction_form.semantic_operands["src_dst"]
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if isinstance(x, MemoryOperand)
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][0]
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)
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# if multiple options, choose based on reg type
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data_port_uops = [
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ldp[1]
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for ldp in load_perf_data
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if ldp[0].dst is not None
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and self._machine_model._check_operands(
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dummy_reg, RegisterOperand(name=ldp[0].dst)
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)
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]
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if len(data_port_uops) < 1:
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data_port_uops = load_perf_data[0][1]
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else:
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data_port_uops = data_port_uops[0]
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data_port_pressure = self._machine_model.average_port_pressure(
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data_port_uops
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)
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if "load_throughput_multiplier" in self._machine_model:
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multiplier = self._machine_model["load_throughput_multiplier"][
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reg_type
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]
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data_port_pressure = [pp * multiplier for pp in data_port_pressure]
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if INSTR_FLAGS.HAS_ST in instruction_form.flags:
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# STORE performance data
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destinations = (
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instruction_form.semantic_operands["destination"]
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+ instruction_form.semantic_operands["src_dst"]
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)
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store_perf_data = self._machine_model.get_store_throughput(
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[x for x in destinations if isinstance(x, MemoryOperand)][0],
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dummy_reg,
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)
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st_data_port_uops = store_perf_data[0][1]
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# zero data port pressure and remove HAS_ST flag if
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# - no mem operand in dst &&
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# - all mem operands in src_dst are pre-/post_indexed
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# since it is no mem store
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if (
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self._parser.isa() == "aarch64"
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and not isinstance(
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instruction_form.semantic_operands["destination"],
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MemoryOperand,
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)
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and all(
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[
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op.post_indexed or op.pre_indexed
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for op in instruction_form.semantic_operands["src_dst"]
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if isinstance(op, MemoryOperand)
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]
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)
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):
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st_data_port_uops = []
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instruction_form.flags.remove(INSTR_FLAGS.HAS_ST)
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# sum up all data ports in case for LOAD and STORE
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st_data_port_pressure = self._machine_model.average_port_pressure(
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st_data_port_uops
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)
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if "store_throughput_multiplier" in self._machine_model:
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multiplier = self._machine_model["store_throughput_multiplier"][
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reg_type
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]
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st_data_port_pressure = [
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pp * multiplier for pp in st_data_port_pressure
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]
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data_port_pressure = [
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sum(x) for x in zip(data_port_pressure, st_data_port_pressure)
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]
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data_port_uops += st_data_port_uops
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throughput = max(max(data_port_pressure), instruction_data_reg.throughput)
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latency = instruction_data_reg.latency
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# Add LD and ST latency
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latency += (
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self._machine_model.get_load_latency(reg_type)
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if INSTR_FLAGS.HAS_LD in instruction_form.flags
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else 0
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)
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latency += (
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self._machine_model.get_store_latency(reg_type)
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if INSTR_FLAGS.HAS_ST in instruction_form.flags
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else 0
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)
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latency_wo_load = instruction_data_reg.latency
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# add latency of ADD if post- or pre_indexed load
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# TODO more investigation: check dot-graph, wrong latency distribution!
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# if (
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# latency_wo_load == 0
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# and self._isa == 'aarch64'
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# and any(
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# [
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# 'post_indexed' in op['memory'] or
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# 'pre_indexed' in op['memory']
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# for op in instruction_form.operands
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# if 'memory' in op
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# ]
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# )
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# ):
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# latency_wo_load = 1.0
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instruction_form.port_pressure = [
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sum(x)
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for x in zip(
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data_port_pressure,
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self._machine_model.average_port_pressure(
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instruction_data_reg.port_pressure
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),
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)
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]
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instruction_form.port_uops = list(
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chain(instruction_data_reg.port_pressure, data_port_uops)
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)
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if assign_unknown:
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# --> mark as unknown and assume 0 cy for latency/throughput
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throughput = 0.0
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latency = 0.0
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latency_wo_load = latency
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instruction_form.port_pressure = [0.0 for i in range(port_number)]
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# instruction_formport_uops = []
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flags += [INSTR_FLAGS.TP_UNKWN, INSTR_FLAGS.LT_UNKWN]
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# flatten flag list
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flags = list(set(flags))
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if instruction_form.flags == []:
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instruction_form.flags = flags
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else:
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instruction_form.flags += flags
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instruction_form.throughput = throughput
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instruction_form.latency = latency
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instruction_form.latency_wo_load = latency_wo_load
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# for later CP and loop-carried dependency analysis
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instruction_form.latency_cp = 0
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instruction_form.latency_lcd = 0
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def _handle_instruction_found(self, instruction_data, port_number, instruction_form, flags):
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"""Apply performance data to instruction if it was found in the archDB"""
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instruction_form.check_normalized()
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throughput = instruction_data.throughput
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port_pressure = self._machine_model.average_port_pressure(instruction_data.port_pressure)
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instruction_form.port_uops = instruction_data.port_pressure
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try:
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assert isinstance(port_pressure, list)
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assert len(port_pressure) == port_number
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instruction_form.port_pressure = port_pressure
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if sum(port_pressure) == 0 and throughput is not None:
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# port pressure on all ports 0 --> not bound to a port
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flags.append(INSTR_FLAGS.NOT_BOUND)
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except AssertionError:
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warnings.warn(
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"Port pressure could not be imported correctly from database. "
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+ "Please check entry for:\n {}".format(instruction_form)
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)
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instruction_form.port_pressure = [0.0 for i in range(port_number)]
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instruction_form.port_uops = []
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flags.append(INSTR_FLAGS.TP_UNKWN)
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if throughput is None:
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# assume 0 cy and mark as unknown
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throughput = 0.0
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flags.append(INSTR_FLAGS.TP_UNKWN)
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latency = instruction_data.latency
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latency_wo_load = latency
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if latency is None:
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# assume 0 cy and mark as unknown
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latency = 0.0
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latency_wo_load = latency
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flags.append(INSTR_FLAGS.LT_UNKWN)
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if INSTR_FLAGS.HAS_LD in instruction_form.flags:
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flags.append(INSTR_FLAGS.LD)
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return throughput, port_pressure, latency, latency_wo_load
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def convert_op_to_reg(self, reg_type, regtype="0"):
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"""Create register operand for a memory addressing operand"""
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if self._parser.isa() == "x86":
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if reg_type == "gpr":
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register = RegisterOperand(name="r" + str(int(regtype) + 9))
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else:
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register = RegisterOperand(name=reg_type + regtype)
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elif self._parser.isa() == "aarch64":
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register = RegisterOperand(name=regtype, prefix=reg_type)
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return register
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def _nullify_data_ports(self, port_pressure):
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"""Set all ports to 0.0 for the ports of a machine model"""
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data_ports = self._machine_model.get_data_ports()
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for port in data_ports:
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index = self._machine_model.get_ports().index(port)
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port_pressure[index] = 0.0
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return port_pressure
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def _itemsetter(self, *items):
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if len(items) == 1:
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item = items[0]
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def g(obj, value):
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obj[item] = value
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else:
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def g(obj, *values):
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for item, value in zip(items, values):
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obj[item] = value
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return g
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def _to_list(self, obj):
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if isinstance(obj, tuple):
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return list(obj)
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else:
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return [obj]
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@staticmethod
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def get_throughput_sum(kernel):
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"""Get the overall throughput sum separated by port of all instructions of a kernel."""
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# ignoring all lines with throughput == 0.0, because there won't be anything to sum up
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# typically comment, label and non-instruction lines
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port_pressures = [instr.port_pressure for instr in kernel if instr.throughput != 0.0]
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# Essentially summing up each columns of port_pressures, where each column is one port
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# and each row is one line of the kernel
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# round is necessary to ensure termination of ArchsSemantics.assign_optimal_throughput
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tp_sum = [round(sum(col), 2) for col in zip(*port_pressures)]
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return tp_sum
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