mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2025-12-16 00:50:06 +01:00
1ceac6e9f3
- Enhanced RISC-V parser to support reloc_type and symbol in ImmediateOperand. - Added missing attributes (reloc_type, symbol) to ImmediateOperand and updated __eq__ for backward compatibility. - Fixed all flake8 (E501, E265, F401, F841) and Black formatting issues across the codebase. - Improved docstrings and split long lines for better readability. - Fixed test failures related to ImmediateOperand instantiation and attribute errors. - Ensured all tests pass, including edge cases for RISC-V, x86, and AArch64. - Updated .gitignore and documentation as needed. - Renamed example files for consistency (rv6 -> rv64).
344 lines
11 KiB
Python
344 lines
11 KiB
Python
#!/usr/bin/env python3
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import argparse
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import json
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import math
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import re
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import sys
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from asmbench import bench, op
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from osaca.semantics import MachineModel
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def build_bench_instruction(name, operands):
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# Converts an OSACA model instruction to an asmbench one.
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# Returns `None` in case something went wrong.
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asmbench_inst = name
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direction = "dst"
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separator = " "
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shift = ""
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for operand in operands:
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if operand["class"] == "register" or operand["class"] == "register_shift":
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if operand["prefix"] == "x":
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shape = "i64"
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constraint = "r"
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elif operand["prefix"] == "s":
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shape = "float"
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constraint = "w"
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elif operand["prefix"] == "d":
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shape = "double"
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constraint = "w"
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elif operand["prefix"] == "v":
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constraint = "w"
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if operand["shape"] == "b":
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shape = "<16 x i8>"
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elif operand["shape"] == "h":
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shape = "<8 x i16>"
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elif operand["shape"] == "s":
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shape = "<4 x float>"
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elif operand["shape"] == "d":
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shape = "<2 x double>"
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else:
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return None
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else:
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return None
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if operand["class"] == "register_shift":
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shift = ", {}".format(operand["shift_op"])
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if operand["shift"] is not None:
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shift += " {}".format(operand["shift"])
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elif operand["class"] == "immediate" or operand["class"] == "immediate_shift":
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shape = "i32"
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# Different instructions have different ranges for literaly,
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# so need to pick something "reasonable" for each.
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if name in [
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"cmeq",
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"cmge",
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"cmgt",
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"cmle",
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"cmlt",
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"fcmeq",
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"fcmge",
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"fcmgt",
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"fcmle",
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"fcmlt",
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"fcmp",
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]:
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constraint = "0"
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elif name in ["and", "ands", "eor", "eors", "orr", "orrs"]:
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constraint = "255"
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elif name in [
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"bfi",
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"extr",
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"sbfiz",
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"sbfx",
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"shl",
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"sshr",
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"ubfiz",
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"ubfx",
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"ushr",
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]:
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constraint = "7"
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else:
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constraint = "42"
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if operand["class"] == "immediate_shift":
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shift = ", {}".format(operand["shift_op"])
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if operand["shift"] is not None:
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shift += " {}".format(operand["shift"])
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else:
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return None
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asmbench_inst += "{}{{{}:{}:{}}}{}".format(
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separator, direction, shape, constraint, shift
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)
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direction = "src"
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separator = ", "
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return asmbench_inst
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def bench_instruction(name, operands):
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# Converts an OSACA model instruction to an asmbench one and benchmarks it.
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# Returned tuple may contain a `None` in case something went wrong.
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asmbench_inst = build_bench_instruction(name, operands)
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if asmbench_inst is None:
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return (None, None)
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return bench.bench_instructions([op.Instruction.from_string(asmbench_inst)])
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def round_cycles(value):
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if value < 0.9:
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# Frequently found, so we might want to include them.
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# Measurements over-estimate a lot here, hence the high bound.
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return 0.5
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else:
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# Measurements usually over-estimate, so usually round down,
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# but still allow slightly smaller values.
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return float(math.floor(value + 0.1))
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def operand_parse(op, state):
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# Parses an operand from an PMEvo instruction and emits an OSACA model one.
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# State object is used to keep track of types for future operands, e.g. literals.
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# Future invocations may also modify previously returned objects.
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parameter = {}
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if op.startswith("_((REG:"):
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parts = op.split(".")
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register = parts[0][7:-2]
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read_write, register_type, bits = register.split(":")
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parameter["class"] = "register"
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if register_type == "G":
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if bits == "32":
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parameter["prefix"] = "r"
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elif bits == "64":
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parameter["prefix"] = "x"
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else:
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raise ValueError(
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"Invalid register bits for {} {}".format(register_type, bits)
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)
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elif register_type == "F":
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if bits == "32":
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parameter["prefix"] = "s"
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state["type"] = "float"
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elif bits == "64":
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parameter["prefix"] = "d"
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state["type"] = "double"
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elif bits == "128":
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parameter["prefix"] = "q"
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elif bits == "VEC":
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vec_shape = parts[1]
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parameter["prefix"] = "v"
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if vec_shape == "16b":
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parameter["shape"] = "b"
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elif vec_shape == "8h":
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parameter["shape"] = "h"
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elif vec_shape == "4s":
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parameter["shape"] = "s"
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state["type"] = "float"
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elif vec_shape == "2d":
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parameter["shape"] = "d"
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state["type"] = "double"
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else:
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raise ValueError("Invalid vector shape {}".format(vec_shape))
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else:
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raise ValueError(
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"Invalid register bits for {} {}".format(register_type, bits)
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)
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else:
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raise ValueError("Unknown register type {}".format(register_type))
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elif op.startswith("_[((MEM:"):
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bits = op[8:-2].split(":")[0]
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if bits == "64":
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state["memory_base"] = "x"
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else:
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raise ValueError("Invalid register bits for MEM {}".format(bits))
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return None
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elif op.startswith("_((MIMM:"):
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bits = op[8:-3].split(":")[0]
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if bits == "16":
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parameter["class"] = "memory"
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parameter["base"] = state["memory_base"]
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parameter["offset"] = "imd"
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parameter["index"] = "*"
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parameter["scale"] = "*"
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parameter["post-indexed"] = False
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parameter["pre-indexed"] = False
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else:
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raise ValueError("Invalid register bits for MEM {}".format(bits))
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elif re.fullmatch("_#?-?(0x)?[0-9a-f]+", op):
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parameter["class"] = "immediate"
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parameter["imd"] = "int"
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elif re.fullmatch("_#?-?[0-9]*\\.[0-9]*", op):
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parameter["class"] = "immediate"
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parameter["imd"] = state["type"]
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elif re.fullmatch("_((sxt|uxt)[bhw]|lsl|lsr|asr|rol|ror)(_[0-9]+)?", op):
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# split = op[1:].split('_')
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# shift_op = split[0]
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# shift = None
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# if len(split) >= 2:
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# shift = split[1]
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# state['previous']['class'] += '_shift'
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# state['previous']['shift_op'] = shift_op
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# if shift != None:
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# state['previous']['shift'] = shift
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# return None
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raise ValueError("Skipping instruction with shift operand: {}".format(op))
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else:
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raise ValueError("Unknown operand {}".format(op))
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state["previous"] = parameter
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return parameter
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def port_convert(ports):
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# Try to merge repeated entries together and emit in OSACA's format.
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# FIXME: This does not handle having more than 10 ports.
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pressures = []
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previous = None
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cycles = 0
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for entry in ports:
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possible_ports = "".join(entry)
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if possible_ports != previous:
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if previous is not None:
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pressures.append([cycles, previous])
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previous = possible_ports
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cycles = 0
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cycles += 1
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if previous is not None:
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pressures.append([cycles, previous])
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return pressures
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def throughput_guess(ports):
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# Minimum amount of possible ports per cycle should determine throughput
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# to some degree of accuracy. (THIS IS *NOT* ALWAYS TRUE!)
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bottleneck_ports = min(map(lambda it: len(it), ports))
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return float(len(ports)) / bottleneck_ports
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def latency_guess(ports):
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# Each entry in the ports array equates to one cycle on any of the ports.
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# So this is about as good as it is going to get.
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return float(len(ports))
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def extract_model(mapping, arch, template_model, asmbench):
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try:
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isa = MachineModel.get_isa_for_arch(arch)
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except ValueError:
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print("Skipping...", file=sys.stderr)
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return None
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if template_model is None:
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mm = MachineModel(isa=isa)
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else:
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mm = template_model
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for port in mapping["arch"]["ports"]:
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mm.add_port(port)
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for insn in mapping["arch"]["insns"]:
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try:
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ports = mapping["assignment"][insn]
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# Parse instruction
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insn_split = insn.split("_")
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name = insn_split[1]
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insn_parts = list(("_" + "_".join(insn_split[2:])).split(","))
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operands = []
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state = {}
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for operand in insn_parts:
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parsed = operand_parse(operand, state)
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if parsed is not None:
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operands.append(parsed)
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# Port pressures from mapping
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port_pressure = port_convert(ports)
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# Initial guessed throughput and latency
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throughput = throughput_guess(ports)
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latency = latency_guess(ports)
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# Benchmark with asmbench
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# print(build_bench_instruction(name, operands))
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if asmbench:
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bench_latency, bench_throughput = bench_instruction(name, operands)
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if bench_throughput is not None:
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throughput = round_cycles(bench_throughput)
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else:
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print(
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"Failed to measure throughput for instruction {}.".format(insn)
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)
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if bench_latency is not None:
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latency = round_cycles(bench_latency)
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else:
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print("Failed to measure latency for instruction {}.".format(insn))
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# No u-ops data available
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uops = None
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# Insert instruction if not already found (can happen with template)
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if mm.get_instruction(name, operands) is None:
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mm.set_instruction(
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name, operands, latency, port_pressure, throughput, uops
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)
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except ValueError as e:
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print("Failed to parse instruction {}: {}.".format(insn, e))
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return mm
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def main():
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parser = argparse.ArgumentParser()
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parser.add_argument("json", help="path of mapping.json")
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parser.add_argument("yaml", help="path of template.yml", nargs="?")
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parser.add_argument(
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"--asmbench",
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help="Benchmark latency and throughput using asmbench.",
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action="store_true",
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)
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args = parser.parse_args()
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json_file = open(args.json, "r")
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mapping = json.load(json_file)
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arch = mapping["arch"]["name"].lower()
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json_file.close()
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template_model = None
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if args.yaml is not None:
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template_model = MachineModel(path_to_yaml=args.yaml)
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if args.asmbench:
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bench.setup_llvm()
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model = extract_model(mapping, arch, template_model, args.asmbench)
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with open("{}.yml".format(arch.lower()), "w") as f:
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f.write(model.dump())
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if __name__ == "__main__":
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main()
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