mirror of
https://github.com/RRZE-HPC/OSACA.git
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1ceac6e9f3
- Enhanced RISC-V parser to support reloc_type and symbol in ImmediateOperand. - Added missing attributes (reloc_type, symbol) to ImmediateOperand and updated __eq__ for backward compatibility. - Fixed all flake8 (E501, E265, F401, F841) and Black formatting issues across the codebase. - Improved docstrings and split long lines for better readability. - Fixed test failures related to ImmediateOperand instantiation and attribute errors. - Ensured all tests pass, including edge cases for RISC-V, x86, and AArch64. - Updated .gitignore and documentation as needed. - Renamed example files for consistency (rv6 -> rv64).
752 lines
14 KiB
YAML
752 lines
14 KiB
YAML
---
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osaca_version: 0.7.0
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micro_architecture: rv64
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arch_code: rv64
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isa: riscv
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# RV64 core parameters
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ROB_size: 96
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retired_uOps_per_cycle: 3
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scheduler_size: 84
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hidden_loads: false
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# Pipeline ports (simplified model)
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ports:
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- ALU
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- MEM
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- DIV
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- FP
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port_model_scheme: |
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ALU: Integer arithmetic and logic operations
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MEM: Load/store and address generation
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DIV: Integer division operations
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FP: Floating-point operations and vector instructions
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# Load latency in cycles by register type
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load_latency:
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gpr: 3
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fpr: 3
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vr: 4
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# Simplified load throughput model
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load_throughput_default: [[1, ["MEM"]]]
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store_throughput_default: [[1, ["MEM"]]]
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store_to_load_forward_latency: 4
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# Instruction forms - listed by category
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instruction_forms:
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# Basic integer arithmetic (latency 1, throughput 1)
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- name: ADD
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: ADDI
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: SUB
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: LUI
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operands:
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- class: register
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prefix: x
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- class: immediate
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imd: int
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: AUIPC
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operands:
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- class: register
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prefix: x
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- class: immediate
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imd: int
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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# Logical operations
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- name: AND
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: ANDI
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: OR
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: ORI
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: XOR
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: XORI
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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# Shifts
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- name: SLL
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: SLLI
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: SRL
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: SRLI
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: SRA
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: SRAI
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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# Multiplication
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- name: MUL
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 3
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: MULH
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 3
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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# Division (higher latency)
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- name: DIV
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 10
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throughput: 10
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port_pressure: [[1, ["DIV"]]]
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- name: DIVU
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 10
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throughput: 10
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port_pressure: [[1, ["DIV"]]]
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- name: REM
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 10
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throughput: 10
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port_pressure: [[1, ["DIV"]]]
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- name: REMU
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: register
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prefix: x
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latency: 10
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throughput: 10
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port_pressure: [[1, ["DIV"]]]
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# Memory operations
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- name: LW
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operands:
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- class: register
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prefix: x
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- class: memory
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base: x
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offset: imd
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index: null
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scale: 1
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latency: 3
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throughput: 1
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port_pressure: [[1, ["MEM"]]]
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- name: LD
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operands:
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- class: register
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prefix: x
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- class: memory
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base: x
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offset: imd
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index: null
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scale: 1
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latency: 3
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throughput: 1
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port_pressure: [[1, ["MEM"]]]
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- name: SW
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operands:
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- class: register
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prefix: x
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- class: memory
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base: x
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offset: imd
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index: null
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scale: 1
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latency: 1
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throughput: 1
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port_pressure: [[1, ["MEM"]]]
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- name: SD
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operands:
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- class: register
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prefix: x
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- class: memory
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base: x
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offset: imd
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index: null
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scale: 1
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latency: 1
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throughput: 1
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port_pressure: [[1, ["MEM"]]]
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# Control flow
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- name: BEQ
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: identifier
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: BNE
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: identifier
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: BLT
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: identifier
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: BGE
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: identifier
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: JAL
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operands:
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- class: register
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prefix: x
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- class: identifier
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: JALR
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: immediate
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imd: int
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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# Floating point operations
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- name: FLW
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operands:
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- class: register
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prefix: f
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- class: memory
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base: x
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offset: imd
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index: null
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scale: 1
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latency: 3
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throughput: 1
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port_pressure: [[1, ["MEM"]]]
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- name: FLD
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operands:
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- class: register
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prefix: f
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- class: memory
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base: x
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offset: imd
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index: null
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scale: 1
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latency: 3
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throughput: 1
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port_pressure: [[1, ["MEM"]]]
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- name: FSW
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operands:
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- class: register
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prefix: f
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- class: memory
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base: x
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offset: imd
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index: null
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scale: 1
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latency: 1
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throughput: 1
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port_pressure: [[1, ["MEM"]]]
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- name: FSD
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operands:
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- class: register
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prefix: f
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- class: memory
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base: x
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offset: imd
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index: null
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scale: 1
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latency: 1
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throughput: 1
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port_pressure: [[1, ["MEM"]]]
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- name: FADD.S
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operands:
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- class: register
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prefix: f
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- class: register
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prefix: f
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- class: register
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prefix: f
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latency: 3
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throughput: 1
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port_pressure: [[1, ["FP"]]]
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- name: FADD.D
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operands:
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- class: register
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prefix: f
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- class: register
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prefix: f
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- class: register
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prefix: f
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latency: 3
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throughput: 1
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port_pressure: [[1, ["FP"]]]
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- name: FSUB.S
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operands:
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- class: register
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prefix: f
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- class: register
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prefix: f
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- class: register
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prefix: f
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latency: 3
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throughput: 1
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port_pressure: [[1, ["FP"]]]
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- name: FMUL.S
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operands:
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- class: register
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prefix: f
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- class: register
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prefix: f
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- class: register
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prefix: f
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latency: 3
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throughput: 1
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port_pressure: [[1, ["FP"]]]
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- name: FDIV.S
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operands:
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- class: register
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prefix: f
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- class: register
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prefix: f
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- class: register
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prefix: f
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latency: 10
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throughput: 10
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port_pressure: [[1, ["FP"]]]
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- name: FMADD.S
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operands:
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- class: register
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prefix: f
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- class: register
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prefix: f
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- class: register
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prefix: f
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- class: register
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prefix: f
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latency: 4
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throughput: 1
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port_pressure: [[1, ["FP"]]]
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# Vector instructions
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- name: VSETVLI
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operands:
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- class: register
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prefix: x
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- class: register
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prefix: x
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- class: identifier
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- class: identifier
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- class: identifier
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- class: identifier
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latency: 1
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throughput: 1
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port_pressure: [[1, ["ALU"]]]
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- name: VLE64.V
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operands:
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- class: register
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prefix: v
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- class: memory
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base: x
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offset: imd
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index: null
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scale: 1
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latency: 4
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throughput: 1
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port_pressure: [[1, ["MEM"]]]
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- name: VLE8.V
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operands:
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- class: register
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prefix: v
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- class: memory
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base: x
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offset: imd
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index: null
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scale: 1
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latency: 4
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throughput: 1
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port_pressure: [[1, ["MEM"]]]
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- name: VSE64.V
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operands:
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- class: register
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prefix: v
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- class: memory
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base: x
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offset: imd
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index: null
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scale: 1
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latency: 1
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throughput: 1
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port_pressure: [[1, ["MEM"]]]
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- name: VSE8.V
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operands:
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- class: register
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prefix: v
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- class: memory
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base: x
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offset: imd
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index: null
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scale: 1
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latency: 1
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throughput: 1
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port_pressure: [[1, ["MEM"]]]
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- name: VFMACC.VF
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operands:
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- class: register
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prefix: v
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- class: register
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prefix: f
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- class: register
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prefix: v
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latency: 4
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throughput: 1
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port_pressure: [[1, ["FP"]]]
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- name: VFMACC.VV
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operands:
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- class: register
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prefix: v
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- class: register
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prefix: v
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- class: register
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prefix: v
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latency: 4
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throughput: 1
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port_pressure: [[1, ["FP"]]]
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- name: VFADD.VV
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operands:
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- class: register
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prefix: v
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- class: register
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prefix: v
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- class: register
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prefix: v
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latency: 3
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throughput: 1
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|
port_pressure: [[1, ["FP"]]]
|
|
|
|
- name: VFMADD.VV
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
- class: register
|
|
prefix: v
|
|
- class: register
|
|
prefix: v
|
|
latency: 4
|
|
throughput: 1
|
|
port_pressure: [[1, ["FP"]]]
|
|
|
|
- name: FMUL.D
|
|
operands:
|
|
- class: register
|
|
prefix: f
|
|
- class: register
|
|
prefix: f
|
|
- class: register
|
|
prefix: f
|
|
latency: 3
|
|
throughput: 1
|
|
port_pressure: [[1, ["FP"]]]
|
|
|
|
- name: VFMUL.VF
|
|
operands:
|
|
- class: register
|
|
prefix: v
|
|
- class: register
|
|
prefix: v
|
|
- class: register
|
|
prefix: f
|
|
latency: 4
|
|
throughput: 1
|
|
port_pressure: [[1, ["FP"]]]
|
|
|
|
- name: J
|
|
operands:
|
|
- class: identifier
|
|
latency: 1
|
|
throughput: 1
|
|
port_pressure: [[1, ["ALU"]]]
|
|
|
|
# CSR instructions
|
|
- name: CSRR
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: identifier
|
|
latency: 1
|
|
throughput: 1
|
|
port_pressure: [[1, ["ALU"]]]
|
|
|
|
- name: CSRW
|
|
operands:
|
|
- class: identifier
|
|
- class: register
|
|
prefix: x
|
|
latency: 1
|
|
throughput: 1
|
|
port_pressure: [[1, ["ALU"]]]
|
|
|
|
# Pseudo-instructions
|
|
- name: MV
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: register
|
|
prefix: x
|
|
latency: 1
|
|
throughput: 1
|
|
port_pressure: [[1, ["ALU"]]]
|
|
|
|
- name: LI
|
|
operands:
|
|
- class: register
|
|
prefix: x
|
|
- class: immediate
|
|
imd: int
|
|
latency: 1
|
|
throughput: 1
|
|
port_pressure: [[1, ["ALU"]]]
|
|
|
|
- name: RET
|
|
operands: []
|
|
latency: 1
|
|
throughput: 1
|
|
port_pressure: [[1, ["ALU"]]] |