mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2026-01-09 04:30:05 +01:00
103 lines
2.1 KiB
Python
Executable File
103 lines
2.1 KiB
Python
Executable File
#!/usr/bin/env python3
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import os
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from jinja2 import Template
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class IbenchAPI(object):
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def __init__(self, isa):
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# TODO
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self.isa = isa.lower()
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def create_ubenchmark(self):
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# TODO
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if self.isa == 'aarch64':
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self.create_ubench_aarch64()
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elif self.isa == 'x86':
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self.create_ubench_x86()
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def import_ibench_output(self, filepath):
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# TODO
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assert os.path.exists(filepath)
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raise NotImplementedError
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def create_ubench_aarch(self):
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# TODO
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raise NotImplementedError
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def create_ubench_x86(self):
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# TODO
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raise NotImplementedError
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# TODO
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# template_x86 = Template()
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template_aarch64 = Template(
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'''
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#define INSTR {{ instr }}
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#define NINST {{ ninst }}
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#define N x0
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.globl ninst
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.data
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ninst:
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.long NINST
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{% if imd %}
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IMD:
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.long 0xf01b866e, 0x400921f9, 0xf01b866e, 0x400921f9
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{% endif %}
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.text
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.globl latency
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.type latency, @function
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.align 32
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latency:
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{% if vector_regs %}
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# push callee-save registers onto stack
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sub sp, sp, #64
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st1 {v8.4s, v9.4s, v10.4s, v11.4s}, [sp]
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sub sp, sp, #64
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st1 {v12.4s, v13.4s, v14.4s, v15.4s}, [sp]
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mov x4, N
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fmov v0.2d, #1.00000000
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fmov v1.2d, #1.00000000
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fmov v2.2d, #1.00000000
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fmov v3.2d, #1.00000000
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fmov v4.2d, #1.00000000
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fmov v5.2d, #1.00000000
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fmov v6.2d, #1.00000000
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fmov v7.2d, #1.00000000
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fmov v8.2d, #1.00000000
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fmov v9.2d, #1.00000000
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fmov v10.2d, #1.00000000
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fmov v11.2d, #1.00000000
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fmov v12.2d, #1.00000000
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fmov v13.2d, #1.00000000
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fmov v14.2d, #1.00000000
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fmov v15.2d, #1.00000000
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{% endif %}
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{% if gp_regs %}
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{% endif %}
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loop:
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{{ loop_kernel }}
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subs x4, x4, #1
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bne loop
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done:
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{% if vector_regs %}
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# pop callee-save registers from stack
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ld1 {v12.4s, v13.4s, v14.4s, v15.4s}, [sp]
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add sp, sp, #64
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ld1 {v8.4s, v9.4s, v10.4s, v11.4s}, [sp]
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add sp, sp, #64
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{% endif %}
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{% if gp_regs %}
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{% endif %}
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ret
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.size latency, .-latency
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'''
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)
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