mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2025-12-16 09:00:05 +01:00
983 lines
40 KiB
Python
983 lines
40 KiB
Python
#!/usr/bin/env python3
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import hashlib
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import os
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import pickle
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import re
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import string
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from collections import defaultdict
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from itertools import product
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from pathlib import Path
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import ruamel.yaml
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from osaca import __version__, utils
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from osaca.parser import ParserX86ATT
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from osaca.parser.instruction_form import instructionForm
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from osaca.parser.operand import Operand
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from osaca.parser.memory import MemoryOperand
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from osaca.parser.register import RegisterOperand
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from osaca.parser.immediate import ImmediateOperand
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from osaca.parser.identifier import IdentifierOperand
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from osaca.parser.condition import ConditionOperand
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class MachineModel(object):
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WILDCARD = "*"
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INTERNAL_VERSION = 1 # increase whenever self._data format changes to invalidate cache!
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_runtime_cache = {}
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def __init__(self, arch=None, path_to_yaml=None, isa=None, lazy=False):
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if not arch and not path_to_yaml:
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if not isa:
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raise ValueError("One of arch, path_to_yaml and isa must be specified")
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self._data = {
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"osaca_version": str(__version__),
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"micro_architecture": None,
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"arch_code": None,
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"isa": isa,
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"ROB_size": None,
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"retired_uOps_per_cycle": None,
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"scheduler_size": None,
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"hidden_loads": None,
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"load_latency": {},
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"load_throughput": [
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{
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"base": b,
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"index": i,
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"offset": o,
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"scale": s,
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"port_pressure": [],
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}
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for b, i, o, s in product(["gpr"], ["gpr", None], ["imd", None], [1, 8])
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],
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"load_throughput_default": [],
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"store_throughput": [],
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"store_throughput_default": [],
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"store_to_load_forward_latency": None,
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"ports": [],
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"port_model_scheme": None,
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"instruction_forms": [],
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"instruction_forms_dict": defaultdict(list),
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}
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else:
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if arch and path_to_yaml:
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raise ValueError("Only one of arch and path_to_yaml is allowed.")
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self._path = path_to_yaml
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self._arch = arch
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if arch:
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self._arch = arch.lower()
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self._path = utils.find_datafile(self._arch + ".yml")
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# Check runtime cache
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if self._path in MachineModel._runtime_cache and not lazy:
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self._data = MachineModel._runtime_cache[self._path]
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# check if file is cached
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cached = self._get_cached(self._path) if not lazy else False
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if cached:
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self._data = cached
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else:
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yaml = self._create_yaml_object()
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# otherwise load
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with open(self._path, "r") as f:
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if not lazy:
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self._data = yaml.load(f)
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else:
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file_content = ""
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line = f.readline()
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while "instruction_forms:" not in line:
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file_content += line
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line = f.readline()
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self._data = yaml.load(file_content)
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self._data["instruction_forms"] = []
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# separate multi-alias instruction forms
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for entry in [
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x for x in self._data["instruction_forms"] if isinstance(x["name"], list)
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]:
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for name in entry["name"]:
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new_entry = {"name": name}
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for k in [x for x in entry.keys() if x != "name"]:
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new_entry[k] = entry[k]
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self._data["instruction_forms"].append(new_entry)
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# remove old entry
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self._data["instruction_forms"].remove(entry)
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# Normalize instruction_form names (to UPPERCASE) and build dict for faster access:
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self._data["instruction_forms_dict"] = defaultdict(list)
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for iform in self._data["instruction_forms"]:
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iform["name"] = iform["name"].upper()
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if iform["operands"] != []:
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new_operands = []
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# Change operand types from dicts to classes
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for o in iform["operands"]:
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self.operand_to_class(o, new_operands)
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iform["operands"] = new_operands
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# Do the same for hidden operands
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if "hidden_operands" in iform:
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new_operands = []
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# Change operand types from dicts to classes
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for o in iform["hidden_operands"]:
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self.operand_to_class(o, new_operands)
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iform["hidden_operands"] = new_operands
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# Change dict iform style to class style
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new_iform = instructionForm(
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instruction_id=iform["name"].upper() if "name" in iform else None,
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operands_id=iform["operands"] if "operands" in iform else [],
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hidden_operands=iform["hidden_operands"]
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if "hidden_operands" in iform
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else [],
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directive_id=iform["directive"] if "directive" in iform else None,
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comment_id=iform["comment"] if "comment" in iform else None,
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line=iform["line"] if "line" in iform else None,
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line_number=iform["line_number"] if "line_number" in iform else None,
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latency=iform["latency"] if "latency" in iform else None,
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throughput=iform["throughput"] if "throughput" in iform else None,
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uops=iform["uops"] if "uops" in iform else None,
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port_pressure=iform["port_pressure"] if "port_pressure" in iform else None,
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operation=iform["operation"] if "operation" in iform else None,
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breaks_dep=iform["breaks_dependency_on_equal_operands"]
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if "breaks_dependency_on_equal_operands" in iform
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else False,
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semantic_operands=iform["semantic_operands"]
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if "semantic_operands" in iform
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else {"source": [], "destination": [], "src_dst": []},
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)
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# List containing classes with same name/instruction
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self._data["instruction_forms_dict"][iform["name"]].append(new_iform)
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self._data["internal_version"] = self.INTERNAL_VERSION
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self.load_store_tp()
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if not lazy:
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# cache internal representation for future use
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self._write_in_cache(self._path)
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# Store in runtime cache
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if not lazy:
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MachineModel._runtime_cache[self._path] = self._data
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def load_store_tp(self):
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new_throughputs = []
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if "load_throughput" in self._data:
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for m in self._data["load_throughput"]:
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new_throughputs.append(
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MemoryOperand(
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base_id=m["base"],
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offset_ID=m["offset"],
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scale_id=m["scale"],
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index_id=m["index"],
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port_pressure=m["port_pressure"],
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dst=m["dst"] if "dst" in m else None,
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)
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)
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self._data["load_throughput"] = new_throughputs
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new_throughputs = []
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if "store_throughput" in self._data:
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for m in self._data["store_throughput"]:
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new_throughputs.append(
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MemoryOperand(
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base_id=m["base"],
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offset_ID=m["offset"],
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scale_id=m["scale"],
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index_id=m["index"],
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port_pressure=m["port_pressure"],
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)
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)
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self._data["store_throughput"] = new_throughputs
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def operand_to_class(self, o, new_operands):
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"""Convert an operand from dict type to class"""
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if o["class"] == "register":
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new_operands.append(
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RegisterOperand(
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name=o["name"] if "name" in o else None,
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prefix_id=o["prefix"] if "prefix" in o else None,
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shape=o["shape"] if "shape" in o else None,
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mask=o["mask"] if "mask" in o else False,
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pre_indexed=o["pre_indexed"] if "pre_indexed" in o else False,
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post_indexed=o["post_indexed"] if "post_indexed" in o else False,
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source=o["source"] if "source" in o else False,
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destination=o["destination"] if "destination" in o else False,
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)
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)
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elif o["class"] == "memory":
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if isinstance(o["base"], dict):
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o["base"] = RegisterOperand(name=o["base"]["name"])
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if isinstance(o["index"], dict):
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o["index"] = RegisterOperand(
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name=o["index"]["name"],
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prefix_id=o["index"]["prefix"] if "prefix" in o["index"] else None,
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)
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new_operands.append(
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MemoryOperand(
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base_id=o["base"],
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offset_ID=o["offset"],
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index_id=o["index"],
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scale_id=o["scale"],
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source=o["source"] if "source" in o else False,
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destination=o["destination"] if "destination" in o else False,
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pre_indexed=o["pre_indexed"] if "pre_indexed" in o else False,
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post_indexed=o["post_indexed"] if "post_indexed" in o else False,
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)
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)
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elif o["class"] == "immediate":
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new_operands.append(
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ImmediateOperand(
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type_id=o["imd"],
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source=o["source"] if "source" in o else False,
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destination=o["destination"] if "destination" in o else False,
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)
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)
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elif o["class"] == "identifier":
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new_operands.append(
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IdentifierOperand(
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name=o["name"] if "name" in o else None,
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source=o["source"] if "source" in o else False,
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destination=o["destination"] if "destination" in o else False,
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)
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)
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elif o["class"] == "condition":
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new_operands.append(
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ConditionOperand(
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ccode=o["ccode"].upper(),
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source=o["source"] if "source" in o else False,
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destination=o["destination"] if "destination" in o else False,
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)
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)
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else:
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new_operands.append(o)
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def get(self, key, default=None):
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"""Return config entry for key or default/None."""
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return self._data.get(key, default)
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def __getitem__(self, key):
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"""Return configuration entry."""
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return self._data[key]
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def __contains__(self, key):
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"""Return true if configuration key is present."""
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return key in self._data
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######################################################
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def get_instruction(self, name, operands):
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"""Find and return instruction data from name and operands."""
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# For use with dict instead of list as DB
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if name is None:
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return None
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name_matched_iforms = self._data["instruction_forms_dict"].get(name.upper(), [])
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try:
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return next(
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instruction_form
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for instruction_form in name_matched_iforms
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if self._match_operands(
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instruction_form.operands,
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operands,
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)
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)
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except StopIteration:
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return None
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except TypeError as e:
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print("\nname: {}\noperands: {}".format(name, operands))
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raise TypeError from e
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def average_port_pressure(self, port_pressure, option=0):
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"""Construct average port pressure list from instruction data."""
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port_list = self._data["ports"]
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average_pressure = [0.0] * len(port_list)
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# if there are multiple port utilization options and none is selected, choose first one
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if isinstance(port_pressure, dict):
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used_pp = port_pressure[option]
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else:
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used_pp = port_pressure
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for cycles, ports in used_pp:
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for p in ports:
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try:
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average_pressure[port_list.index(p)] += cycles / len(ports)
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except ValueError as e:
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raise KeyError("Port {!r} not in port list.".format(p)) from e
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return average_pressure
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def set_instruction(
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self,
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instruction,
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operands=None,
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latency=None,
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port_pressure=None,
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throughput=None,
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uops=None,
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):
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"""Import instruction form information."""
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# If it already exists. Overwrite information.
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instr_data = self.get_instruction(instruction, operands)
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if instr_data is None:
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instr_data = instructionForm()
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self._data["instruction_forms"].append(instr_data)
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self._data["instruction_forms_dict"][instruction].append(instr_data)
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instr_data.instruction = instruction
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instr_data.operands = operands
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instr_data.latency = latency
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instr_data.port_pressure = port_pressure
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instr_data.throughput = throughput
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instr_data.uops = uops
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def set_instruction_entry(self, entry):
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"""Import instruction as entry object form information."""
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if entry.instruction is None and entry.operands == []:
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raise KeyError
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self.set_instruction(
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entry.instruction,
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entry.operands,
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entry.latency,
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entry.port_pressure,
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entry.throughput,
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entry.uops,
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)
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def add_port(self, port):
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"""Add port in port model of current machine model."""
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if port not in self._data["ports"]:
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self._data["ports"].append(port)
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def get_ISA(self):
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"""Return ISA of :class:`MachineModel`."""
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return self._data["isa"].lower()
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def get_arch(self):
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"""Return micro-architecture code of :class:`MachineModel`."""
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return self._data["arch_code"].lower()
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def get_ports(self):
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"""Return port model of :class:`MachineModel`."""
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return self._data["ports"]
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def has_hidden_loads(self):
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"""Return if model has hidden loads."""
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if "hidden_loads" in self._data:
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return self._data["hidden_loads"]
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return False
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def get_load_latency(self, reg_type):
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"""Return load latency for given register type."""
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return self._data["load_latency"][reg_type] if self._data["load_latency"][reg_type] else 0
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def get_load_throughput(self, memory):
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"""Return load thorughput for given register type."""
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ld_tp = [m for m in self._data["load_throughput"] if self._match_mem_entries(memory, m)]
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if len(ld_tp) > 0:
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return ld_tp.copy()
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return [MemoryOperand(port_pressure=self._data["load_throughput_default"].copy())]
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def get_store_latency(self, reg_type):
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"""Return store latency for given register type."""
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# assume 0 for now, since load-store-dependencies currently not detectable
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return 0
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def get_store_throughput(self, memory, src_reg=None):
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"""Return store throughput for a given destination and register type."""
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st_tp = [m for m in self._data["store_throughput"] if self._match_mem_entries(memory, m)]
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if src_reg is not None:
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st_tp = [
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tp
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for tp in st_tp
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if "src" in tp and self._check_operands(src_reg, RegisterOperand(name=tp["src"]))
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]
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if len(st_tp) > 0:
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return st_tp.copy()
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return [MemoryOperand(port_pressure=self._data["store_throughput_default"].copy())]
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def _match_mem_entries(self, mem, i_mem):
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"""Check if memory addressing ``mem`` and ``i_mem`` are of the same type."""
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if self._data["isa"].lower() == "aarch64":
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return self._is_AArch64_mem_type(i_mem, mem)
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if self._data["isa"].lower() == "x86":
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return self._is_x86_mem_type(i_mem, mem)
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def get_data_ports(self):
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"""Return all data ports (i.e., ports with D-suffix) of current model."""
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data_port = re.compile(r"^[0-9]+D$")
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data_ports = [x for x in filter(data_port.match, self._data["ports"])]
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return data_ports
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@staticmethod
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def get_full_instruction_name(instruction_form):
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"""Get one instruction name string including the mnemonic and all operands."""
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operands = []
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for op in instruction_form.operands:
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op_attrs = []
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if op.name is not None:
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op_attrs.append("name:" + op.name)
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if op.prefix is not None:
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op_attrs.append("prefix:" + op.prefix)
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if op.shape is not None:
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op_attrs.append("shape:" + op.shape)
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operands.append("{}({})".format("register", ",".join(op_attrs)))
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return "{} {}".format(instruction_form.instruction.lower(), ",".join(operands))
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@staticmethod
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def get_isa_for_arch(arch):
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"""Return ISA for given micro-arch ``arch``."""
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arch_dict = {
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"a64fx": "aarch64",
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"tsv110": "aarch64",
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"a72": "aarch64",
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"tx2": "aarch64",
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"n1": "aarch64",
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"zen1": "x86",
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"zen+": "x86",
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"zen2": "x86",
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"zen3": "x86",
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"con": "x86", # Intel Conroe
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"wol": "x86", # Intel Wolfdale
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"snb": "x86",
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"ivb": "x86",
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"hsw": "x86",
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"bdw": "x86",
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"skl": "x86",
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"skx": "x86",
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"csx": "x86",
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"wsm": "x86",
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"nhm": "x86",
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"kbl": "x86",
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"cnl": "x86",
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"cfl": "x86",
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"icl": "x86",
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"icx": "x86",
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}
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arch = arch.lower()
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if arch in arch_dict:
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return arch_dict[arch].lower()
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else:
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raise ValueError("Unknown architecture {!r}.".format(arch))
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def dump(self, stream=None):
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"""Dump machine model to stream or return it as a ``str`` if no stream is given."""
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# Replace instruction form's port_pressure with styled version for RoundtripDumper
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'''
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formatted_instruction_forms = deepcopy(self._data["instruction_forms"])
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for instruction_form in formatted_instruction_forms:
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if instruction_form["port_pressure"] is not None:
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cs = ruamel.yaml.comments.CommentedSeq(instruction_form["port_pressure"])
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cs.fa.set_flow_style()
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instruction_form["port_pressure"] = cs
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# Replace load_throughput with styled version for RoundtripDumper
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formatted_load_throughput = []
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for lt in self._data["load_throughput"]:
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lt = self.operand_to_dict(lt)
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cm = ruamel.yaml.comments.CommentedMap(lt)
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cm.fa.set_flow_style()
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formatted_load_throughput.append(cm)
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# Create YAML object
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# yaml = self._create_yaml_object()
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if not stream:
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stream = StringIO()
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"""
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yaml.dump(
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{
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k: v
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for k, v in self._data.items()
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if k
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not in [
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"instruction_forms",
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"instruction_forms_dict",
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"load_throughput",
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"internal_version",
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]
|
|
},
|
|
stream,
|
|
)
|
|
|
|
yaml.dump({"load_throughput": formatted_load_throughput}, stream)
|
|
yaml.dump({"instruction_forms": formatted_instruction_forms}, stream)
|
|
"""
|
|
if isinstance(stream, StringIO):
|
|
return stream.getvalue()
|
|
'''
|
|
|
|
def operand_to_dict(self, mem):
|
|
return {
|
|
"base": mem.base,
|
|
"offset": mem.offset,
|
|
"index": mem.index,
|
|
"scale": mem.scale,
|
|
"port_pressure": mem.port_pressure,
|
|
}
|
|
|
|
######################################################
|
|
|
|
def _get_cached(self, filepath):
|
|
"""
|
|
Check if machine model is cached and if so, load it.
|
|
|
|
:param filepath: path to check for cached machine model
|
|
:type filepath: str
|
|
:returns: cached DB if existing, `False` otherwise
|
|
"""
|
|
p = Path(filepath)
|
|
hexhash = hashlib.sha256(p.read_bytes()).hexdigest()
|
|
|
|
# 1. companion cachefile: same location, with '.<name>_<sha512hash>.pickle'
|
|
companion_cachefile = p.with_name("." + p.stem + "_" + hexhash).with_suffix(".pickle")
|
|
if companion_cachefile.exists():
|
|
# companion file (must be up-to-date, due to equal hash)
|
|
with companion_cachefile.open("rb") as f:
|
|
data = pickle.load(f)
|
|
if data.get("internal_version") == self.INTERNAL_VERSION:
|
|
return data
|
|
|
|
# 2. home cachefile: ~/.osaca/cache/<name>_<sha512hash>.pickle
|
|
home_cachefile = (Path(utils.CACHE_DIR) / (p.stem + "_" + hexhash)).with_suffix(".pickle")
|
|
if home_cachefile.exists():
|
|
# home file (must be up-to-date, due to equal hash)
|
|
with home_cachefile.open("rb") as f:
|
|
data = pickle.load(f)
|
|
if data.get("internal_version") == self.INTERNAL_VERSION:
|
|
return data
|
|
return False
|
|
|
|
def _write_in_cache(self, filepath):
|
|
"""
|
|
Write machine model to cache
|
|
|
|
:param filepath: path to store DB
|
|
:type filepath: str
|
|
"""
|
|
p = Path(filepath)
|
|
hexhash = hashlib.sha256(p.read_bytes()).hexdigest()
|
|
# 1. companion cachefile: same location, with '.<name>_<sha512hash>.pickle'
|
|
companion_cachefile = p.with_name("." + p.stem + "_" + hexhash).with_suffix(".pickle")
|
|
if os.access(str(companion_cachefile.parent), os.W_OK):
|
|
with companion_cachefile.open("wb") as f:
|
|
pickle.dump(self._data, f)
|
|
return
|
|
|
|
# 2. home cachefile: ~/.osaca/cache/<name>_<sha512hash>.pickle
|
|
cache_dir = Path(utils.CACHE_DIR)
|
|
try:
|
|
os.makedirs(cache_dir, exist_ok=True)
|
|
except OSError:
|
|
return
|
|
home_cachefile = (cache_dir / (p.stem + "_" + hexhash)).with_suffix(".pickle")
|
|
if os.access(str(home_cachefile.parent), os.W_OK):
|
|
with home_cachefile.open("wb") as f:
|
|
pickle.dump(self._data, f)
|
|
|
|
def _get_key(self, name, operands):
|
|
"""Get unique instruction form key for dict DB."""
|
|
key_string = name.lower() + "-"
|
|
if operands is None:
|
|
return key_string[:-1]
|
|
key_string += "_".join([self._get_operand_hash(op) for op in operands])
|
|
return key_string
|
|
|
|
def _get_operand_hash(self, operand):
|
|
"""Get unique key for operand for dict DB"""
|
|
operand_string = ""
|
|
if "class" in operand:
|
|
# DB entry
|
|
opclass = operand["class"]
|
|
else:
|
|
# parsed instruction
|
|
opclass = list(operand.keys())[0]
|
|
operand = operand[opclass]
|
|
if opclass == "immediate":
|
|
# Immediate
|
|
operand_string += "i"
|
|
elif opclass == "register":
|
|
# Register
|
|
if "prefix" in operand:
|
|
operand_string += operand["prefix"]
|
|
operand_string += operand["shape"] if "shape" in operand else ""
|
|
elif "name" in operand:
|
|
operand_string += "r" if operand["name"] == "gpr" else operand["name"][0]
|
|
elif opclass == "memory":
|
|
# Memory
|
|
operand_string += "m"
|
|
operand_string += "b" if operand["base"] is not None else ""
|
|
operand_string += "o" if operand["offset"] is not None else ""
|
|
operand_string += "i" if operand["index"] is not None else ""
|
|
operand_string += (
|
|
"s" if operand["scale"] == self.WILDCARD or operand["scale"] > 1 else ""
|
|
)
|
|
if "pre_indexed" in operand:
|
|
operand_string += "r" if operand["pre_indexed"] else ""
|
|
operand_string += "p" if operand["post_indexed"] else ""
|
|
return operand_string
|
|
|
|
def _create_db_operand_aarch64(self, operand):
|
|
"""Create instruction form operand for DB out of operand string."""
|
|
if operand == "i":
|
|
return ImmediateOperand(type_id="int")
|
|
elif operand in "wxbhsdq":
|
|
return RegisterOperand(prefix_id=operand)
|
|
elif operand.startswith("v"):
|
|
return RegisterOperand(prefix_id="v", shape=operand[1:2])
|
|
elif operand.startswith("m"):
|
|
return MemoryOperand(
|
|
base_id="x" if "b" in operand else None,
|
|
offset_ID="imd" if "o" in operand else None,
|
|
index_id="gpr" if "i" in operand else None,
|
|
scale_id=8 if "s" in operand else 1,
|
|
pre_indexed=True if "r" in operand else False,
|
|
post_indexed=True if "p" in operand else False,
|
|
)
|
|
else:
|
|
raise ValueError("Parameter {} is not a valid operand code".format(operand))
|
|
|
|
def _create_db_operand_x86(self, operand):
|
|
"""Create instruction form operand for DB out of operand string."""
|
|
if operand == "r":
|
|
return RegisterOperand(name="gpr")
|
|
elif operand in "xyz":
|
|
return RegisterOperand(name=operand + "mm")
|
|
elif operand == "i":
|
|
return ImmediateOperand(type_id="int")
|
|
elif operand.startswith("m"):
|
|
return MemoryOperand(
|
|
base_id="gpr" if "b" in operand else None,
|
|
offset_ID="imd" if "o" in operand else None,
|
|
index_id="gpr" if "i" in operand else None,
|
|
scale_id=8 if "s" in operand else 1,
|
|
)
|
|
else:
|
|
raise ValueError("Parameter {} is not a valid operand code".format(operand))
|
|
|
|
def _check_for_duplicate(self, name, operands):
|
|
"""
|
|
Check if instruction form exists at least twice in DB.
|
|
|
|
:param str name: mnemonic of instruction form
|
|
:param list operands: instruction form operands
|
|
|
|
:returns: `True`, if duplicate exists, `False` otherwise
|
|
"""
|
|
matches = [
|
|
instruction_form
|
|
for instruction_form in self._data["instruction_forms"]
|
|
if instruction_form["name"].lower() == name.lower()
|
|
and self._match_operands(instruction_form["operands"], operands)
|
|
]
|
|
if len(matches) > 1:
|
|
return True
|
|
return False
|
|
|
|
def _match_operands(self, i_operands, operands):
|
|
"""Check if all operand types of ``i_operands`` and ``operands`` match."""
|
|
operands_ok = True
|
|
if len(operands) != len(i_operands):
|
|
return False
|
|
for idx, operand in enumerate(operands):
|
|
i_operand = i_operands[idx]
|
|
operands_ok = operands_ok and self._check_operands(i_operand, operand)
|
|
if operands_ok:
|
|
return True
|
|
else:
|
|
return False
|
|
|
|
def _check_operands(self, i_operand, operand):
|
|
"""Check if the types of operand ``i_operand`` and ``operand`` match."""
|
|
# check for wildcard
|
|
if isinstance(operand, dict) and self.WILDCARD in operand:
|
|
if isinstance(i_operand, RegisterOperand):
|
|
return True
|
|
else:
|
|
return False
|
|
if self._data["isa"].lower() == "aarch64":
|
|
return self._check_AArch64_operands(i_operand, operand)
|
|
if self._data["isa"].lower() == "x86":
|
|
return self._check_x86_operands(i_operand, operand)
|
|
|
|
def _check_AArch64_operands(self, i_operand, operand):
|
|
"""Check if the types of operand ``i_operand`` and ``operand`` match."""
|
|
# if "class" in operand:
|
|
# compare two DB entries
|
|
# return self._compare_db_entries(i_operand, operand)
|
|
# TODO support class wildcards
|
|
# register
|
|
if isinstance(operand, RegisterOperand):
|
|
if not isinstance(i_operand, RegisterOperand):
|
|
return False
|
|
return self._is_AArch64_reg_type(i_operand, operand)
|
|
# memory
|
|
if isinstance(operand, MemoryOperand):
|
|
if not isinstance(i_operand, MemoryOperand):
|
|
return False
|
|
return self._is_AArch64_mem_type(i_operand, operand)
|
|
# immediate
|
|
if isinstance(i_operand, ImmediateOperand) and i_operand.type == self.WILDCARD:
|
|
return isinstance(operand, ImmediateOperand) and (operand.value is not None)
|
|
|
|
if isinstance(i_operand, ImmediateOperand) and i_operand.type == "int":
|
|
return (
|
|
isinstance(operand, ImmediateOperand)
|
|
and operand.type == "int"
|
|
and operand.value is not None
|
|
)
|
|
|
|
if isinstance(i_operand, ImmediateOperand) and i_operand.type == "float":
|
|
return (
|
|
isinstance(operand, ImmediateOperand)
|
|
and operand.type == "float"
|
|
and operand.value is not None
|
|
)
|
|
|
|
if isinstance(i_operand, ImmediateOperand) and i_operand.type == "double":
|
|
return (
|
|
isinstance(operand, ImmediateOperand)
|
|
and operand.type == "double"
|
|
and operand.value is not None
|
|
)
|
|
|
|
# identifier
|
|
if isinstance(operand, IdentifierOperand) or (
|
|
isinstance(operand, ImmediateOperand) and operand.identifier is not None
|
|
):
|
|
return isinstance(i_operand, IdentifierOperand)
|
|
# prefetch option
|
|
if not isinstance(operand, Operand) and "prfop" in operand:
|
|
return i_operand["class"] == "prfop"
|
|
# condition
|
|
if isinstance(operand, ConditionOperand):
|
|
if isinstance(i_operand, ConditionOperand):
|
|
return (i_operand.ccode == self.WILDCARD) or (i_operand.ccode == operand.ccode)
|
|
# no match
|
|
return False
|
|
|
|
def _check_x86_operands(self, i_operand, operand):
|
|
"""Check if the types of operand ``i_operand`` and ``operand`` match."""
|
|
# if "class" in operand.name:
|
|
# compare two DB entries
|
|
# return self._compare_db_entries(i_operand, operand)
|
|
# register
|
|
if isinstance(operand, RegisterOperand):
|
|
if not isinstance(i_operand, RegisterOperand):
|
|
return False
|
|
return self._is_x86_reg_type(i_operand, operand, consider_masking=False)
|
|
# memory
|
|
if isinstance(operand, MemoryOperand):
|
|
if not isinstance(i_operand, MemoryOperand):
|
|
return False
|
|
return self._is_x86_mem_type(i_operand, operand)
|
|
# immediate
|
|
if isinstance(operand, ImmediateOperand):
|
|
# if "immediate" in operand.name or operand.value != None:
|
|
return isinstance(i_operand, ImmediateOperand) and i_operand.type == "int"
|
|
# identifier (e.g., labels)
|
|
if isinstance(operand, IdentifierOperand):
|
|
return isinstance(i_operand, IdentifierOperand)
|
|
return self._compare_db_entries(i_operand, operand)
|
|
|
|
def _compare_db_entries(self, operand_1, operand_2):
|
|
"""Check if operand types in DB format (i.e., not parsed) match."""
|
|
return True
|
|
operand_attributes = list(
|
|
filter(
|
|
lambda x: True if x != "source" and x != "destination" else False,
|
|
operand_1,
|
|
)
|
|
)
|
|
for key in operand_attributes:
|
|
try:
|
|
if operand_1[key] != operand_2[key] and not any(
|
|
[x == self.WILDCARD for x in [operand_1[key], operand_2[key]]]
|
|
):
|
|
return False
|
|
except KeyError:
|
|
return False
|
|
return True
|
|
|
|
def _is_AArch64_reg_type(self, i_reg, reg):
|
|
"""Check if register type match."""
|
|
# check for wildcards
|
|
if reg.prefix == self.WILDCARD or i_reg.prefix == self.WILDCARD:
|
|
if reg.shape is not None:
|
|
if i_reg.shape is not None and (
|
|
reg.shape == i_reg.shape or self.WILDCARD in (reg.shape + i_reg.shape)
|
|
):
|
|
return True
|
|
return False
|
|
return True
|
|
# check for prefix and shape
|
|
if reg.prefix != i_reg.prefix:
|
|
return False
|
|
if reg.shape is not None:
|
|
if i_reg.shape is not None and (
|
|
reg.shape == i_reg.shape or self.WILDCARD in (reg.shape + i_reg.shape)
|
|
):
|
|
return True
|
|
return False
|
|
if reg.lanes is not None:
|
|
if i_reg.lanes is not None and (
|
|
reg.lanes == i_reg.lanes or self.WILDCARD in (reg.lanes + i_reg.lanes)
|
|
):
|
|
return True
|
|
return False
|
|
return True
|
|
|
|
def _is_x86_reg_type(self, i_reg, reg, consider_masking=False):
|
|
"""Check if register type match."""
|
|
if reg is None:
|
|
if i_reg is None:
|
|
return True
|
|
return False
|
|
if isinstance(i_reg, RegisterOperand):
|
|
i_reg_name = i_reg.name
|
|
else:
|
|
i_reg_name = i_reg
|
|
# check for wildcards
|
|
if isinstance(reg, str):
|
|
return False
|
|
if i_reg_name is None and reg.name is None:
|
|
return True
|
|
if i_reg_name == self.WILDCARD or reg.name == self.WILDCARD:
|
|
return True
|
|
# differentiate between vector registers (mm, xmm, ymm, zmm) and others (gpr)
|
|
parser_x86 = ParserX86ATT()
|
|
if parser_x86.is_vector_register(reg):
|
|
if reg.name.rstrip(string.digits).lower() == i_reg_name:
|
|
# Consider masking and zeroing for AVX512
|
|
if consider_masking:
|
|
mask_ok = zero_ok = True
|
|
if reg.mask is not None or i_reg.mask is not None:
|
|
# one instruction is missing the masking while the other has it
|
|
mask_ok = False
|
|
# check for wildcard
|
|
if (
|
|
(
|
|
reg.mask is not None
|
|
and reg.mask.rstrip(string.digits).lower() == i_reg.mask
|
|
)
|
|
or reg.mask == self.WILDCARD
|
|
or i_reg.mask == self.WILDCARD
|
|
):
|
|
mask_ok = True
|
|
if bool(reg.zeroing) ^ bool("zeroing" in i_reg):
|
|
# one instruction is missing zeroing while the other has it
|
|
zero_ok = False
|
|
# check for wildcard
|
|
if i_reg.zeroing == self.WILDCARD or reg.zeroing == self.WILDCARD:
|
|
zero_ok = True
|
|
if not mask_ok or not zero_ok:
|
|
return False
|
|
return True
|
|
else:
|
|
if reg.name.rstrip(string.digits).lower() == i_reg_name:
|
|
return True
|
|
if i_reg_name == "gpr":
|
|
return True
|
|
return False
|
|
|
|
def _is_AArch64_mem_type(self, i_mem, mem):
|
|
"""Check if memory addressing type match."""
|
|
if (
|
|
# check base
|
|
(
|
|
(mem.base is None and i_mem.base is None)
|
|
or i_mem.base == self.WILDCARD
|
|
or (isinstance(mem.base, RegisterOperand) and (mem.base.prefix == i_mem.base))
|
|
)
|
|
# check offset
|
|
and (
|
|
mem.offset == i_mem.offset
|
|
or i_mem.offset == self.WILDCARD
|
|
or (
|
|
mem.offset is not None
|
|
and isinstance(mem.offset, IdentifierOperand)
|
|
and isinstance(i_mem.offset, IdentifierOperand)
|
|
)
|
|
or (
|
|
mem.offset is not None
|
|
and isinstance(mem.offset, ImmediateOperand)
|
|
and i_mem.offset == "imd"
|
|
)
|
|
)
|
|
# check index
|
|
and (
|
|
mem.index == i_mem.index
|
|
or i_mem.index == self.WILDCARD
|
|
or (
|
|
mem.index is not None
|
|
and mem.index.prefix is not None
|
|
and mem.index.prefix == i_mem.index
|
|
)
|
|
)
|
|
# check scale
|
|
and (
|
|
mem.scale == i_mem.scale
|
|
or i_mem.scale == self.WILDCARD
|
|
or (mem.scale != 1 and i_mem.scale != 1)
|
|
)
|
|
# check pre-indexing
|
|
and (i_mem.pre_indexed == self.WILDCARD or mem.pre_indexed == i_mem.pre_indexed)
|
|
# check post-indexing
|
|
and (
|
|
i_mem.post_indexed == self.WILDCARD
|
|
or mem.post_indexed == i_mem.post_indexed
|
|
or (isinstance(mem.post_indexed, dict) and i_mem.post_indexed)
|
|
)
|
|
):
|
|
return True
|
|
return False
|
|
|
|
def _is_x86_mem_type(self, i_mem, mem):
|
|
"""Check if memory addressing type match."""
|
|
if (
|
|
# check base
|
|
(
|
|
(mem.base is None and i_mem.base is None)
|
|
or i_mem.base == self.WILDCARD
|
|
or self._is_x86_reg_type(i_mem.base, mem.base)
|
|
)
|
|
# check offset
|
|
and (
|
|
mem.offset == i_mem.offset
|
|
or i_mem.offset == self.WILDCARD
|
|
or (
|
|
mem.offset is not None
|
|
and isinstance(mem.offset, IdentifierOperand)
|
|
and isinstance(i_mem.offset, IdentifierOperand)
|
|
)
|
|
or (
|
|
mem.offset is not None
|
|
and isinstance(mem.offset, ImmediateOperand)
|
|
and (
|
|
i_mem.offset == "imd" or (i_mem.offset is None and mem.offset.value == "0")
|
|
)
|
|
)
|
|
or (isinstance(mem.offset, IdentifierOperand) and i_mem.offset == "id")
|
|
)
|
|
# check index
|
|
and (
|
|
mem.index == i_mem.index
|
|
or i_mem.index == self.WILDCARD
|
|
or (
|
|
mem.index is not None
|
|
# and mem.index.name != None
|
|
and self._is_x86_reg_type(i_mem.index, mem.index)
|
|
)
|
|
)
|
|
# check scale
|
|
and (
|
|
mem.scale == i_mem.scale
|
|
or i_mem.scale == self.WILDCARD
|
|
or (mem.scale != 1 and i_mem.scale != 1)
|
|
)
|
|
):
|
|
return True
|
|
return False
|
|
|
|
def _create_yaml_object(self):
|
|
"""Create YAML object for parsing and dumping DB"""
|
|
yaml_obj = ruamel.yaml.YAML()
|
|
yaml_obj.representer.add_representer(type(None), self.__represent_none)
|
|
yaml_obj.default_flow_style = None
|
|
yaml_obj.width = 120
|
|
yaml_obj.representer.ignore_aliases = lambda *args: True
|
|
return yaml_obj
|
|
|
|
def __represent_none(self, yaml_obj, data):
|
|
"""YAML representation for `None`"""
|
|
return yaml_obj.represent_scalar("tag:yaml.org,2002:null", "~")
|