mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2026-01-07 11:40:06 +01:00
766 lines
30 KiB
Python
Executable File
766 lines
30 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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import sys
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import os
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import io
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import re
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import subprocess
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from datetime import datetime
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import pandas as pd
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import numpy as np
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from osaca.param import Register, MemAddr, Parameter
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from osaca.eu_sched import Scheduler
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from osaca.testcase import Testcase
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DATA_DIR = os.path.expanduser('~') + '/.osaca/'
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def flatten(l):
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"""
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Flatten a nested list of strings.
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Parameters
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----------
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l : [[...[str]]]
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Nested list of strings
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Returns
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-------
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[str]
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List of strings
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"""
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if not l:
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return l
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if isinstance(l[0], list):
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return flatten(l[0]) + flatten(l[1:])
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return l[:1] + flatten(l[1:])
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def get_assembly_from_binary(file_path):
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"""
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Load binary file compiled with '-g' in class attribute srcCode and
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separate by line.
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"""
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return subprocess.run(['objdump', '--source', file_path],
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stdout=subprocess.PIPE,
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stderr=subprocess.PIPE).stdout.decode('utf-8').split('\n')
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class OSACA(object):
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srcCode = None
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tp_list = False
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# Variables for checking lines
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numSeps = 0
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indentChar = ''
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sem = 0
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# Variables for creating output
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longestInstr = 30
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machine_readable = False
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# Constants
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ASM_LINE = re.compile(r'\s[0-9a-f]+[:]')
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# Matches every variation of the IACA start marker
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IACA_SM = re.compile(r'\s*movl[ \t]+\$111[ \t]*,[ \t]*%ebx.*\n\s*\.byte[ \t]+100.*'
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r'((,[ \t]*103.*((,[ \t]*144)|(\n\s*\.byte[ \t]+144)))|(\n\s*\.byte'
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r'[ \t]+103.*((,[ \t]*144)|(\n\s*\.byte[ \t]+144))))')
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# Matches every variation of the IACA end marker
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IACA_EM = re.compile(r'\s*movl[ \t]+\$222[ \t]*,[ \t]*%ebx.*\n\s*\.byte[ \t]+100.*'
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r'((,[ \t]*103.*((,[ \t]*144)|(\n\s*\.byte[ \t]+144)))|(\n\s*\.byte'
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r'[ \t]+103.*((,[ \t]*144)|(\n\s*\.byte[ \t]+144))))')
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VALID_ARCHS = ['SNB', 'IVB', 'HSW', 'BDW', 'SKL', 'ZEN']
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def __init__(self, arch, file_path, output=sys.stdout):
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# Check architecture
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if arch not in self.VALID_ARCHS:
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raise ValueError("Invalid architecture ({!r}), must be one of {}.".format(
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arch, self.VALID_ARCHS))
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self.arch = arch
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self.file_path = file_path
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self.instr_forms = []
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self.file_output = output
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# Check if data files are already in usr dir, otherwise create them
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if not os.path.isdir(os.path.join(DATA_DIR, 'data')):
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print('Copying files in user directory...', file=self.file_output, end='')
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os.makedirs(os.path.join(DATA_DIR, 'data'))
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subprocess.call(['cp', '-r',
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'/'.join(os.path.realpath(__file__).split('/')[:-1]) + '/data',
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DATA_DIR])
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print(' Done!', file=self.file_output)
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# Check for database for the chosen architecture
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self.df = self.read_csv()
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# -----------------main functions depending on arguments--------------------
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def include_ibench(self):
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"""
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Read ibench output and include it in the architecture specific csv file.
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"""
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if not self.check_file():
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print('Invalid file path or file format.', file=sys.stderr)
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sys.exit(1)
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# Create sequence of numbers and their reciprocals for validate the measurements
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cyc_list, reci_list = self.create_sequences()
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# print('Everything seems fine! Let\'s start!', file=self.file_output)
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new_data = []
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added_vals = 0
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for line in self.srcCode:
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if 'Using frequency' in line or len(line) == 0:
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continue
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column = 'LT'
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instr = line.split()[0][:-1]
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if 'TP' in line:
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# We found a command with a throughput value. Get instruction and the number of
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# clock cycles and remove the '-TP' suffix.
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column = 'TP'
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instr = instr[:-3]
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# Otherwise it is a latency value. Nothing to do.
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clk_cyc = float(line.split()[1])
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clk_cyc_tmp = clk_cyc
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clk_cyc = self.validate_val(clk_cyc, instr, True if (column == 'TP') else False,
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cyc_list, reci_list)
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txt_output = (clk_cyc_tmp == clk_cyc)
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val = -2
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new = False
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try:
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entry = self.df.loc[lambda df, inst=instr: df.instr == inst, column]
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val = entry.values[0]
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# If val is -1 (= not filled with a valid value) add it immediately
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if val == -1:
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self.df.set_value(entry.index[0], column, clk_cyc)
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added_vals += 1
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continue
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except IndexError:
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# Instruction not in database yet --> add it
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new = True
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# First check if LT or TP value has already been added before
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for i, item in enumerate(new_data):
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if instr in item:
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if column == 'TP':
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new_data[i][1] = clk_cyc
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elif column == 'LT':
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new_data[i][2] = clk_cyc
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new = False
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break
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if new and column == 'TP':
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new_data.append([instr, clk_cyc, '-1', (-1,)])
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elif new and column == 'LT':
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new_data.append([instr, '-1', clk_cyc, (-1,)])
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new = True
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added_vals += 1
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if not new and abs((val / np.float64(clk_cyc)) - 1) > 0.05:
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print('Different measurement for {} ({}): {}(old) vs. '.format(instr, column, val)
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+ '{}(new)\nPlease check for correctness '.format(clk_cyc)
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+ '(no changes were made).', file=self.file_output)
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txt_output = True
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if txt_output:
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print('', file=self.file_output)
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# Now merge the DataFrames and write new csv file
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self.df = self.df.append(pd.DataFrame(new_data, columns=['instr', 'TP', 'LT', 'ports']),
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ignore_index=True)
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self.write_csv()
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print('ibench output included successfully in data file .', file=self.file_output)
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print('{} values were added.'.format(added_vals), file=self.file_output)
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def check_elffile(self):
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"""
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Check if the format is elf64 and then load into srcCode
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:return: true if file could be loaded and is an elf64 file
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"""
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# FIXME remove this workaround when restructuring is complete
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srcCode = get_assembly_from_binary(self.file_path)
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if len(srcCode) > 2 and 'file format elf64' in srcCode[1].lower():
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self.srcCode = srcCode
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return True
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return False
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def inspect_binary(self):
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"""
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Main function of OSACA. Inspect binary file and create analysis.
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"""
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# Check args and exit program if something's wrong
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if not self.check_elffile():
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print('Invalid file path or file format. Not an ELF file.', file=sys.stderr)
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sys.exit(1)
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# print('Everything seems fine! Let\'s start checking!', file=self.file_output)
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for i, line in enumerate(self.srcCode):
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if i == 0:
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self.check_line(line, True)
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else:
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self.check_line(line)
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output = self.create_output(self.tp_list, True, self.machine_readable)
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if self.machine_readable:
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return output
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else:
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print(output, file=self.file_output)
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def inspect_with_iaca(self):
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"""
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Main function of OSACA with IACA markers instead of OSACA marker.
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Inspect binary file and create analysis.
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"""
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# Check if input file is a binary or assembly file
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binary_file = True
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if not self.check_elffile():
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binary_file = False
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if not self.check_file(True):
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print('Invalid file path or file format.', file=sys.stderr)
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sys.exit(1)
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# print('Everything seems fine! Let\'s start checking!', file=self.file_output)
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if binary_file:
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self.iaca_bin()
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else:
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self.iaca_asm()
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output = self.create_output(self.tp_list, True, self.machine_readable)
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if self.machine_readable:
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return output
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else:
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print(output, file=self.file_output)
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# --------------------------------------------------------------------------
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def check_file(self, iaca_flag=False):
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"""
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Check if the given filepath exists and store file data in attribute
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srcCode.
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Parameters
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----------
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iaca_flag : bool
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store file data as a string in attribute srcCode if True,
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store it as a list of strings (lines) if False (default False)
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Returns
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-------
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bool
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True if file exists
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False if file does not exist
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"""
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if os.path.isfile(self.file_path):
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self.store_src_code(iaca_flag)
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return True
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return False
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def store_src_code(self, iaca_flag=False):
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"""
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Load arbitrary file in class attribute srcCode.
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Parameters
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----------
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iaca_flag : bool
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store file data as a string in attribute srcCode if True,
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store it as a list of strings (lines) if False (default False)
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"""
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with open(self.file_path, 'r') as f:
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self.srcCode = f.read()
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if iaca_flag:
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return
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self.srcCode = self.srcCode.split('\n')
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def read_csv(self):
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"""
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Read architecture dependent CSV from data directory.
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Returns
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-------
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DataFrame
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CSV as DataFrame object
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"""
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# curr_dir = '/'.join(os.path.realpath(__file__).split('/')[:-1])
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return pd.read_csv(DATA_DIR + 'data/' + self.arch.lower() + '_data.csv')
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def write_csv(self):
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"""
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Write architecture DataFrame as CSV into data directory.
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"""
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# curr_dir = '/'.join(os.path.realpath(__file__).split('/')[:-1])
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csv = self.df.to_csv(index=False)
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with open(DATA_DIR + 'data/' + self.arch.lower() + '_data.csv', 'w') as f:
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f.write(csv)
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def create_sequences(self, end=101):
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"""
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Create list of integers from 1 to end and list of their reciprocals.
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Parameters
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----------
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end : int
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End value for list of integers (default 101)
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Returns
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-------
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[int]
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cyc_list of integers
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[float]
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reci_list of floats
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"""
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cyc_list = []
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reci_list = []
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for i in range(1, end):
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cyc_list.append(i)
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reci_list.append(1 / i)
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return cyc_list, reci_list
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def validate_val(self, clk_cyc, instr, is_tp, cyc_list, reci_list):
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"""
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Validate given clock cycle clk_cyc and return rounded value in case of
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success.
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A succeeded validation means the clock cycle clk_cyc is only 5% higher or
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lower than an integer value from cyc_list or - if clk_cyc is a throughput
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value - 5% higher or lower than a reciprocal from the reci_list.
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Parameters
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----------
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clk_cyc : float
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Clock cycle to validate
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instr : str
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Instruction for warning output
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is_tp : bool
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True if a throughput value is to check, False for a latency value
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cyc_list : [int]
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Cycle list for validating
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reci_list : [float]
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Reciprocal cycle list for validating
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Returns
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-------
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float
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Clock cycle, either rounded to an integer or its reciprocal or the
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given clk_cyc parameter
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"""
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column = 'LT'
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if is_tp:
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column = 'TP'
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for i in range(0, len(cyc_list)):
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if cyc_list[i] * 1.05 > float(clk_cyc) > cyc_list[i] * 0.95:
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# Value is probably correct, so round it to the estimated value
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return cyc_list[i]
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# Check reciprocal only if it is a throughput value
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elif is_tp and reci_list[i] * 1.05 > float(clk_cyc) > reci_list[i] * 0.95:
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# Value is probably correct, so round it to the estimated value
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return reci_list[i]
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# No value close to an integer or its reciprocal found, we assume the
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# measurement is incorrect
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print('Your measurement for {} ({}) is probably wrong. '.format(instr, column)
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+ 'Please inspect your benchmark!', file=self.file_output)
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print('The program will continue with the given value', file=self.file_output)
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return clk_cyc
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def iaca_bin(self):
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"""
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Extract instruction forms out of binary file using IACA markers.
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"""
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self.CODE_MARKER = r'fs addr32 nop'
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part1 = re.compile(r'64\s+fs')
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part2 = re.compile(r'67 90\s+addr32 nop')
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for line in self.srcCode:
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# Check if marker is in line
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if self.CODE_MARKER in line:
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self.sem += 1
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elif re.search(part1, line) or re.search(part2, line):
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self.sem += 0.5
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elif self.sem == 1:
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# We're in the marked code snippet
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# Check if the line is ASM code
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match = re.search(self.ASM_LINE, line)
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if match:
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# Further analysis of instructions
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# Check if there are comments in line
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if r'//' in line:
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continue
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# Do the same instruction check as for the OSACA marker line check
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self.check_instr(''.join(re.split(r'\t', line)[-1:]))
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elif self.sem == 2:
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# Not in the loop anymore. Due to the fact it's the IACA marker we can stop here
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# After removing the last line which belongs to the IACA marker
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del self.instr_forms[-1:]
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# if(is_2_lines):
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# The marker is splitted into two lines, therefore delete another line
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# del self.instr_forms[-1:]
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return
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def iaca_asm(self):
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"""
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Extract instruction forms out of assembly file using IACA markers.
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"""
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# Extract the code snippet surround by the IACA markers
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code = self.srcCode
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# Search for the start marker
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match = re.match(self.IACA_SM, code)
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while not match:
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code = code.split('\n', 1)
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if len(code) > 1:
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code = code[1]
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else:
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raise ValueError("No IACA-style markers found in assembly code.")
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match = re.match(self.IACA_SM, code)
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# Search for the end marker
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code = (code.split('144', 1)[1]).split('\n', 1)[1]
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res = ''
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match = re.match(self.IACA_EM, code)
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while not match:
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res += code.split('\n', 1)[0] + '\n'
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code = code.split('\n', 1)[1]
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match = re.match(self.IACA_EM, code)
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# Split the result by line go on like with OSACA markers
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res = res.split('\n')
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for line in res:
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line = line.split('#')[0]
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line = line.lstrip()
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if len(line) == 0 or '//' in line or line.startswith('..'):
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continue
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self.check_instr(line)
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def check_instr(self, instr):
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"""
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Inspect instruction for its parameters and add it to the instruction forms
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pool instr_form.
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Parameters
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----------
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instr : str
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Instruction as string
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"""
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# Check for strange clang padding bytes
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while instr.startswith('data32'):
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instr = instr[7:]
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# Separate mnemonic and operands
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mnemonic = instr.split()[0]
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params = ''.join(instr.split()[1:])
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# Check if line is not only a byte
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empty_byte = re.compile(r'[0-9a-f]{2}')
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if re.match(empty_byte, mnemonic) and len(mnemonic) == 2:
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return
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# Check if there's one or more operands and store all in a list
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param_list = flatten(self._separate_params(params))
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param_list_types = list(param_list)
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# Check operands and separate them by IMMEDIATE (IMD), REGISTER (REG),
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# MEMORY (MEM) or LABEL(LBL)
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for i in range(len(param_list)):
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op = param_list[i]
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if len(op) <= 0:
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op = Parameter('NONE')
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elif op[0] == '$':
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op = Parameter('IMD')
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elif op[0] == '%' and '(' not in op:
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j = len(op)
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opmask = False
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if '{' in op:
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j = op.index('{')
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opmask = True
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op = Register(op[1:j], opmask)
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elif '<' in op or op.startswith('.'):
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op = Parameter('LBL')
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else:
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op = MemAddr(op, )
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param_list[i] = str(op)
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param_list_types[i] = op
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# Add to list
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instr = instr.rstrip()
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if len(instr) > self.longestInstr:
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self.longestInstr = len(instr)
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instr_form = [mnemonic] + list(reversed(param_list_types)) + [instr]
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self.instr_forms.append(instr_form)
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# If flag is set, create testcase for instruction form
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# Do this in reversed param list order, du to the fact it's intel syntax
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# Only create benchmark if no label (LBL) is part of the operands
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if 'LBL' in param_list or '' in param_list:
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return
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tc = Testcase(mnemonic, list(reversed(param_list_types)), '32')
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# Only write a testcase if it not already exists or already in data file
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writeTP, writeLT = tc.is_in_dir()
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inDB = len(self.df.loc[lambda df: df.instr == tc.get_entryname()])
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if inDB == 0:
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tc.write_testcase(not writeTP, not writeLT)
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def _separate_params(self, params):
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"""
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Delete comments, separates parameters and return them as a list.
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Parameters
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----------
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params : str
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Splitted line after mnemonic
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Returns
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|
-------
|
|
[[...[str]]]
|
|
Nested list of strings. The number of nest levels depend on the
|
|
number of parametes given.
|
|
"""
|
|
param_list = [params]
|
|
if ',' in params:
|
|
if ')' in params:
|
|
if params.index(')') < len(params) - 1 and params[params.index(')') + 1] == ',':
|
|
i = params.index(')') + 1
|
|
elif params.index('(') < params.index(','):
|
|
return param_list
|
|
else:
|
|
i = params.index(',')
|
|
else:
|
|
i = params.index(',')
|
|
param_list = [params[:i], self._separate_params(params[i + 1:])]
|
|
elif '#' in params:
|
|
i = params.index('#')
|
|
param_list = [params[:i]]
|
|
return param_list
|
|
|
|
def create_output(self, tp_list=False, pr_sched=True, machine_readable=False):
|
|
"""
|
|
Creates output of analysed file including a time stamp.
|
|
|
|
Parameters
|
|
----------
|
|
tp_list : bool
|
|
Boolean for indicating the need for the throughput list as output
|
|
(default False)
|
|
pr_sched : bool
|
|
Boolean for indicating the need for predicting a scheduling
|
|
(default True)
|
|
|
|
Returns
|
|
-------
|
|
str
|
|
OSACA output
|
|
"""
|
|
# Check the output alignment depending on the longest instruction
|
|
if self.longestInstr > 70:
|
|
self.longestInstr = 70
|
|
horiz_line = self.create_horiz_sep()
|
|
# Write general information about the benchmark
|
|
output = '--{}\n| Architecture:\t\t{}\n|\n'.format(
|
|
horiz_line, self.arch)
|
|
if tp_list:
|
|
output += self.create_tp_list(horiz_line)
|
|
if pr_sched:
|
|
output += '\n\n'
|
|
sched = Scheduler(self.arch, self.instr_forms)
|
|
sched_output, port_binding = sched.new_schedule(machine_readable)
|
|
# if machine_readable, we're already done here
|
|
if machine_readable:
|
|
return sched_output
|
|
binding = sched.get_port_binding(port_binding)
|
|
output += sched.get_report_info() + '\n' + binding + '\n\n' + sched_output
|
|
block_tp = round(max(port_binding), 2)
|
|
output += 'Total number of estimated throughput: ' + str(block_tp)
|
|
return output
|
|
|
|
def create_horiz_sep(self):
|
|
"""
|
|
Calculate and return horizontal separator line.
|
|
|
|
Returns
|
|
-------
|
|
str
|
|
Horizontal separator line
|
|
"""
|
|
return '-' * (self.longestInstr + 8)
|
|
|
|
def create_tp_list(self, horiz_line):
|
|
"""
|
|
Create list of instruction forms with the proper throughput value.
|
|
|
|
Parameter
|
|
---------
|
|
horiz_line : str
|
|
Calculated horizontal line for nice alignement
|
|
|
|
Returns
|
|
-------
|
|
str
|
|
Throughput list output for printing
|
|
"""
|
|
warning = False
|
|
ws = ' ' * (len(horiz_line) - 23)
|
|
|
|
output = '\n| INSTRUCTION{}CLOCK CYCLES\n| {}\n|\n'.format(ws, horiz_line)
|
|
# Check for the throughput data in CSV
|
|
for elem in self.instr_forms:
|
|
op_ext = []
|
|
for i in range(1, len(elem) - 1):
|
|
if isinstance(elem[i], Register) and elem[i].reg_type == 'GPR':
|
|
optmp = 'r' + str(elem[i].size)
|
|
elif isinstance(elem[i], MemAddr):
|
|
optmp = 'mem'
|
|
else:
|
|
optmp = str(elem[i]).lower()
|
|
op_ext.append(optmp)
|
|
operands = '_'.join(op_ext)
|
|
# Now look up the value in the dataframe
|
|
# Check if there is a stored throughput value in database
|
|
import warnings
|
|
warnings.filterwarnings("ignore", 'This pattern has match groups')
|
|
series = self.df['instr'].str.contains(elem[0] + '-' + operands)
|
|
if True in series.values:
|
|
# It's a match!
|
|
not_found = False
|
|
try:
|
|
tp = self.df[self.df.instr == elem[0] + '-' + operands].TP.values[0]
|
|
except IndexError:
|
|
# Something went wrong
|
|
print('Error while fetching data from data file', file=self.file_output)
|
|
continue
|
|
# Did not found the exact instruction form.
|
|
# Try to find the instruction form for register operands only
|
|
else:
|
|
op_ext_regs = []
|
|
for operand in op_ext:
|
|
try:
|
|
# regTmp = Register(operand)
|
|
# Create Register only to see if it is one
|
|
Register(operand)
|
|
op_ext_regs.append(True)
|
|
except KeyError:
|
|
op_ext_regs.append(False)
|
|
if True not in op_ext_regs:
|
|
# No register in whole instr form. How can I find out what regsize we need?
|
|
print('Feature not included yet: ', end='', file=self.file_output)
|
|
print(elem[0] + ' for ' + operands, file=self.file_output)
|
|
tp = 0
|
|
warning = True
|
|
num_whitespaces = self.longestInstr - len(elem[-1])
|
|
ws = ' ' * num_whitespaces + '| '
|
|
n_f = ' ' * (5 - len(str(tp))) + '*'
|
|
data = '| ' + elem[-1] + ws + str(tp) + n_f + '\n'
|
|
output += data
|
|
continue
|
|
if op_ext_regs[0] is False:
|
|
# Instruction stores result in memory. Check for storing in register instead.
|
|
if len(op_ext) > 1:
|
|
if op_ext_regs[1] is True:
|
|
op_ext[0] = op_ext[1]
|
|
elif len(op_ext) > 2:
|
|
if op_ext_regs[2] is True:
|
|
op_ext[0] = op_ext[2]
|
|
if len(op_ext_regs) == 2 and op_ext_regs[1] is False:
|
|
# Instruction loads value from memory and has only two operands. Check for
|
|
# loading from register instead
|
|
if op_ext_regs[0] is True:
|
|
op_ext[1] = op_ext[0]
|
|
if len(op_ext_regs) == 3 and op_ext_regs[2] is False:
|
|
# Instruction loads value from memory and has three operands. Check for loading
|
|
# from register instead
|
|
op_ext[2] = op_ext[0]
|
|
operands = '_'.join(op_ext)
|
|
# Check for register equivalent instruction
|
|
series = self.df['instr'].str.contains(elem[0] + '-' + operands)
|
|
if True in series.values:
|
|
# It's a match!
|
|
not_found = False
|
|
try:
|
|
tp = self.df[self.df.instr == elem[0] + '-' + operands].TP.values[0]
|
|
except IndexError:
|
|
# Something went wrong
|
|
print('Error while fetching data from data file', file=self.file_output)
|
|
continue
|
|
# Did not found the register instruction form. Set warning and go on with
|
|
# throughput 0
|
|
else:
|
|
tp = 0
|
|
not_found = True
|
|
warning = True
|
|
# Check the alignement again
|
|
num_whitespaces = self.longestInstr - len(elem[-1])
|
|
ws = ' ' * num_whitespaces + '| '
|
|
n_f = ''
|
|
if not_found:
|
|
n_f = ' ' * (5 - len(str(tp))) + '*'
|
|
data = '| ' + elem[-1] + ws + '{:3.2f}'.format(tp) + n_f + '\n'
|
|
output += data
|
|
# Finally end the list of throughput values
|
|
output += '| ' + horiz_line + '\n'
|
|
if warning:
|
|
output += ('\n\n* There was no throughput value found for the specific instruction '
|
|
'form.\n Please create a testcase via the create_testcase-method or add a '
|
|
'value manually.')
|
|
return output
|
|
|
|
|
|
# ------------------------------------------------------------------------------
|
|
# Stolen from pip
|
|
def __read(*names, **kwargs):
|
|
with io.open(
|
|
os.path.join(os.path.dirname(__file__), *names),
|
|
encoding=kwargs.get("encoding", "utf8")
|
|
) as fp:
|
|
return fp.read()
|
|
|
|
|
|
# Stolen from pip
|
|
def __find_version(*file_paths):
|
|
version_file = __read(*file_paths)
|
|
version_match = re.search(r"^__version__ = ['\"]([^'\"]*)['\"]", version_file, re.M)
|
|
if version_match:
|
|
return version_match.group(1)
|
|
raise RuntimeError('Unable to find version string.')
|
|
|
|
|
|
# ------------Main method--------------
|
|
def main():
|
|
# Parse args
|
|
parser = argparse.ArgumentParser(description='Analyzes a marked innermost loop snippet'
|
|
'for a given architecture type and prints out the '
|
|
'estimated average throughput.')
|
|
parser.add_argument('-V', '--version', action='version',
|
|
version='%(prog)s ' + __find_version('__init__.py'))
|
|
parser.add_argument('--arch', type=str, required=True,
|
|
help='define architecture (SNB, IVB, HSW, BDW, SKL, ZEN)')
|
|
parser.add_argument('--tp-list', action='store_true',
|
|
help='print an additional list of all throughput values for the kernel')
|
|
group = parser.add_mutually_exclusive_group(required=False)
|
|
group.add_argument('-i', '--include-ibench', action='store_true',
|
|
help='includes the given values in form of the output of ibench in the'
|
|
'data file')
|
|
group.add_argument('--insert-marker', '-m', action='store_true',
|
|
help='try to find blocks probably corresponding to loops in assembly and'
|
|
'insert IACA marker')
|
|
parser.add_argument('-l', '--list-output', dest='machine_readable', action='store_true',
|
|
help='returns output as machine readable list of lists')
|
|
parser.add_argument('filepath', type=str, help='path to object (Binary, ASM, CSV)')
|
|
|
|
# Store args in global variables
|
|
args = parser.parse_args()
|
|
|
|
# Create OSACA object
|
|
osaca = OSACA(args.arch.upper(), args.filepath)
|
|
if args.tp_list:
|
|
osaca.tp_list = True
|
|
if args.machine_readable:
|
|
osaca.machine_readable = True
|
|
osaca.output = None
|
|
|
|
if args.include_ibench:
|
|
osaca.include_ibench()
|
|
elif args.insert_marker:
|
|
try:
|
|
from kerncraft import iaca
|
|
except ImportError:
|
|
print("ImportError: Module kerncraft not installed. Use 'pip install --user "
|
|
"kerncraft' for installation.\nFor more information see "
|
|
"https://github.com/RRZE-HPC/kerncraft", file=sys.stderr)
|
|
sys.exit(1)
|
|
# Change due to newer kerncraft version (hopefully temporary)
|
|
# iaca.iaca_instrumentation(input_file=filepath, output_file=filepath,
|
|
# block_selection='manual', pointer_increment=1)
|
|
with open(args.filepath, 'r') as f_in, open(args.filepath[:-2] + '-iaca.s', 'w') as f_out:
|
|
iaca.iaca_instrumentation(input_file=f_in, output_file=f_out,
|
|
block_selection='manual', pointer_increment=1)
|
|
else:
|
|
return osaca.inspect_with_iaca()
|
|
|
|
|
|
# ------------Main method--------------
|
|
if __name__ == '__main__':
|
|
main()
|