mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2025-12-16 00:50:06 +01:00
5492 lines
239 KiB
YAML
5492 lines
239 KiB
YAML
osaca_version: 0.5.3
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micro_architecture: AMD Zen4
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arch_code: ZEN4
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isa: x86
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ROB_size: 320
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dispatched_uops_per_cycle: 6
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retired_uOps_per_cycle: ~
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scheduler_size: ~
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hidden_loads: false
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load_latency: {gpr: 4.0, mm: 4.0, xmm: 4.0, ymm: 4.0, zmm: 4.0}
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load_throughput:
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- {dst: gpr, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '135'], [1, ['1D', '3D', '5D']]]}
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- {dst: xmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '135'], [1, ['1D', '3D']]]}
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- {dst: ymm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, '135'], [1, ['1D', '3D']]]}
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- {dst: zmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[2, '135'], [2, ['1D', '3D']]]}
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load_throughput_default: [[1, '135'], [1, ['1D', '3D']]]
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store_throughput:
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- {src: gpr, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['1', '3']], [1, ['8', '13']]]}
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- {src: xmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['1', '3']], [1, ['13']]]}
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- {src: ymm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[1, ['1', '3']], [1, ['13']]]}
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- {src: zmm, base: "*", index: "*", offset: "*", scale: "*", port_pressure: [[2, ['1', '3']], [2, ['13']]]}
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store_throughput_default: [[1 , ['1', '3']], [1, ['13']]]
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store_to_load_forward_latency: 0.0
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ports: ['0', '1', 1D, '2', '3', 3D, '4', 4DV, '5', 5D, '6', '7', '8', '9', 9DV, '10', '11', 11DV, '12', '13']
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port_model_scheme: |
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+--------------------------------------------------------------+ +-------------------------------------------------------+
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| INT0-7 4x24 OoO scheduler | |2x32 FP0 FP2 FP1 FP3 |
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+--------------------------------------------------------------+ +-------------------------------------------------------+
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0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 |
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\/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/
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+------+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +------+ +-------+ +-------+ +-------+ +-------+ +------+
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| ALU | | AGU | | ALU | | AGU | | ALU | | AGU | | ALU | | BR | | iST | |AVX MUL| |AVX ALU| |AVX MUL| |AVX ALU| | ST |
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+------+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +------+ +-------+ +-------+ +-------+ +-------+ +------+
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+------+ +-----+ +-----+ +-----+ +-----+ +-----+ +------+ +-------+ +-------+ +-------+ +-------+
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|BRANCH| | LD | | SHF | | LD | | SHF | | iLD | | F2I | |AVX FMA| |AVX ADD| |AVX FMA| |AVX ADD|
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+------+ +-----+ +-----+ +-----+ +-----+ +-----+ +------+ +-------+ +-------+ +-------+ +-------+
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//MUL //DIV +-------+ +-------+ +-------+ +-------+
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| DIV | | CONV/ | | DIV | | AVX |
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+-------+ | SHUF | +-------+ | SHUF |
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+-------+ +-------+ +-------+
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| AVX | | AVX |
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| SHUF | | SHUF |
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+-------+ +-------+
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instruction_forms:
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##########################################
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# assume all jmp instruction 0
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- name: [jo, jno, js, jns, jp, jpe, jnp, jpo]
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operands:
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- class: identifier
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throughput: 0.0
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latency: 0.0
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port_pressure: []
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- name: [jc, jb, jae, jnb, jna, jbe, ja, jnbe]
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operands:
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- class: identifier
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throughput: 0.0
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latency: 0.0
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port_pressure: []
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- name: [je, jz, jne, jnz, jl, jnge]
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operands:
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- class: identifier
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throughput: 0.0
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latency: 0.0
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port_pressure: []
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- name: [jge, jnl, jle, jng, jg, jnle]
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operands:
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- class: identifier
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throughput: 0.0
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latency: 0.0
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port_pressure: []
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- name: jmp
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operands:
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- class: identifier
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throughput: 0.0
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latency: 0.0
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port_pressure: []
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##########################################
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# assume all cmp's equal for now
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# TODO add cmp instructions
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- name: [cmp, cmpeqpd, cmpltpd, cmplepd, cmpunordpd, cmpneqpd, cmpnltpd, cmpnlepd, cmpordpd, cmpltps, cmpleps, cmpunordps, cmpneqps, cmpnltps, cmpnleps, cmpordps]
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operands:
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- class: register
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name: '*'
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- class: register
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name: '*'
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latency: 1.0
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port_pressure: [[1, '0246']]
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throughput: 0.25
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uops: 1
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- name: [cmp, cmpeqpd, cmpltpd, cmplepd, cmpunordpd, cmpneqpd, cmpnltpd, cmpnlepd, cmpordpd, cmpltps, cmpleps, cmpunordps, cmpneqps, cmpnltps, cmpnleps, cmpordps]
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operands:
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- class: immediate
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imd: int
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- class: register
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name: '*'
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latency: 1.0
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port_pressure: [[1, '0246']]
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throughput: 0.25
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uops: 1
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##########################################
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- name: push
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operands:
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- class: immediate
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imd: int
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latency: 0
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port_pressure: [[1, ['1', '3']], [1, ['8', '13']]]
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throughput: 0.5
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uops: 2
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- name: push
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operands:
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- class: register
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name: gpr
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latency: 11
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port_pressure: [[1, ['1', '3']], [1, ['8', '13']]]
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throughput: 0.5
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uops: 2
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- name: push
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operands:
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- class: memory
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base: "*"
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offset: "*"
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index: "*"
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scale: "*"
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latency: 11
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port_pressure: [[1, ['1', '3']], [1, ['8', '13']]]
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throughput: 0.5
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uops: 2
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- name: pop
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operands:
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- class: immediate
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imd: int
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latency: 4
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port_pressure: [[1, '135'], [1, ['1D', '3D', '5D']]]
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throughput: 0.3333333333333333
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uops: 1
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- name: pop
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operands:
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- class: register
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name: gpr
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latency: 4
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port_pressure: [[1, '135'], [1, ['1D', '3D', '5D']]]
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throughput: 0.3333333333333333
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uops: 1
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- name: pop
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operands:
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- class: memory
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base: "*"
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offset: "*"
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index: "*"
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scale: "*"
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latency: 12
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port_pressure: [[1, '135'], [1, ['1D', '3D', '5D']]]
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throughput: 0.3333333333333333
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uops: 2
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##########################################
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- name: mov
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operands:
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- class: register
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name: gpr
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- class: register
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name: gpr
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latency: 0
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port_pressure: [[1, '0246']]
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throughput: 0.25
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uops: 1.0
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- name: mov # with store
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operands:
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- class: register
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name: gpr
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- class: memory
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base: "*"
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offset: "*"
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index: "*"
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scale: "*"
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latency: 0
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port_pressure: [[1, '135'], [1, ['8', '13']]]
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throughput: 0.5
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uops: 2
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- name: mov # with load
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operands:
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- class: memory
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base: "*"
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offset: "*"
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index: "*"
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scale: "*"
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- class: register
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name: gpr
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latency: 4
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port_pressure: [[1, '135'], [1, ['1D', '3D', '5D']]]
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throughput: 0.3333333333333333
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uops: 1
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- name: mov
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operands:
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- class: immediate
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imd: int
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- class: register
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name: gpr
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latency: 1
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port_pressure: [[1, '0246']]
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throughput: 0.25
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uops: 1.0
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- name: mov # with store
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operands:
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- class: immediate
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imd: int
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- class: memory
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base: "*"
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offset: "*"
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index: "*"
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scale: "*"
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latency: 0
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port_pressure: [[1 , ['1', '3']], [1, ['8', '13']]]
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throughput: 0.5
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uops: 2
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- name: movabs
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operands:
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- class: immediate
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imd: int
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- class: register
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name: gpr
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latency: 1
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port_pressure: [[1, '0246']]
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throughput: 0.25
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uops: 1.0
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- name: movapd
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operands:
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- class: register
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name: xmm
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- class: register
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name: xmm
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latency: 0
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port_pressure: [[1, ['9', '10', '11', '12']]]
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throughput: 0.25
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uops: 1.0
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- name: movapd # with store
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operands:
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- class: register
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name: xmm
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- class: memory
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base: "*"
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offset: "*"
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index: "*"
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scale: "*"
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latency: 0
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port_pressure: [[1 , ['1', '3']], [1, ['13']]]
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throughput: 0.5
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uops: 2
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- name: movapd # with load
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operands:
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- class: memory
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base: "*"
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offset: "*"
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index: "*"
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scale: "*"
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- class: register
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name: xmm
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latency: 4
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port_pressure: [[1, '135'], [1, ['1D', '3D']]]
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throughput: 0.5
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uops: 1
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- name: vmovapd
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operands:
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- class: register
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name: xmm
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- class: register
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name: xmm
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latency: 0
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port_pressure: [[1, ['9', '10', '11', '12']]]
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throughput: 0.25
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uops: 1.0
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- name: vmovapd # with store
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operands:
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- class: register
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name: xmm
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- class: memory
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base: "*"
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offset: "*"
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index: "*"
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scale: "*"
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latency: 0
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port_pressure: [[1 , ['1', '3']], [1, ['13']]]
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throughput: 0.5
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uops: 2
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- name: vmovapd # with load
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operands:
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- class: memory
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base: "*"
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offset: "*"
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index: "*"
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scale: "*"
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- class: register
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name: xmm
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latency: 4
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port_pressure: [[1, '135'], [1, ['1D', '3D']]]
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throughput: 0.5
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uops: 1
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- name: vmovapd
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operands:
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- class: register
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name: ymm
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- class: register
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name: ymm
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latency: 0
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port_pressure: [[1, ['9', '10', '11', '12']]]
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throughput: 0.25
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uops: 1.0
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- name: vmovapd # with store
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operands:
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- class: register
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name: ymm
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- class: memory
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base: "*"
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offset: "*"
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index: "*"
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scale: "*"
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latency: 0
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port_pressure: [[1 , ['1', '3']], [1, ['13']]]
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throughput: 0.5
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uops: 2
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- name: vmovapd # with load
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operands:
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- class: memory
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base: "*"
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offset: "*"
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index: "*"
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scale: "*"
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- class: register
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name: ymm
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latency: 4
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port_pressure: [[1, '135'], [1, ['1D', '3D']]]
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throughput: 0.5
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uops: 1
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- name: vmovapd
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operands:
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- class: register
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name: zmm
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- class: register
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name: zmm
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latency: 0
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port_pressure: [[1, ['9', '10', '11', '12']]]
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throughput: 0.25
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uops: 1.0
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- name: vmovapd # with store
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operands:
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- class: register
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name: zmm
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- class: memory
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base: "*"
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offset: "*"
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index: "*"
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scale: "*"
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latency: 0
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port_pressure: [[2 , ['1', '3']], [2, ['13']]]
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throughput: 2.0
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uops: 4
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- name: vmovapd # with load
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operands:
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- class: memory
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base: "*"
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offset: "*"
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index: "*"
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scale: "*"
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- class: register
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name: zmm
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latency: 4
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port_pressure: [[2, '135'], [2, ['1D', '3D']]]
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throughput: 1.0
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uops: 2
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- name: movaps
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operands:
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- class: register
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name: xmm
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- class: register
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name: xmm
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latency: 0
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port_pressure: [[1, ['9', '10', '11', '12']]]
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throughput: 0.25
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uops: 1.0
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- name: movaps # with store
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operands:
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- class: register
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name: xmm
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- class: memory
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base: "*"
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offset: "*"
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index: "*"
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scale: "*"
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latency: 0
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port_pressure: [[1 , ['1', '3']], [1, ['13']]]
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throughput: 0.5
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uops: 2
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- name: movaps # with load
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operands:
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- class: memory
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base: "*"
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offset: "*"
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index: "*"
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scale: "*"
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- class: register
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name: xmm
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latency: 4
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port_pressure: [[1, '135'], [1, ['1D', '3D']]]
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throughput: 0.5
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uops: 1
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- name: vmovaps
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operands:
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- class: register
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name: xmm
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- class: register
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name: xmm
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latency: 0
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port_pressure: [[1, ['9', '10', '11', '12']]]
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throughput: 0.25
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|
uops: 1.0
|
|
- name: vmovaps # with store
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|
operands:
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- class: register
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|
name: xmm
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|
- class: memory
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|
base: "*"
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offset: "*"
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|
index: "*"
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|
scale: "*"
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|
latency: 0
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|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
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throughput: 0.5
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|
uops: 2
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|
- name: vmovaps # with load
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|
operands:
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- class: memory
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|
base: "*"
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|
offset: "*"
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|
index: "*"
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|
scale: "*"
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|
- class: register
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|
name: xmm
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|
latency: 4
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|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
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throughput: 0.5
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|
uops: 1
|
|
- name: vmovaps
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|
operands:
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- class: register
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name: ymm
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- class: register
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|
name: ymm
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latency: 0
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port_pressure: [[1, ['9', '10', '11', '12']]]
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|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovaps # with store
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|
operands:
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|
- class: register
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|
name: ymm
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|
- class: memory
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|
base: "*"
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|
offset: "*"
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|
index: "*"
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|
scale: "*"
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|
latency: 0
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|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
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|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovaps # with load
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|
operands:
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|
- class: memory
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|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
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|
name: ymm
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|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovaps
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|
operands:
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- class: register
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|
name: zmm
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|
- class: register
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|
name: zmm
|
|
latency: 0
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|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
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throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovaps # with store
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|
operands:
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|
- class: register
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|
name: zmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[2 , ['1', '3']], [2, ['13']]]
|
|
throughput: 2.0
|
|
uops: 4
|
|
- name: vmovaps # with load
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|
operands:
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|
- class: memory
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|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: zmm
|
|
latency: 4
|
|
port_pressure: [[2, '135'], [2, ['1D', '3D']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: movdqa
|
|
operands:
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- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: movdqa # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: movdqa # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqa
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqa # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovdqa # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqa
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqa # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: ymm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovdqa # with store
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqa32
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqa32 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovdqa32 # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqa32
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqa32 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: ymm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovdqa32 # with store
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqa32
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqa32 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: zmm
|
|
latency: 4
|
|
port_pressure: [[2, '135'], [2, ['1D', '3D']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: vmovdqa32 # with store
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[2 , ['1', '3']], [2, ['13']]]
|
|
throughput: 2.0
|
|
uops: 4
|
|
- name: vmovdqa64
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqa64 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovdqa64 # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqa64
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqa64 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: ymm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovdqa64 # with store
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqa64
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqa64 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: zmm
|
|
latency: 4
|
|
port_pressure: [[2, '135'], [2, ['1D', '3D']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: vmovdqa64 # with store
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[2 , ['1', '3']], [2, ['13']]]
|
|
throughput: 2.0
|
|
uops: 4
|
|
- name: movdqu
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: movdqu # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: movdqu # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqu
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqu # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovdqu # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqu
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqu # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: ymm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovdqu # with store
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqu8
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqu8 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovdqu8 # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqu8
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqu8 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: ymm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovdqu8 # with store
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqu8
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqu8 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: zmm
|
|
latency: 4
|
|
port_pressure: [[2, '135'], [2, ['1D', '3D']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: vmovdqu8 # with store
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[2 , ['1', '3']], [2, ['13']]]
|
|
throughput: 2.0
|
|
uops: 4
|
|
- name: vmovdqu16
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqu16 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovdqu16 # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqu16
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqu16 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: ymm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovdqu16 # with store
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqu16
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqu16 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: zmm
|
|
latency: 4
|
|
port_pressure: [[2, '135'], [2, ['1D', '3D']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: vmovdqu16 # with store
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[2 , ['1', '3']], [2, ['13']]]
|
|
throughput: 2.0
|
|
uops: 4
|
|
- name: vmovdqu32
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqu32 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovdqu32 # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqu32
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqu32 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: ymm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovdqu32 # with store
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqu32
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqu32 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: zmm
|
|
latency: 4
|
|
port_pressure: [[2, '135'], [2, ['1D', '3D']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: vmovdqu32 # with store
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[2 , ['1', '3']], [2, ['13']]]
|
|
throughput: 2.0
|
|
uops: 4
|
|
- name: vmovdqu64
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqu64 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovdqu64 # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqu64
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqu64 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: ymm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovdqu64 # with store
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovdqu64
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovdqu64 # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: zmm
|
|
latency: 4
|
|
port_pressure: [[2, '135'], [2, ['1D', '3D']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: vmovdqu64 # with store
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[2 , ['1', '3']], [2, ['13']]]
|
|
throughput: 2.0
|
|
uops: 4
|
|
- name: movntdq # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovntdq # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovntdq # with store
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovntdq # with store
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[2 , ['1', '3']], [2, ['13']]]
|
|
throughput: 2.0
|
|
uops: 4
|
|
- name: movntdqa # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovntdqa # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovntdqa # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: ymm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovntdqa # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: zmm
|
|
latency: 4
|
|
port_pressure: [[2, '135'], [2, ['1D', '3D']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: movnti # with store
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['8', '13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: movntpd # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovntpd # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovntpd # with store
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovntpd # with store
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[2 , ['1', '3']], [2, ['13']]]
|
|
throughput: 2.0
|
|
uops: 4
|
|
- name: movntps # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovntps # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovntps # with store
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovntps # with store
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[2 , ['1', '3']], [2, ['13']]]
|
|
throughput: 2.0
|
|
uops: 4
|
|
- name: movntq # with store
|
|
operands:
|
|
- class: register
|
|
name: mm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: movq
|
|
operands:
|
|
- class: register
|
|
name: mm
|
|
- class: register
|
|
name: mm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1
|
|
- name: movq # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: mm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: movq # with store
|
|
operands:
|
|
- class: register
|
|
name: mm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: movq
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: movq # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: movq # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovq
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovq # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovq # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: movsd
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: movsd # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: movsd # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovsd
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovsd # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovsd # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: movss
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: movss # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovss
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovss # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovss
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovss # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: movss # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: movsx
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: gpr
|
|
latency: 0
|
|
port_pressure: [[1, '0246']]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: movsx # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: gpr
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D', '5D']]]
|
|
throughput: 0.333333333
|
|
uops: 1
|
|
- name: movsxd
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: gpr
|
|
latency: 0
|
|
port_pressure: [[1, '0246']]
|
|
throughput: 0.25
|
|
uops: 1
|
|
- name: movsxd # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: gpr
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D', '5D']]]
|
|
throughput: 0.3333333
|
|
uops: 1
|
|
- name: movsb
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: gpr
|
|
latency: 0
|
|
port_pressure: [[1, '0246']]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: movsb # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: gpr
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D', '5D']]]
|
|
throughput: 0.333333333333
|
|
uops: 1
|
|
- name: movsw
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: gpr
|
|
latency: 0
|
|
port_pressure: [[1, '0246']]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: movsw # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: gpr
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D', '5D']]]
|
|
throughput: 0.3333333333
|
|
uops: 1
|
|
- name: movsl
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: gpr
|
|
latency: 0
|
|
port_pressure: [[1, '0246']]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: movsl # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: gpr
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D', '5D']]]
|
|
throughput: 0.333333333
|
|
uops: 1
|
|
- name: movsq
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: gpr
|
|
latency: 0
|
|
port_pressure: [[1, '0246']]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: movsq # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: gpr
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D', '5D']]]
|
|
throughput: 0.333333333333333
|
|
uops: 1
|
|
- name: movupd
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: movupd # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: movupd # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovupd
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovupd # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovupd # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovupd
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovupd # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: ymm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovupd # with store
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovupd
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovupd # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: zmm
|
|
latency: 4
|
|
port_pressure: [[2, '135'], [2, ['1D', '3D']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: vmovupd # with store
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[2 , ['1', '3']], [2, ['13']]]
|
|
throughput: 2.0
|
|
uops: 4
|
|
- name: movups
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: movups # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: movups # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovups
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovups # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovups # with store
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovups
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovups # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: ymm
|
|
latency: 4
|
|
port_pressure: [[1, '135'], [1, ['1D', '3D']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vmovups # with store
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[1 , ['1', '3']], [1, ['13']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vmovups
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 0
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1.0
|
|
- name: vmovups # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: zmm
|
|
latency: 4
|
|
port_pressure: [[2, '135'], [2, ['1D', '3D']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: vmovups # with store
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
latency: 0
|
|
port_pressure: [[2 , ['1', '3']], [2, ['13']]]
|
|
throughput: 2.0
|
|
uops: 4
|
|
##########################################
|
|
- name: adc # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: gpr # ibench
|
|
- class: register # ibench
|
|
name: gpr # ibench
|
|
latency: 1 # ibench
|
|
port_pressure: [[1, '07']] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: add # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: gpr # ibench
|
|
- class: register # ibench
|
|
name: gpr # ibench
|
|
latency: 1 # ibench
|
|
port_pressure: [[1, '0246']] # ibench
|
|
throughput: 0.25 # ibench
|
|
uops: 1 # ibench
|
|
- name: add # ibench
|
|
operands: # ibench
|
|
- class: immediate # ibench
|
|
imd: int # ibench
|
|
- class: register # ibench
|
|
name: gpr # ibench
|
|
latency: 1 # ibench
|
|
port_pressure: [[1, '0246']] # ibench
|
|
throughput: 0.25 # ibench
|
|
uops: 1 # ibench
|
|
- name: addpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: addsd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: mulsd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: mulpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: mulss # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: mulps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: addps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: addss # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: rcpss # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 1.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: rcpps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 1.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vrcpps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 1.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vrcpps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 1.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vrcpss # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 1.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: sqrtsd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 21 # ibench
|
|
port_pressure: [[17, ['9DV', '11DV']], [1, ['9', '11']]] # ibench
|
|
throughput: 8.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: sqrtss # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 15 # ibench
|
|
port_pressure: [[10, ['9DV', '11DV']], [1, ['9', '11']]] # ibench
|
|
throughput: 5.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vsqrtsd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 21 # ibench
|
|
port_pressure: [[17, ['9DV', '11DV']], [1, ['9', '11']]] # ibench
|
|
throughput: 8.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vsqrtss # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 15 # ibench
|
|
port_pressure: [[10, ['9DV', '11DV']], [1, ['9', '11']]] # ibench
|
|
throughput: 5.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: sub # ibench
|
|
operands: # ibench
|
|
- class: immediate # ibench
|
|
imd: int # ibench
|
|
- class: register # ibench
|
|
name: gpr # ibench
|
|
latency: 1 # ibench
|
|
port_pressure: [[1, '0246']] # ibench
|
|
throughput: 0.25 # ibench
|
|
uops: 1 # ibench
|
|
- name: sub # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: gpr # ibench
|
|
- class: register # ibench
|
|
name: gpr # ibench
|
|
latency: 1 # ibench
|
|
port_pressure: [[1, '0246']] # ibench
|
|
throughput: 0.25 # ibench
|
|
uops: 1 # ibench
|
|
- name: vaddpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vaddpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vaddpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[2, ['10', '12']]] # ibench
|
|
throughput: 1.0 # ibench
|
|
uops: 2 # ibench
|
|
- name: vaddpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[2, ['10', '12']]] # ibench
|
|
throughput: 1.0 # ibench
|
|
uops: 2 # ibench
|
|
- name: vaddpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vaddpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vaddps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[2, ['10', '12']]] # ibench
|
|
throughput: 1.0 # ibench
|
|
uops: 2 # ibench
|
|
- name: vaddps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vaddps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vaddps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vaddps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vaddps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[2, ['10', '12']]] # ibench
|
|
throughput: 1.0 # ibench
|
|
uops: 2 # ibench
|
|
- name: vaddsd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vaddsd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vaddss # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vaddss # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 2 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vdivpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 13 # ibench
|
|
port_pressure: [[1, ['9', '11']], [10, ['9DV', '11DV']]] # ibench
|
|
throughput: 5.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vdivpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
latency: 13 # ibench
|
|
port_pressure: [[1, ['9', '11']], [10, ['9DV', '11DV']]] # ibench
|
|
throughput: 5.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vdivpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
latency: 13 # ibench
|
|
port_pressure: [[1, ['9', '11']], [18, ['9DV', '11DV']]] # ibench
|
|
throughput: 9.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vdivpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
mask: True # ibench
|
|
latency: 13 # ibench
|
|
port_pressure: [[1, ['9', '11']], [18, ['9DV', '11DV']]] # ibench
|
|
throughput: 9.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vdivpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
mask: True # ibench
|
|
latency: 13 # ibench
|
|
port_pressure: [[1, ['9', '11']], [10, ['9DV', '11DV']]] # ibench
|
|
throughput: 5.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vdivpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 13 # ibench
|
|
port_pressure: [[1, ['9', '11']], [10, ['9DV', '11DV']]] # ibench
|
|
throughput: 5.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vdivps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
latency: 11 # ibench
|
|
port_pressure: [[1, ['9', '11']], [12, ['9DV', '11DV']]] # ibench
|
|
throughput: 6.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vdivps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
mask: True # ibench
|
|
latency: 11 # ibench
|
|
port_pressure: [[1, ['9', '11']], [12, ['9DV', '11DV']]] # ibench
|
|
throughput: 6.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vdivps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
mask: True # ibench
|
|
latency: 11 # ibench
|
|
port_pressure: [[1, ['9', '11']], [6, ['9DV', '11DV']]] # ibench
|
|
throughput: 3.0 # ibench
|
|
uops: 5 # ibench
|
|
- name: vdivps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
latency: 11 # ibench
|
|
port_pressure: [[1, ['9', '11']], [6, ['9DV', '11DV']]] # ibench
|
|
throughput: 3.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vdivps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 11 # ibench
|
|
port_pressure: [[1, ['9', '11']], [6, ['9DV', '11DV']]] # ibench
|
|
throughput: 3.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vdivps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 11 # ibench
|
|
port_pressure: [[1, ['9', '11']], [6, ['9DV', '11DV']]] # ibench
|
|
throughput: 3.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vdivss # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 11 # ibench
|
|
port_pressure: [[1, ['9', '11']], [6, ['9DV', '11DV']]] # ibench
|
|
throughput: 3.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vdivss # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 11 # ibench
|
|
port_pressure: [[1, ['9', '11']], [6, ['9DV', '11DV']]] # ibench
|
|
throughput: 3.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vdivsd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 13 # ibench
|
|
port_pressure: [[1, ['9', '11']], [10, ['9DV', '11DV']]] # ibench
|
|
throughput: 5.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vdivsd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 13 # ibench
|
|
port_pressure: [[1, ['9', '11']], [10, ['9DV', '11DV']]] # ibench
|
|
throughput: 5.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd, vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd, vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd, vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
mask: True # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd, vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]]
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd, vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[2, ['9', '11']]]
|
|
throughput: 1.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vfmadd213pd, vfmadd132pd, vfmadd231pd, vfnmadd213pd, vfnmadd132pd, vfnmadd231pd, vfmsub213pd, vfmsub132pd, vfmsub231pd, vfnmsub213pd, vfnmsub132pd, vfnmsub231pd] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
mask: True # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[2, ['9', '11']]]
|
|
throughput: 1.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps, vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]]
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps, vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]]
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps, vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]]
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps, vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
mask: True # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]]
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps, vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[2, ['9', '11']]]
|
|
throughput: 1.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vfmadd213ps, vfmadd132ps, vfmadd231ps, vfnmadd213ps, vfnmadd132ps, vfnmadd231ps, vfmsub213ps, vfmsub132ps, vfmsub231ps, vfnmsub213ps, vfnmsub132ps, vfnmsub231ps] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
mask: True # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]]
|
|
throughput: 1.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vfmadd213sd, vfmadd132sd, vfmadd231sd, vfnmadd213sd, vfnmadd132sd, vfnmadd231sd, vfmsub213sd, vfmsub132sd, vfmsub231sd, vfnmsub213sd, vfnmsub132sd, vfnmsub231sd] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]]
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vfmadd213sd, vfmadd132sd, vfmadd231sd, vfnmadd213sd, vfnmadd132sd, vfnmadd231sd, vfmsub213sd, vfmsub132sd, vfmsub231sd, vfnmsub213sd, vfnmsub132sd, vfnmsub231sd] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]]
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vfmadd213ss, vfmadd132ss, vfmadd231ss, vfnmadd213ss, vfnmadd132ss, vfnmadd231ss, vfmsub213ss, vfmsub132ss, vfmsub231ss, vfnmsub213ss, vfnmsub132ss, vfnmsub231ss] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]]
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vfmadd213ss, vfmadd132ss, vfmadd231ss, vfnmadd213ss, vfnmadd132ss, vfnmadd231ss, vfmsub213ss, vfmsub132ss, vfmsub231ss, vfnmsub213ss, vfnmsub132ss, vfnmsub231ss] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 4 # ibench
|
|
port_pressure: [[1, ['9', '11']]]
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vgatherdpd, vgatherqpd] # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
latency: 13
|
|
port_pressure: [[6, ['1D', '3D']], [2, ['135']], [1, ['9', '10', '11', '12']], [2, ['9', '11']], [1, ['10','11','12']]]
|
|
throughput: 3.0
|
|
uops: 18
|
|
- name: [vgatherdpd, vgatherqpd] # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: ymm
|
|
latency: 15
|
|
port_pressure: [[8, ['1D', '3D']], [4, '135'], [1, ['9', '10', '11', '12']], [4, ['9', '11']], [2, ['10','11','12']]]
|
|
throughput: 4.0
|
|
uops: 24
|
|
- name: [vgatherdpd, vgatherqpd] # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: zmm
|
|
latency: 26
|
|
port_pressure: [[22, ['1D', '3D']], [8, '135'], [2, ['9', '10', '11', '12']], [8, ['9', '11']], [4, ['10','11','12']]]
|
|
throughput: 11.0
|
|
uops: 48
|
|
- name: [vgatherdpd, vgatherqpd] # uops.info
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: xmm
|
|
mask: True
|
|
latency: 14
|
|
port_pressure: [[8, ['1D', '3D']], [2, '135'], [1, ['9', '10', '11', '12']], [2, ['9', '11']], [1, ['10','11','12']]]
|
|
throughput: 4.0
|
|
uops: 18
|
|
- name: [vgatherdpd, vgatherqpd] # uops.info
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: ymm
|
|
mask: True
|
|
latency: 15
|
|
port_pressure: [[8, ['1D', '3D']], [4, '135'], [1, ['9', '10', '11', '12']], [4, ['9', '11']], [2, ['10','11','12']]]
|
|
throughput: 4.0
|
|
uops: 24
|
|
- name: [vgatherdpd, vgatherqpd] # uops.info
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: zmm
|
|
mask: True
|
|
latency: 26
|
|
port_pressure: [[22, ['1D', '3D']], [8, '135'], [2, ['9', '10', '11', '12']], [8, ['9', '11']], [4, ['10','11','12']]]
|
|
throughput: 11.0
|
|
uops: 48
|
|
- name: vgatherdps # with load # ibench
|
|
operands: # ibench
|
|
- class: memory # ibench
|
|
base: "*" # ibench
|
|
offset: "*" # ibench
|
|
index: "*" # ibench
|
|
scale: "*" # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 15 # ibench
|
|
port_pressure: [[8, ['1D', '3D']], [4, '135'], [1, ['9', '10', '11', '12']], [1, ['9', '11']], [2, ['10','11','12']]]
|
|
throughput: 4.0 # ibench
|
|
uops: 24 # ibench
|
|
- name: vgatherdps # with load # uops.info
|
|
operands: # uops.info
|
|
- class: memory # uops.info
|
|
base: "*" # uops.info
|
|
offset: "*" # uops.info
|
|
index: "*" # uops.info
|
|
scale: "*" # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
latency: 20 # uops.info
|
|
port_pressure: [[16, ['1D', '3D']], [8, '135'], [1, ['9', '10', '11', '12']], [2, ['9', '11']], [4, ['10','11','12']]]
|
|
throughput: 8.0 # uops.info
|
|
uops: 42 #uops.info
|
|
- name: vgatherdps # with load # ibench
|
|
operands: # ibench
|
|
- class: memory # ibench
|
|
base: "*" # ibench
|
|
offset: "*" # ibench
|
|
index: "*" # ibench
|
|
scale: "*" # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 15 # ibench
|
|
port_pressure: [[10, ['1D', '3D']], [4, '135'], [1, ['9', '10', '11', '12']], [1, ['9', '11']], [2, ['10','11','12']]]
|
|
throughput: 5.0 # ibench
|
|
uops: 24 # ibench
|
|
- name: vgatherdps # with load # uops.info
|
|
operands: # uops.info
|
|
- class: memory # uops.info
|
|
base: "*" # uops.info
|
|
offset: "*" # uops.info
|
|
index: "*" # uops.info
|
|
scale: "*" # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
mask: True # ibench
|
|
latency: 21 # uops.info
|
|
port_pressure: [[18, ['1D', '3D']], [8, '135'], [1, ['9', '10', '11', '12']], [2, ['9', '11']], [4, ['10','11','12']]]
|
|
throughput: 9.0 # uops.info
|
|
uops: 41 #uops.info
|
|
- name: vgatherdps # with load # uops.info
|
|
operands: # uops.info
|
|
- class: memory # uops.info
|
|
base: "*" # uops.info
|
|
offset: "*" # uops.info
|
|
index: "*" # uops.info
|
|
scale: "*" # uops.info
|
|
- class: register # uops.info
|
|
name: zmm # uops.info
|
|
mask: True # ibench
|
|
latency: 35 # uops.info
|
|
port_pressure: [[34, ['1D', '3D']], [16, '135'], [2, ['9', '10', '11', '12']], [4, ['9', '11']], [8, ['10','11','12']]]
|
|
throughput: 17.0 # uops.info
|
|
uops: 81 #uops.info
|
|
- name: vmulpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vmulpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vmulpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vmulpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vmulpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[2, ['9', '11']]] # ibench
|
|
throughput: 1.0 # ibench
|
|
uops: 2 # ibench
|
|
- name: vmulpd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 1.0 # ibench
|
|
uops: 2 # ibench
|
|
- name: vmulps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vmulps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vmulps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vmulps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vmulps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[2, ['9', '11']]] # ibench
|
|
throughput: 1.0 # ibench
|
|
uops: 2 # ibench
|
|
- name: vmulps # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 1.0 # ibench
|
|
uops: 2 # ibench
|
|
- name: vmulsd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vmulsd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vmulss # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vmulss # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['9', '11']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vpaddd, vpaddq] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 1 # ibench
|
|
port_pressure: [[1, ['9', '10', '11', '12']]] # ibench
|
|
throughput: 0.25 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vpaddd, vpaddq] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
latency: 1 # ibench
|
|
port_pressure: [[1, ['9', '10', '11', '12']]] # ibench
|
|
throughput: 0.25 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vpaddd, vpaddq] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
latency: 1 # ibench
|
|
port_pressure: [[2, ['9', '10', '11', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vpaddd, vpaddq] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 1 # ibench
|
|
port_pressure: [[1, ['9', '10', '11', '12']]] # ibench
|
|
throughput: 0.25 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vpaddd, vpaddq] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
mask: True # ibench
|
|
latency: 1 # ibench
|
|
port_pressure: [[1, ['9', '10', '11', '12']]] # ibench
|
|
throughput: 0.25 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vpaddd, vpaddq] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
mask: True # ibench
|
|
latency: 1 # ibench
|
|
port_pressure: [[2, ['9', '10', '11', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vrcp14pd, vrcp14ps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
latency: 5 # asmbench
|
|
port_pressure: [[1, ['9', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vrcp14pd, vrcp14ps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
latency: 5 # asmbench
|
|
port_pressure: [[1, ['9', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vrcp14pd, vrcp14ps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
latency: 5 # asmbench
|
|
port_pressure: [[2, ['9', '11']]] # asmbench
|
|
throughput: 1.0 # asmbench
|
|
uops: 2 # asmbench
|
|
- name: [vrcp14pd, vrcp14ps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
mask: True # asmbench
|
|
latency: 5 # asmbench
|
|
port_pressure: [[1, ['9', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vrcp14pd, vrcp14ps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
mask: True # asmbench
|
|
latency: 5 # asmbench
|
|
port_pressure: [[1, ['9', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vrcp14pd, vrcp14ps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
mask: True # asmbench
|
|
latency: 5 # asmbench
|
|
port_pressure: [[2, ['9', '11']]] # asmbench
|
|
throughput: 1.0 # asmbench
|
|
uops: 2 # asmbench
|
|
- name: vrcpss # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
latency: 4 # asmbench
|
|
port_pressure: [[1, ['9', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: vrcpps # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
latency: 4 # asmbench
|
|
port_pressure: [[1, ['9', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: vrcpps # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
latency: 4 # asmbench
|
|
port_pressure: [[1, ['9', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vrsqrt14pd, vrsqrt14ps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
latency: 5 # asmbench
|
|
port_pressure: [[1, ['9', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vrsqrt14pd, vrsqrt14ps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
latency: 5 # asmbench
|
|
port_pressure: [[1, ['9', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vrsqrt14pd, vrsqrt14ps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
latency: 5 # asmbench
|
|
port_pressure: [[2, ['9', '11']]] # asmbench
|
|
throughput: 1.0 # asmbench
|
|
uops: 2 # asmbench
|
|
- name: [vrsqrt14pd, vrsqrt14ps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
mask: True # asmbench
|
|
latency: 5 # asmbench
|
|
port_pressure: [[1, ['9', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vrsqrt14pd, vrsqrt14ps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
mask: True # asmbench
|
|
latency: 5 # asmbench
|
|
port_pressure: [[1, ['9', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vrsqrt14pd, vrsqrt14ps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
mask: True # asmbench
|
|
latency: 5 # asmbench
|
|
port_pressure: [[2, ['9', '11']]] # asmbench
|
|
throughput: 1.0 # asmbench
|
|
uops: 2 # asmbench
|
|
- name: vsqrtpd # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
latency: 21 # asmbench
|
|
port_pressure: [[16, ['9', '11']]] # asmbench
|
|
throughput: 8.0 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: vsqrtpd # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
latency: 21 # asmbench
|
|
port_pressure: [[16, ['9', '11']]] # asmbench
|
|
throughput: 8.0 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: vsqrtpd # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
latency: 21 # asmbench
|
|
port_pressure: [[32, ['9', '11']]] # asmbench
|
|
throughput: 16.0 # asmbench
|
|
uops: 2 # asmbench
|
|
- name: vsqrtpd # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
mask: True # asmbench
|
|
latency: 21 # asmbench
|
|
port_pressure: [[16, ['9', '11']]] # asmbench
|
|
throughput: 8.0 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: vsqrtpd # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
mask: True # asmbench
|
|
latency: 21 # asmbench
|
|
port_pressure: [[16, ['9', '11']]] # asmbench
|
|
throughput: 8.0 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: vsqrtpd # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
mask: True # asmbench
|
|
latency: 21 # asmbench
|
|
port_pressure: [[32, ['9', '11']]] # asmbench
|
|
throughput: 16.0 # asmbench
|
|
uops: 2 # asmbench
|
|
- name: vrsqrtps # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
latency: 4 # asmbench
|
|
port_pressure: [[1, ['9', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: vrsqrtps # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
latency: 4 # asmbench
|
|
port_pressure: [[1, ['9', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [inc, dec]
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
latency: 1
|
|
port_pressure: [[1, '0246']]
|
|
throughput: 0.25
|
|
uops: 1
|
|
- name: vcvtdq2pd # uops.info
|
|
operands: # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
- class: register # uops.info
|
|
name: zmm # uops.info
|
|
latency: 6 # uops.info
|
|
port_pressure: [[2, ['10', '11']], [2, ['10', '12']]] # uops.info
|
|
throughput: 1.33 # uops.info
|
|
- name: vcvtss2si # uops.info
|
|
operands: # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
- class: register # uops.info
|
|
name: gpr # uops.info
|
|
latency: 8 # uops.info
|
|
port_pressure: [[1, ['10']]] # uops.info
|
|
throughput: 1 # uops.info
|
|
uops: 1 # uops.info
|
|
- name: vcvtss2sd # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
latency: 3 # asmbench
|
|
port_pressure: [[1, ['10', '12']]] # uops.info
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vsubpd, vsubps] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 1.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vsubpd, vsubps] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vsubpd, vsubps] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vsubpd, vsubps] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
- class: register # ibench
|
|
name: ymm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: [vsubpd, vsubps] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[2, ['10', '12']]] # ibench
|
|
throughput: 1.0 # ibench
|
|
uops: 2 # ibench
|
|
- name: [vsubpd, vsubps] # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
- class: register # ibench
|
|
name: zmm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[2, ['10', '12']]] # ibench
|
|
throughput: 1.0 # ibench
|
|
uops: 1 # ibench
|
|
- name: vsubsd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vsubsd # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vsubss # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
mask: True # ibench
|
|
latency: 3 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: vsubss # ibench
|
|
operands: # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
- class: register # ibench
|
|
name: xmm # ibench
|
|
latency: 2 # ibench
|
|
port_pressure: [[1, ['10', '12']]] # ibench
|
|
throughput: 0.5 # ibench
|
|
uops: 1 # ibench
|
|
- name: lea # uops.info
|
|
operands: # uops.info
|
|
- class: memory # uops.info
|
|
base: "*" # uops.info
|
|
offset: "*" # uops.info
|
|
index: "*" # uops.info
|
|
scale: "*" # uops.info
|
|
- class: register # uops.info
|
|
name: gpr # uops.info
|
|
latency: 1 # uops.info
|
|
port_pressure: [[1, '0246']] # uops.info
|
|
throughput: 0.25 # uops.info
|
|
uops: 1 # uops.info
|
|
- name: [shl, shr, sal, sar] # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: gpr # uops.info
|
|
latency: 1 # uops.info
|
|
port_pressure: [[1, '24']] # uops.info
|
|
throughput: 0.5 # uops.info
|
|
uops: 1 # uops.info
|
|
- name: [shl, shr, sal, sar]
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
latency: 1 # uops.info
|
|
port_pressure: [[1, '4']] # uops.info
|
|
throughput: 0.5 # uops.info
|
|
uops: 1 # uops.info
|
|
- name: vinsertf128
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 1
|
|
port_pressure: [[1, ['10', '11']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vinserti128
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 1
|
|
port_pressure: [[1, ['10', '11']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vinsertf32x4
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 1
|
|
port_pressure: [[1, ['10', '11']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vinsertf32x8
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 1
|
|
port_pressure: [[2, ['10', '11']]]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: vinsertf64x2
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 1
|
|
port_pressure: [[1, ['10', '11']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vinsertf64x4
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 1
|
|
port_pressure: [[2, ['10', '11']]]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: vinsertps
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 1
|
|
port_pressure: [[1, ['10', '11', '12']]]
|
|
throughput: 0.33333333333
|
|
uops: 1
|
|
- name: vinserti64x4
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 1
|
|
port_pressure: [[2, ['10', '11']]]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: vinserti64x2
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 1
|
|
port_pressure: [[1, ['10', '11']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vcvtsi2sd
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 3
|
|
port_pressure: [[1, ['10']]]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: vcvtdq2pd
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: ymm
|
|
latency: 4
|
|
port_pressure: [[1, ['10', '11']], [1, ['11', '12']]]
|
|
throughput: 0.6666666666
|
|
uops: 2
|
|
- name: vcvtsi2ss
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 3
|
|
port_pressure: [[1, ['10']]]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: [vextractf128, vextracti128]
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: xmm
|
|
latency: 1
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1
|
|
- name: vextractps
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: gpr
|
|
latency: 6
|
|
port_pressure: [[1, ['10']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: [vextractf32x4, vextracti32x4] # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
latency: 1 # uops.info
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1 # uops.info
|
|
- name: [vextractf32x4, vextracti32x4] # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: zmm # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
latency: 4 # uops.info
|
|
port_pressure: [[2, ['9', '11']]]
|
|
throughput: 1.00
|
|
uops: 1 # uops.info
|
|
- name: [vextractf32x4, vextracti32x4] # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: zmm # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
mask: True # uops.info
|
|
latency: 4 # uops.info
|
|
port_pressure: [[2, ['9', '11']]]
|
|
throughput: 1.00
|
|
uops: 1 # uops.info
|
|
- name: [vextractf32x4, vextracti32x4] # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
mask: True # uops.info
|
|
latency: 1 # uops.info
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1 # uops.info
|
|
- name: [vextractf32x8, vextracti32x8] # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: zmm # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
mask: True # uops.info
|
|
latency: 1 # uops.info
|
|
port_pressure: [[2, ['9', '10', '11', '12']]]
|
|
throughput: 0.50
|
|
uops: 1 # uops.info
|
|
- name: [vextractf32x8, vextracti32x8] # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: zmm # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
latency: 1 # uops.info
|
|
port_pressure: [[2, ['9', '10', '11', '12']]]
|
|
throughput: 0.50
|
|
uops: 1 # uops.info
|
|
- name: [vextractf64x2, vextracti64x2] # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
latency: 1 # uops.info
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1 # uops.info
|
|
- name: [vextractf64x2, vextracti64x2] # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
mask: True # uops.info
|
|
latency: 4 # uops.info
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1 # uops.info
|
|
- name: [vextractf64x2, vextracti64x2] # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: zmm # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
mask: True # uops.info
|
|
latency: 4 # uops.info
|
|
port_pressure: [[2, ['10', '11']]]
|
|
throughput: 1.0
|
|
uops: 1 # uops.info
|
|
- name: [vextractf64x2, vextracti64x2] # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: zmm # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
latency: 4 # uops.info
|
|
port_pressure: [[2, ['10', '11']]]
|
|
throughput: 1.0
|
|
uops: 1 # uops.info
|
|
- name: [vextractf64x4, vextracti64x4] # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: zmm # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
latency: 1 # uops.info
|
|
port_pressure: [[2, ['9', '10', '11', '12']]]
|
|
throughput: 0.50
|
|
uops: 1 # uops.info
|
|
- name: [vextractf64x4, vextracti64x4] # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: zmm # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
mask: True # uops.info
|
|
latency: 1 # uops.info
|
|
port_pressure: [[2, ['9', '10', '11', '12']]]
|
|
throughput: 0.50
|
|
uops: 1 # uops.info
|
|
- name: vpinsrd # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: gpr # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
latency: 1 # uops.info
|
|
port_pressure: [[1, ['11']]] # uops.info
|
|
throughput: 1.0 # uops.info
|
|
uops: 1 # uops.info
|
|
- name: vpalignr # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
latency: 2 # uops.info
|
|
port_pressure: [[1, ['10', '11']]] # uops.info
|
|
throughput: 0.5 # uops.info
|
|
uops: 1 # uops.info
|
|
- name: vpalignr # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
- class: register # uops.info
|
|
name: xmm # uops.info
|
|
mask: True # uops.info
|
|
latency: 2 # uops.info
|
|
port_pressure: [[1, ['10', '11']]] # uops.info
|
|
throughput: 0.5 # uops.info
|
|
uops: 1 # uops.info
|
|
- name: vpalignr # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
latency: 2 # uops.info
|
|
port_pressure: [[1, ['10', '11']]] # uops.info
|
|
throughput: 0.5 # uops.info
|
|
uops: 1 # uops.info
|
|
- name: vpalignr # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
- class: register # uops.info
|
|
name: ymm # uops.info
|
|
mask: True # uops.info
|
|
latency: 2 # uops.info
|
|
port_pressure: [[1, ['10', '11']]] # uops.info
|
|
throughput: 0.5 # uops.info
|
|
uops: 1 # uops.info
|
|
- name: vpalignr # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: zmm # uops.info
|
|
- class: register # uops.info
|
|
name: zmm # uops.info
|
|
- class: register # uops.info
|
|
name: zmm # uops.info
|
|
latency: 2 # uops.info
|
|
port_pressure: [[2, ['10', '11']]] # uops.info
|
|
throughput: 1.0 # uops.info
|
|
uops: 2 # uops.info
|
|
- name: vpalignr # uops.info
|
|
operands: # uops.info
|
|
- class: immediate # uops.info
|
|
imd: int # uops.info
|
|
- class: register # uops.info
|
|
name: zmm # uops.info
|
|
- class: register # uops.info
|
|
name: zmm # uops.info
|
|
- class: register # uops.info
|
|
name: zmm # uops.info
|
|
mask: True # uops.info
|
|
latency: 2 # uops.info
|
|
port_pressure: [[2, ['10', '11']]] # uops.info
|
|
throughput: 1.0 # uops.info
|
|
uops: 2 # uops.info
|
|
- name: [vperm2f128, vperm2i128] # asmbench
|
|
operands: # asmbench
|
|
- class: immediate # asmbench
|
|
imd: int # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
latency: 3 # asmbench
|
|
port_pressure: [[1, ['10', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: vpermd # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
latency: 4 # asmbench
|
|
port_pressure: [[1, ['10', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: vpermd # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
mask: True # asmbench
|
|
latency: 4 # asmbench
|
|
port_pressure: [[1, ['10', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vpermd, vpermt2q] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
latency: 5 # asmbench
|
|
port_pressure: [[2, ['10', '11']]] # asmbench
|
|
throughput: 1.0 # asmbench
|
|
uops: 2 # asmbench
|
|
- name: [vpermd, vpermt2q] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
mask: True # asmbench
|
|
latency: 5 # asmbench
|
|
port_pressure: [[2, ['10', '11']]] # asmbench
|
|
throughput: 1.0 # asmbench
|
|
uops: 2 # asmbench
|
|
- name: [vpermpd, vpermps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
latency: 4 # asmbench
|
|
port_pressure: [[1, ['10', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vpermpd, vpermps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
mask: True # asmbench
|
|
latency: 4 # asmbench
|
|
port_pressure: [[1, ['10', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vpermpd, vpermps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
latency: 5 # asmbench
|
|
port_pressure: [[2, ['10', '11']]] # asmbench
|
|
throughput: 1.0 # asmbench
|
|
uops: 2 # asmbench
|
|
- name: [vpermpd, vpermps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
mask: True # asmbench
|
|
latency: 5 # asmbench
|
|
port_pressure: [[2, ['10', '11']]] # asmbench
|
|
throughput: 1.0 # asmbench
|
|
uops: 2 # asmbench
|
|
- name: [vpermilpd, vpermilps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
latency: 2 # asmbench
|
|
port_pressure: [[1, ['10', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vpermilpd, vpermilps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
mask: True # asmbench
|
|
latency: 2 # asmbench
|
|
port_pressure: [[1, ['10', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vpermilpd, vpermilps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
latency: 2 # asmbench
|
|
port_pressure: [[1, ['10', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vpermilpd, vpermilps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
mask: True # asmbench
|
|
latency: 2 # asmbench
|
|
port_pressure: [[1, ['10', '11']]] # asmbench
|
|
throughput: 0.5 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vpermilpd, vpermilps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
latency: 2 # asmbench
|
|
port_pressure: [[2, ['10', '11']]] # asmbench
|
|
throughput: 1.0 # asmbench
|
|
uops: 2 # asmbench
|
|
- name: [vpermilpd, vpermilps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
mask: True # asmbench
|
|
latency: 2 # asmbench
|
|
port_pressure: [[2, ['10', '11']]] # asmbench
|
|
throughput: 1.0 # asmbench
|
|
uops: 2 # asmbench
|
|
- name: [vpermilpd, vpermilps] # asmbench
|
|
operands: # asmbench
|
|
- class: immediate
|
|
imd: int
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
latency: 1 # asmbench
|
|
port_pressure: [[1, ['10', '11', '12']]] # asmbench
|
|
throughput: 0.3333333333 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vpermilpd, vpermilps] # asmbench
|
|
operands: # asmbench
|
|
- class: immediate
|
|
imd: int
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
mask: True # asmbench
|
|
latency: 1 # asmbench
|
|
port_pressure: [[1, ['10', '11', '12']]] # asmbench
|
|
throughput: 0.3333333333 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vpermilpd, vpermilps] # asmbench
|
|
operands: # asmbench
|
|
- class: immediate
|
|
imd: int
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
latency: 1 # asmbench
|
|
port_pressure: [[1, ['10', '11', '12']]] # asmbench
|
|
throughput: 0.3333333333 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vpermilpd, vpermilps] # asmbench
|
|
operands: # asmbench
|
|
- class: immediate
|
|
imd: int
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
mask: True # asmbench
|
|
latency: 1 # asmbench
|
|
port_pressure: [[1, ['10', '11', '12']]] # asmbench
|
|
throughput: 0.3333333333 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vpermilpd, vpermilps] # asmbench
|
|
operands: # asmbench
|
|
- class: immediate
|
|
imd: int
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
latency: 1 # asmbench
|
|
port_pressure: [[2, ['10', '11', '12']]] # asmbench
|
|
throughput: 0.6666666666 # asmbench
|
|
uops: 2 # asmbench
|
|
- name: [vpermilpd, vpermilps] # asmbench
|
|
operands: # asmbench
|
|
- class: immediate
|
|
imd: int
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
mask: True # asmbench
|
|
latency: 1 # asmbench
|
|
port_pressure: [[2, ['10', '11', '12']]] # asmbench
|
|
throughput: 0.6666666666 # asmbench
|
|
uops: 2 # asmbench
|
|
- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
latency: 1 # asmbench
|
|
port_pressure: [[1, ['10', '11', '12']]] # asmbench
|
|
throughput: 0.333333333333 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
latency: 1 # asmbench
|
|
port_pressure: [[1, ['10', '11', '12']]] # asmbench
|
|
throughput: 0.333333333333 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
latency: 1 # asmbench
|
|
port_pressure: [[2, ['10', '11', '12']]] # asmbench
|
|
throughput: 0.666666666666 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
- class: register # asmbench
|
|
name: xmm # asmbench
|
|
mask: True # asmbench
|
|
latency: 1 # asmbench
|
|
port_pressure: [[1, ['10', '11', '12']]] # asmbench
|
|
throughput: 0.333333333333 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
- class: register # asmbench
|
|
name: ymm # asmbench
|
|
mask: True # asmbench
|
|
latency: 1 # asmbench
|
|
port_pressure: [[1, ['10', '11', '12']]] # asmbench
|
|
throughput: 0.333333333333 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vunpckhpd, vunpckhps, vunpcklpd, vunpcklps] # asmbench
|
|
operands: # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
- class: register # asmbench
|
|
name: zmm # asmbench
|
|
mask: True # asmbench
|
|
latency: 1 # asmbench
|
|
port_pressure: [[2, ['10', '11', '12']]] # asmbench
|
|
throughput: 0.666666666666 # asmbench
|
|
uops: 1 # asmbench
|
|
- name: [vpcmpgtb, vpcmpgtw, vpcmpgtd, vpcmpgtq]
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: k
|
|
latency: 3
|
|
port_pressure: [[1, '5']]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: [vpcmpgtb, vpcmpgtw, vpcmpgtd, vpcmpgtq]
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: k
|
|
latency: 4
|
|
port_pressure: [[1, ['9', '11']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: [vpcmpgtb, vpcmpgtw, vpcmpgtd, vpcmpgtq, vpcmpeqb, vpcmpeqw, vpcmpeqd, vpcmpeqq]
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: k
|
|
latency: 5
|
|
port_pressure: [[2, ['9', '11']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: vpcmpd
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: k
|
|
latency: 3
|
|
port_pressure: [[1, ['9', '11']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vpcmpd
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: k
|
|
latency: 4
|
|
port_pressure: [[1, ['9', '11']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vpcmpd
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: k
|
|
latency: 5
|
|
port_pressure: [[2, ['9', '11']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: [vpcmpeqb, vpcmpeqw, vpcmpeqd, vpcmpeqq]
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 1
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1
|
|
- name: [vpcmpeqb, vpcmpeqw, vpcmpeqd, vpcmpeqq]
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 1
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1
|
|
- name: [vcmppd, vcmpps]
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 2
|
|
port_pressure: [[1, ['10', '12']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: [vcmppd, vcmpps]
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 2
|
|
port_pressure: [[1, ['10', '12']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vcmpps
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: k
|
|
latency: 5
|
|
port_pressure: [[2, ['9', '11']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: vcmpps
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: k
|
|
mask: True
|
|
latency: 5
|
|
port_pressure: [[2, ['9', '11']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: vcmpps
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: k
|
|
latency: 3
|
|
port_pressure: [[1, ['9', '11']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vcmpps
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: k
|
|
latency: 4
|
|
port_pressure: [[1, ['9', '11']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: vcmppd
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: k
|
|
latency: 5
|
|
port_pressure: [[2, ['9', '11']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: vcmppd
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: k
|
|
mask: True
|
|
latency: 5
|
|
port_pressure: [[2, ['9', '11']]]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: vpunpckhqdq
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 1
|
|
port_pressure: [[1, ['10', '11', '12']]]
|
|
throughput: 0.333333333
|
|
uops: 1
|
|
- name: vpunpckhqdq
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 1
|
|
port_pressure: [[1, ['10', '11', '12']]]
|
|
throughput: 0.333333333
|
|
uops: 1
|
|
- name: vpunpckhqdq
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 1
|
|
port_pressure: [[2, ['10', '11', '12']]]
|
|
throughput: 0.666666666
|
|
uops: 1
|
|
########## TODO ###############
|
|
- name: [AND, OR]
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: gpr
|
|
latency: 1
|
|
port_pressure: [[1, '0246']]
|
|
throughput: 0.25
|
|
uops: 1
|
|
- name: [AND, OR]
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: gpr
|
|
latency: 1
|
|
port_pressure: [[1, '0246']]
|
|
throughput: 0.25
|
|
uops: 1
|
|
|
|
- name: RET
|
|
operands: []
|
|
latency: 0
|
|
port_pressure: [[1, ['1', '3']], [1, ['13']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: CALL
|
|
operands:
|
|
- class: identifier
|
|
latency: 0
|
|
port_pressure: [[1, ['1', '3']], [1, ['13']]]
|
|
throughput: 1.5
|
|
uops: 2
|
|
- name: TEST
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: gpr
|
|
latency: 1
|
|
port_pressure: [[1, '0246']]
|
|
throughput: 0.25
|
|
uops: 1
|
|
- name: TEST
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: gpr
|
|
latency: 1
|
|
port_pressure: [[1, '0246']]
|
|
throughput: 0.25
|
|
uops: 1
|
|
- name: PTEST
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 3
|
|
port_pressure: [[1, ['10', '11'], [1, '13']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: VPTEST
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 3
|
|
port_pressure: [[1, ['10', '11'], [1, '13']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: VPTEST
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 3
|
|
port_pressure: [[1, ['10', '11'], [1, '13']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: [VTESTPD, VTESTPS]
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 3
|
|
port_pressure: [[1, ['10', '11'], [1, '13']]]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: [VTESTPD, VTESTPS]
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 3
|
|
port_pressure: [[1, ['10', '11'], [1, '13']]]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: [vxorps, vxorpd]
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 1
|
|
port_pressure: [[1, ['9','10','11','12']]]
|
|
throughput: 0.25
|
|
uops: 1
|
|
- name: [vxorps, vxorpd]
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 1
|
|
port_pressure: [[1, ['9','10','11','12']]]
|
|
throughput: 0.25
|
|
uops: 1
|
|
- name: VPBROADCASTQ
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: xmm
|
|
latency: 6
|
|
port_pressure: [[1, ['10']]] #uops.info
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: VPBROADCASTQ
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: ymm
|
|
latency: 6
|
|
port_pressure: [[1, ['10']]] #uops.info
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: VPBROADCASTQ
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: zmm
|
|
latency: 6
|
|
port_pressure: [[2, ['10', '11']]] #uops.info
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: VPBROADCASTD
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: xmm
|
|
latency: 6
|
|
port_pressure: [[2, ['10', '11']]] #uops.info
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: VPBROADCASTD
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: ymm
|
|
latency: 6
|
|
port_pressure: [[2, ['10', '11']]] #uops.info
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: VPBROADCASTD
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: zmm
|
|
latency: 6
|
|
port_pressure: [[2, ['10', '11']]] #uops.info
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: VBROADCASTSS
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 1
|
|
port_pressure: [[1, ['10', '11', '12']]]
|
|
throughput: 0.3333333
|
|
uops: 1
|
|
- name: [VBROADCASTSD, VBROADCASTSS]
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: ymm
|
|
latency: 1
|
|
port_pressure: [[1, ['10', '11']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: [VBROADCASTSD, VBROADCASTSS]
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 1
|
|
port_pressure: [[2, ['10', '11']]]
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: [VBROADCASTSD, VBROADCASTSS] # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: ymm
|
|
latency: 8
|
|
port_pressure: [[1, ['1D', '3D']], [1, ['10', '11']], [2, ['135']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: [VBROADCASTSD, VBROADCASTSS] # with load
|
|
operands:
|
|
- class: memory
|
|
base: "*"
|
|
offset: "*"
|
|
index: "*"
|
|
scale: "*"
|
|
- class: register
|
|
name: zmm
|
|
latency: 9
|
|
port_pressure: [[2, ['1D', '3D']], [1, ['10', '11']], [4, ['135']]]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: vandpd
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 1
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1
|
|
- name: vandpd
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 1
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1
|
|
- name: vandpd
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 1
|
|
port_pressure: [[2, ['9', '10', '11', '12']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: vshuff64x2
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 4
|
|
port_pressure: [[2, ['10', '11']]] #uops.info
|
|
throughput: 1.0
|
|
uops: 2
|
|
- name: vmovd
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: xmm
|
|
latency: 1
|
|
port_pressure: [[1, '0']]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: vmov
|
|
operands:
|
|
- class: register
|
|
name: gpr
|
|
- class: register
|
|
name: xmm
|
|
latency: 1
|
|
port_pressure: [[1, '0']]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: vmovq
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: gpr
|
|
latency: 5
|
|
port_pressure: [[1, '8']]
|
|
throughput: 1.0
|
|
uops: 1.0
|
|
- name: [vpor, vpxor, vpord, vpxord]
|
|
operands:
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 1
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1
|
|
- name: [vpor, vpxor, vpord, vpxord]
|
|
operands:
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 1
|
|
port_pressure: [[1, ['9', '10', '11', '12']]]
|
|
throughput: 0.25
|
|
uops: 1
|
|
- name: [vpor, vpxor, vpord, vpxord]
|
|
operands:
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 1
|
|
port_pressure: [[2, ['9', '10', '11', '12']]]
|
|
throughput: 0.5
|
|
uops: 2
|
|
- name: [kxorb, kxorw, kxord, kxnorb, kxnorw, kxnord]
|
|
operands:
|
|
- class: register
|
|
name: k
|
|
- class: register
|
|
name: k
|
|
- class: register
|
|
name: k
|
|
latency: 1
|
|
port_pressure: [[1, ['10', '12']]]
|
|
throughput: 0.5
|
|
uops: 1
|
|
- name: [kxorq, kxnorq]
|
|
operands:
|
|
- class: register
|
|
name: k
|
|
- class: register
|
|
name: k
|
|
- class: register
|
|
name: k
|
|
latency: 1
|
|
port_pressure: [[2, ['10', '12']]]
|
|
throughput: 1.0
|
|
uops: 1
|
|
- name: [vshufpd, vshufps] #asmbench
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
latency: 1
|
|
port_pressure: [[1, '123']]
|
|
throughput: 0.33333
|
|
uops: 1
|
|
- name: [vshufpd, vshufps] #asmbench
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
latency: 1
|
|
port_pressure: [[1, '123']]
|
|
throughput: 0.33333
|
|
uops: 1
|
|
- name: [vshufpd, vshufps] #asmbench
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
latency: 1
|
|
port_pressure: [[2, '123']]
|
|
throughput: 0.66666
|
|
uops: 2
|
|
- name: [vshufpd, vshufps] #asmbench
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: xmm
|
|
- class: register
|
|
name: k
|
|
- class: register
|
|
name: xmm
|
|
latency: 1
|
|
port_pressure: [[1, '123']]
|
|
throughput: 0.33333
|
|
uops: 1
|
|
- name: [vshufpd, vshufps] #asmbench
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: ymm
|
|
- class: register
|
|
name: k
|
|
- class: register
|
|
name: ymm
|
|
latency: 1
|
|
port_pressure: [[1, '123']]
|
|
throughput: 0.33333
|
|
uops: 1
|
|
- name: [vshufpd, vshufps] #asmbench
|
|
operands:
|
|
- class: immediate
|
|
imd: int
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: zmm
|
|
- class: register
|
|
name: k
|
|
- class: register
|
|
name: zmm
|
|
latency: 1
|
|
port_pressure: [[2, '123']]
|
|
throughput: 0.66666
|
|
uops: 2
|