Metehan Dundar 5b193c80ce Add RISCV parser to test suite

2025-03-11 11:42:15 +01:00

..

test_files

Add initial support for RISC-V architecture and update relevant files

2025-03-11 05:10:03 +01:00

__init__.py

made tests a module

2019-10-25 14:49:21 +02:00

all_tests.py

Add RISCV parser to test suite

2025-03-11 11:42:15 +01:00

test_base_parser.py

Port pressure returned in tuple with Memory Operand

2024-03-04 20:00:43 +01:00

test_cli.py

Uncommented tests

2024-03-05 00:19:29 +01:00

test_db_interface.py

moved get_full_instruction_name() from HardwareModel to DBInterface

2024-05-02 16:25:41 +02:00

test_frontend.py

Added updated files

2024-02-27 14:47:55 +01:00

test_marker_utils.py

Fixed semantic and marker tests. Now only dump needs to be adjusted

2023-12-03 16:49:33 +01:00

test_parser_AArch64.py

formattign

2024-05-02 16:30:11 +02:00

test_parser_RISCV.py

Add initial support for RISC-V architecture and update relevant files

2025-03-11 05:10:03 +01:00

test_parser_x86att.py

formatting

2024-08-19 15:52:28 +02:00

test_semantics.py

moved get_full_instruction_name() from HardwareModel to DBInterface

2024-05-02 16:25:41 +02:00