mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2026-01-04 18:20:09 +01:00
590 lines
22 KiB
Python
Executable File
590 lines
22 KiB
Python
Executable File
#!/usr/bin/env python3
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import re
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from copy import deepcopy
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from itertools import product
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import ruamel.yaml
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from ruamel.yaml.compat import StringIO
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from osaca import __version__, utils
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from osaca.parser import ParserX86ATT
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class MachineModel(object):
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WILDCARD = '*'
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def __init__(self, arch=None, path_to_yaml=None, isa=None, lazy=False):
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if not arch and not path_to_yaml:
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if not isa:
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raise ValueError('One of arch, path_to_yaml and isa must be specified')
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self._data = {
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'osaca_version': str(__version__),
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'micro_architecture': None,
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'arch_code': None,
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'isa': isa,
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'ROB_size': None,
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'retired_uOps_per_cycle': None,
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'scheduler_size': None,
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'hidden_loads': None,
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'load_latency': {},
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'load_throughput': [
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{'base': b, 'index': i, 'offset': o, 'scale': s, 'port_pressure': []}
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for b, i, o, s in product(['gpr'], ['gpr', None], ['imd', None], [1, 8])
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],
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'load_throughput_default': [],
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'ports': [],
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'port_model_scheme': None,
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'instruction_forms': [],
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}
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else:
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if arch and path_to_yaml:
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raise ValueError('Only one of arch and path_to_yaml is allowed.')
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self._path = path_to_yaml
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self._arch = arch
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yaml = self._create_yaml_object()
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if arch:
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self._arch = arch.lower()
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self._path = utils.find_file(self._arch + '.yml')
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with open(self._path, 'r') as f:
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if not lazy:
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self._data = yaml.load(f)
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else:
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file_content = ''
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line = f.readline()
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while 'instruction_forms:' not in line:
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file_content += line
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line = f.readline()
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self._data = yaml.load(file_content)
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self._data['instruction_forms'] = []
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# For use with dict instead of list as DB
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# self._data['instruction_dict'] = (
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# self._convert_to_dict(self._data['instruction_forms'])
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# )
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def __getitem__(self, key):
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"""Return configuration entry."""
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return self._data[key]
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def __contains__(self, key):
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"""Return true if configuration key is present."""
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return key in self._data
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######################################################
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def get_instruction(self, name, operands):
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"""Find and return instruction data from name and operands."""
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# For use with dict instead of list as DB
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# return self.get_instruction_from_dict(name, operands)
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if name is None:
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return None
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try:
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return next(
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instruction_form
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for instruction_form in self._data['instruction_forms']
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if instruction_form['name'].upper() == name.upper()
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and self._match_operands(
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instruction_form['operands'] if 'operands' in instruction_form else [],
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operands,
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)
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)
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except StopIteration:
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return None
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except TypeError as e:
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print('\nname: {}\noperands: {}'.format(name, operands))
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raise TypeError from e
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def get_instruction_from_dict(self, name, operands):
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if name is None:
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return None
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try:
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# Check if key is in dict
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instruction_form = self._data['instruction_dict'][self._get_key(name, operands)]
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return instruction_form
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except KeyError:
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return None
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def average_port_pressure(self, port_pressure):
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"""Construct average port pressure list from instruction data."""
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port_list = self._data['ports']
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average_pressure = [0.0] * len(port_list)
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for cycles, ports in port_pressure:
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for p in ports:
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average_pressure[port_list.index(p)] += cycles / len(ports)
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return average_pressure
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def set_instruction(
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self, name, operands=None, latency=None, port_pressure=None, throughput=None, uops=None
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):
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"""Import instruction form information."""
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# If it already exists. Overwrite information.
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instr_data = self.get_instruction(name, operands)
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if instr_data is None:
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instr_data = {}
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self._data['instruction_forms'].append(instr_data)
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instr_data['name'] = name
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instr_data['operands'] = operands
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instr_data['latency'] = latency
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instr_data['port_pressure'] = port_pressure
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instr_data['throughput'] = throughput
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instr_data['uops'] = uops
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def set_instruction_entry(self, entry):
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self.set_instruction(
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entry['name'],
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entry['operands'] if 'operands' in entry else None,
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entry['latency'] if 'latency' in entry else None,
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entry['port_pressure'] if 'port_pressure' in entry else None,
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entry['throughput'] if 'throughput' in entry else None,
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entry['uops'] if 'uops' in entry else None,
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)
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def add_port(self, port):
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if port not in self._data['ports']:
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self._data['ports'].append(port)
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def get_ISA(self):
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return self._data['isa'].lower()
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def get_arch(self):
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return self._data['arch_code'].lower()
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def get_ports(self):
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return self._data['ports']
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def has_hidden_loads(self):
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if 'hidden_loads' in self._data:
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return self._data['hidden_loads']
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return False
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def get_load_latency(self, reg_type):
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return self._data['load_latency'][reg_type]
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def get_load_throughput(self, memory):
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ld_tp = [m for m in self._data['load_throughput'] if self._match_mem_entries(memory, m)]
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if len(ld_tp) > 0:
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return ld_tp[0]['port_pressure']
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return self._data['load_throughput_default']
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def get_store_latency(self, reg_type):
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# assume 0 for now, since load-store-dependencies currently not detectable
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return 0
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def get_store_throughput(self, memory):
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st_tp = [m for m in self._data['store_throughput'] if self._match_mem_entries(memory, m)]
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if len(st_tp) > 0:
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return st_tp[0]['port_pressure']
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return self._data['store_throughput_default']
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def _match_mem_entries(self, mem, i_mem):
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if self._data['isa'].lower() == 'aarch64':
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return self._is_AArch64_mem_type(i_mem, mem)
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if self._data['isa'].lower() == 'x86':
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return self._is_x86_mem_type(i_mem, mem)
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def get_data_ports(self):
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data_port = re.compile(r'^[0-9]+D$')
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data_ports = [x for x in filter(data_port.match, self._data['ports'])]
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return data_ports
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@staticmethod
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def get_full_instruction_name(instruction_form):
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operands = []
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for op in instruction_form['operands']:
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op_attrs = [
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y + ':' + str(op[y])
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for y in list(filter(lambda x: True if x != 'class' else False, op))
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]
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operands.append('{}({})'.format(op['class'], ','.join(op_attrs)))
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return '{} {}'.format(instruction_form['name'], ','.join(operands))
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@staticmethod
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def get_isa_for_arch(arch):
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arch_dict = {
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'tx2': 'aarch64',
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'zen1': 'x86',
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'snb': 'x86',
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'ivb': 'x86',
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'hsw': 'x86',
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'bdw': 'x86',
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'skl': 'x86',
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'skx': 'x86',
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'csx': 'x86',
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'wsm': 'x86',
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'nhm': 'x86',
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'kbl': 'x86',
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'cnl': 'x86',
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'cfl': 'x86',
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'zen+': 'x86',
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}
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arch = arch.lower()
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if arch in arch_dict:
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return arch_dict[arch].lower()
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else:
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raise ValueError("Unknown architecture {!r}.".format(arch))
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def dump(self, stream=None):
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# Replace instruction form's port_pressure with styled version for RoundtripDumper
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formatted_instruction_forms = deepcopy(self._data['instruction_forms'])
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for instruction_form in formatted_instruction_forms:
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if instruction_form['port_pressure'] is not None:
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cs = ruamel.yaml.comments.CommentedSeq(instruction_form['port_pressure'])
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cs.fa.set_flow_style()
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instruction_form['port_pressure'] = cs
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# Replace load_throughput with styled version for RoundtripDumper
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formatted_load_throughput = []
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for lt in self._data['load_throughput']:
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cm = ruamel.yaml.comments.CommentedMap(lt)
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cm.fa.set_flow_style()
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formatted_load_throughput.append(cm)
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# Create YAML object
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yaml = self._create_yaml_object()
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if not stream:
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stream = StringIO()
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yaml.dump(
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{
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k: v
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for k, v in self._data.items()
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if k not in ['instruction_forms', 'load_throughput']
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},
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stream,
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)
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yaml.dump({'load_throughput': formatted_load_throughput}, stream)
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yaml.dump({'instruction_forms': formatted_instruction_forms}, stream)
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if isinstance(stream, StringIO):
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return stream.getvalue()
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######################################################
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def _get_key(self, name, operands):
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key_string = name.lower() + '-'
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if operands is None:
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return key_string[:-1]
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key_string += '_'.join([self._get_operand_hash(op) for op in operands])
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return key_string
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def _convert_to_dict(self, instruction_forms):
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instruction_dict = {}
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for instruction_form in instruction_forms:
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instruction_dict[
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self._get_key(
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instruction_form['name'],
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instruction_form['operands'] if 'operands' in instruction_form else None,
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)
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] = instruction_form
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return instruction_dict
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def _get_operand_hash(self, operand):
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operand_string = ''
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if 'class' in operand:
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# DB entry
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opclass = operand['class']
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else:
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# parsed instruction
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opclass = list(operand.keys())[0]
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operand = operand[opclass]
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if opclass == 'immediate':
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# Immediate
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operand_string += 'i'
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elif opclass == 'register':
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# Register
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if 'prefix' in operand:
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operand_string += operand['prefix']
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operand_string += operand['shape'] if 'shape' in operand else ''
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elif 'name' in operand:
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operand_string += 'r' if operand['name'] == 'gpr' else operand['name'][0]
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elif opclass == 'memory':
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# Memory
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operand_string += 'm'
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operand_string += 'b' if operand['base'] is not None else ''
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operand_string += 'o' if operand['offset'] is not None else ''
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operand_string += 'i' if operand['index'] is not None else ''
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operand_string += (
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's' if operand['scale'] == self.WILDCARD or operand['scale'] > 1 else ''
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)
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if 'pre-indexed' in operand:
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operand_string += 'r' if operand['pre-indexed'] else ''
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operand_string += 'p' if operand['post-indexed'] else ''
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return operand_string
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def _create_db_operand_aarch64(operand):
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if operand == 'i':
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return {'class': 'immediate', 'imd': 'int'}
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elif operand in 'wxbhsdq':
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return {'class': 'register', 'prefix': operand}
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elif operand.startswith('v'):
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return {'class': 'register', 'prefix': 'v', 'shape': operand[1:2]}
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elif operand.startswith('m'):
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return {
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'class': 'memory',
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'base': 'x' if 'b' in operand else None,
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'offset': 'imd' if 'o' in operand else None,
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'index': 'gpr' if 'i' in operand else None,
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'scale': 8 if 's' in operand else 1,
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'pre-indexed': True if 'r' in operand else False,
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'post-indexed': True if 'p' in operand else False,
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}
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else:
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raise ValueError('Parameter {} is not a valid operand code'.format(operand))
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def _create_db_operand_x86(operand):
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if operand == 'r':
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return {'class': 'register', 'name': 'gpr'}
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elif operand in 'xyz':
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return {'class': 'register', 'name': operand + 'mm'}
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elif operand == 'i':
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return {'class': 'immediate', 'imd': 'int'}
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elif operand.startswith('m'):
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return {
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'class': 'memory',
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'base': 'gpr' if 'b' in operand else None,
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'offset': 'imd' if 'o' in operand else None,
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'index': 'gpr' if 'i' in operand else None,
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'scale': 8 if 's' in operand else 1,
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}
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else:
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raise ValueError('Parameter {} is not a valid operand code'.format(operand))
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def _check_for_duplicate(self, name, operands):
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matches = [
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instruction_form
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for instruction_form in self._data['instruction_forms']
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if instruction_form['name'].lower() == name.lower()
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and self._match_operands(instruction_form['operands'], operands)
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]
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if len(matches) > 1:
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return True
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return False
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def _match_operands(self, i_operands, operands):
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operands_ok = True
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if len(operands) != len(i_operands):
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return False
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for idx, operand in enumerate(operands):
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i_operand = i_operands[idx]
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operands_ok = operands_ok and self._check_operands(i_operand, operand)
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if operands_ok:
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return True
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else:
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return False
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def _check_operands(self, i_operand, operand):
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# check for wildcard
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if self.WILDCARD in operand:
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if (
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'class' in i_operand
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and i_operand['class'] == 'register'
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or 'register' in i_operand
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):
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return True
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else:
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return False
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if self._data['isa'].lower() == 'aarch64':
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return self._check_AArch64_operands(i_operand, operand)
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if self._data['isa'].lower() == 'x86':
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return self._check_x86_operands(i_operand, operand)
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def _check_AArch64_operands(self, i_operand, operand):
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if 'class' in operand:
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# compare two DB entries
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return self._compare_db_entries(i_operand, operand)
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# register
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if 'register' in operand:
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if i_operand['class'] != 'register':
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return False
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return self._is_AArch64_reg_type(i_operand, operand['register'])
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# memory
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if 'memory' in operand:
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if i_operand['class'] != 'memory':
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return False
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return self._is_AArch64_mem_type(i_operand, operand['memory'])
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# immediate
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if 'value' in operand or ('immediate' in operand and 'value' in operand['immediate']):
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return i_operand['class'] == 'immediate' and i_operand['imd'] == 'int'
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if 'float' in operand or ('immediate' in operand and 'float' in operand['immediate']):
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return i_operand['class'] == 'immediate' and i_operand['imd'] == 'float'
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if 'double' in operand or ('immediate' in operand and 'double' in operand['immediate']):
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return i_operand['class'] == 'immediate' and i_operand['imd'] == 'double'
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if 'identifier' in operand or (
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'immediate' in operand and 'identifier' in operand['immediate']
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):
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return i_operand['class'] == 'identifier'
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# prefetch option
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if 'prfop' in operand:
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return i_operand['class'] == 'prfop'
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# no match
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return False
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def _check_x86_operands(self, i_operand, operand):
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if 'class' in operand:
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# compare two DB entries
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return self._compare_db_entries(i_operand, operand)
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# register
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if 'register' in operand:
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if i_operand['class'] != 'register':
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return False
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return self._is_x86_reg_type(i_operand['name'], operand['register'])
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# memory
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if 'memory' in operand:
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if i_operand['class'] != 'memory':
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return False
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return self._is_x86_mem_type(i_operand, operand['memory'])
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# immediate
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if 'immediate' in operand or 'value' in operand:
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return i_operand['class'] == 'immediate' and i_operand['imd'] == 'int'
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# identifier (e.g., labels)
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if 'identifier' in operand:
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return i_operand['class'] == 'identifier'
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def _compare_db_entries(self, operand_1, operand_2):
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operand_attributes = list(
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filter(lambda x: True if x != 'source' and x != 'destination' else False, operand_1)
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)
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for key in operand_attributes:
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try:
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if operand_1[key] != operand_2[key]:
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return False
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except KeyError:
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return False
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return True
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def _is_AArch64_reg_type(self, i_reg, reg):
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if reg['prefix'] != i_reg['prefix']:
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return False
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if 'shape' in reg:
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if 'shape' in i_reg and reg['shape'] == i_reg['shape']:
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return True
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return False
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return True
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def _is_x86_reg_type(self, i_reg_name, reg):
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# differentiate between vector registers (mm, xmm, ymm, zmm) and others (gpr)
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parser_x86 = ParserX86ATT()
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if parser_x86.is_vector_register(reg):
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if ''.join([l for l in reg['name'] if not l.isdigit()])[-2:] == i_reg_name[-2:]:
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return True
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else:
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if i_reg_name == 'gpr':
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return True
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return False
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def _is_AArch64_mem_type(self, i_mem, mem):
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if (
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# check base
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(
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(mem['base'] is None and i_mem['base'] is None)
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or i_mem['base'] == self.WILDCARD
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or mem['base']['prefix'] == i_mem['base']
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)
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# check offset
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and (
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mem['offset'] == i_mem['offset']
|
|
or i_mem['offset'] == self.WILDCARD
|
|
or (
|
|
mem['offset'] is not None
|
|
and 'identifier' in mem['offset']
|
|
and i_mem['offset'] == 'identifier'
|
|
)
|
|
or (
|
|
mem['offset'] is not None
|
|
and 'value' in mem['offset']
|
|
and i_mem['offset'] == 'imd'
|
|
)
|
|
)
|
|
# check index
|
|
and (
|
|
mem['index'] == i_mem['index']
|
|
or i_mem['index'] == self.WILDCARD
|
|
or (
|
|
mem['index'] is not None
|
|
and 'prefix' in mem['index']
|
|
and mem['index']['prefix'] == i_mem['index']
|
|
)
|
|
)
|
|
# check scale
|
|
and (
|
|
mem['scale'] == i_mem['scale']
|
|
or i_mem['scale'] == self.WILDCARD
|
|
or (mem['scale'] != 1 and i_mem['scale'] != 1)
|
|
)
|
|
# check pre-indexing
|
|
and (
|
|
i_mem['pre-indexed'] == self.WILDCARD
|
|
or ('pre_indexed' in mem) == (i_mem['pre-indexed'])
|
|
)
|
|
# check post-indexing
|
|
and (
|
|
i_mem['post-indexed'] == self.WILDCARD
|
|
or ('post_indexed' in mem) == (i_mem['post-indexed'])
|
|
)
|
|
):
|
|
return True
|
|
return False
|
|
|
|
def _is_x86_mem_type(self, i_mem, mem):
|
|
if (
|
|
# check base
|
|
(
|
|
(mem['base'] is None and i_mem['base'] is None)
|
|
or i_mem['base'] == self.WILDCARD
|
|
or self._is_x86_reg_type(i_mem['base'], mem['base'])
|
|
)
|
|
# check offset
|
|
and (
|
|
mem['offset'] == i_mem['offset']
|
|
or i_mem['offset'] == self.WILDCARD
|
|
or (
|
|
mem['offset'] is not None
|
|
and 'identifier' in mem['offset']
|
|
and i_mem['offset'] == 'identifier'
|
|
)
|
|
or (
|
|
mem['offset'] is not None
|
|
and 'value' in mem['offset']
|
|
and (
|
|
i_mem['offset'] == 'imd'
|
|
or (i_mem['offset'] is None and mem['offset']['value'] == '0')
|
|
)
|
|
)
|
|
or (
|
|
mem['offset'] is not None
|
|
and 'identifier' in mem['offset']
|
|
and i_mem['offset'] == 'id'
|
|
)
|
|
)
|
|
# check index
|
|
and (
|
|
mem['index'] == i_mem['index']
|
|
or i_mem['index'] == self.WILDCARD
|
|
or (
|
|
mem['index'] is not None
|
|
and 'name' in mem['index']
|
|
and self._is_x86_reg_type(i_mem['index'], mem['index'])
|
|
)
|
|
)
|
|
# check scale
|
|
and (
|
|
mem['scale'] == i_mem['scale']
|
|
or i_mem['scale'] == self.WILDCARD
|
|
or (mem['scale'] != 1 and i_mem['scale'] != 1)
|
|
)
|
|
):
|
|
return True
|
|
return False
|
|
|
|
def _create_yaml_object(self):
|
|
yaml_obj = ruamel.yaml.YAML()
|
|
yaml_obj.representer.add_representer(type(None), self.__represent_none)
|
|
yaml_obj.default_flow_style = None
|
|
yaml_obj.width = 120
|
|
yaml_obj.representer.ignore_aliases = lambda *args: True
|
|
return yaml_obj
|
|
|
|
def __represent_none(self, yaml_obj, data):
|
|
return yaml_obj.represent_scalar(u'tag:yaml.org,2002:null', u'~')
|