mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2026-01-05 02:30:08 +01:00
307 lines
11 KiB
Python
Executable File
307 lines
11 KiB
Python
Executable File
#!/usr/bin/env python3
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import os
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import re
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from ruamel import yaml
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from osaca.parser import ParserX86ATT
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class MachineModel(object):
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def __init__(self, arch=None, path_to_yaml=None):
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if not arch and not path_to_yaml:
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raise ValueError('Either arch or path_to_yaml required.')
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if arch and path_to_yaml:
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raise ValueError('Only one of arch and path_to_yaml is allowed.')
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self._path = path_to_yaml
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self._arch = arch
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if arch:
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self._arch = arch.lower()
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try:
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with open(self._find_file(self._arch), 'r') as f:
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self._data = yaml.load(f, Loader=yaml.Loader)
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except AssertionError:
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raise ValueError(
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'Cannot find specified architecture. Make sure the machine file exists.'
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)
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elif path_to_yaml:
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try:
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assert os.path.exists(self._path)
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with open(self._path, 'r') as f:
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self._data = yaml.load(f, Loader=yaml.Loader)
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except (AssertionError, FileNotFoundError):
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raise ValueError(
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'Cannot find specified path to YAML file. Make sure the machine file exists.'
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)
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def _find_file(self, name):
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data_dir = os.path.expanduser('~/.osaca/data')
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name = os.path.join(data_dir, name + '.yml')
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assert os.path.exists(name)
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return name
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def __getitem__(self, key):
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"""Return configuration entry."""
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return self._data[key]
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def __contains__(self, key):
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"""Return true if configuration key is present."""
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return key in self._data
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######################################################
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def get_instruction(self, name, operands):
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if name is None:
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return None
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try:
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return next(
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instruction_form
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for instruction_form in self._data['instruction_forms']
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if instruction_form['name'].lower() == name.lower()
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and self._match_operands(instruction_form['operands'], operands)
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)
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except StopIteration:
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return None
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except TypeError:
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print('\nname: {}\noperands: {}'.format(name, operands))
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raise TypeError
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def get_ISA(self):
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return self._data['isa']
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def get_arch(self):
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return self._data['arch_code']
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def get_ports(self):
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return self._data['ports']
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def has_hidden_loads(self):
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if 'hidden_loads' in self._data:
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return self._data['hidden_loads']
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return False
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def get_load_latency(self, reg_type):
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return self._data['load_latency'][reg_type]
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def get_load_throughput(self, memory):
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ld_tp = [m for m in self._data['load_throughput'] if self._match_mem_entries(memory, m)]
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if len(ld_tp) > 0:
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return ld_tp[0]['port_pressure']
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return None
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def _match_mem_entries(self, mem, i_mem):
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if self._data['isa'].lower() == 'aarch64':
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return self._is_AArch64_mem_type(i_mem, mem)
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if self._data['isa'].lower() == 'x86':
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return self._is_x86_mem_type(i_mem, mem)
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def get_data_ports(self):
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data_port = re.compile(r'^[0-9]+D$')
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data_ports = [x for x in filter(data_port.match, self._data['ports'])]
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return data_ports
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@staticmethod
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def get_isa_for_arch(arch):
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arch_dict = {
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'vulcan': 'aarch64',
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'zen1': 'x86',
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'snb': 'x86',
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'ivb': 'x86',
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'hsw': 'x86',
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'bdw': 'x86',
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'skl': 'x86',
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'skx': 'x86',
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'csx': 'x86',
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}
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arch = arch.lower()
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if arch in arch_dict:
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return arch_dict[arch].lower()
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return None
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######################################################
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def _check_for_duplicate(self, name, operands):
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matches = [
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instruction_form
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for instruction_form in self._data['instruction_forms']
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if instruction_form['name'].lower() == name.lower()
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and self._match_operands(instruction_form['operands'], operands)
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]
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if len(matches) > 1:
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return True
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return False
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def _match_operands(self, i_operands, operands):
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if isinstance(operands, dict):
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operands = operands['operand_list']
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operands_ok = True
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if len(operands) != len(i_operands):
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return False
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for idx, operand in enumerate(operands):
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i_operand = i_operands[idx]
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operands_ok = operands_ok and self._check_operands(i_operand, operand)
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if operands_ok:
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return True
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else:
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return False
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def _check_operands(self, i_operands, operands):
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if self._data['isa'].lower() == 'aarch64':
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return self._check_AArch64_operands(i_operands, operands)
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if self._data['isa'].lower() == 'x86':
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return self._check_x86_operands(i_operands, operands)
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def _check_AArch64_operands(self, i_operand, operand):
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if 'class' in operand:
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# compare two DB entries
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return self._compare_db_entries(i_operand, operand)
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# register
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if 'register' in operand:
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if i_operand['class'] != 'register':
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return False
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return self._is_AArch64_reg_type(i_operand, operand['register'])
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# memory
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if 'memory' in operand:
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if i_operand['class'] != 'memory':
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return False
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return self._is_AArch64_mem_type(i_operand, operand['memory'])
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# immediate
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if 'value' in operand or ('immediate' in operand and 'value' in operand['immediate']):
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return i_operand['class'] == 'immediate' and i_operand['imd'] == 'int'
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if 'float' in operand or ('immediate' in operand and 'float' in operand['immediate']):
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return i_operand['class'] == 'immediate' and i_operand['imd'] == 'float'
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if 'double' in operand or ('immediate' in operand and 'double' in operand['immediate']):
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return i_operand['class'] == 'immediate' and i_operand['imd'] == 'double'
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if 'identifier' in operand or (
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'immediate' in operand and 'identifier' in operand['immediate']
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):
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return i_operand['class'] == 'identifier'
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# prefetch option
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if 'prfop' in operand:
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return i_operand['class'] == 'prfop'
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# no match
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return False
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def _check_x86_operands(self, i_operand, operand):
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if 'class' in operand:
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# compare two DB entries
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return self._compare_db_entries(i_operand, operand)
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# register
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if 'register' in operand:
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if i_operand['class'] != 'register':
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return False
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return self._is_x86_reg_type(i_operand['name'], operand['register'])
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# memory
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if 'memory' in operand:
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if i_operand['class'] != 'memory':
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return False
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return self._is_x86_mem_type(i_operand, operand['memory'])
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# immediate
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if 'immediate' in operand or 'value' in operand:
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return i_operand['class'] == 'immediate' and i_operand['imd'] == 'int'
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# identifier (e.g., labels)
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if 'identifier' in operand:
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return i_operand['class'] == 'identifier'
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def _compare_db_entries(self, operand_1, operand_2):
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operand_attributes = list(
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filter(lambda x: True if x != 'source' and x != 'destination' else False, operand_1)
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)
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for key in operand_attributes:
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try:
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if operand_1[key] != operand_2[key]:
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return False
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except KeyError:
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return False
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return True
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def _is_AArch64_reg_type(self, i_reg, reg):
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if reg['prefix'] != i_reg['prefix']:
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return False
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if 'shape' in reg:
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if 'shape' in i_reg and reg['shape'] == i_reg['shape']:
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return True
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return False
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return True
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def _is_x86_reg_type(self, i_reg_name, reg):
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# differentiate between vector registers (xmm, ymm, zmm) and others (gpr)
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parser_x86 = ParserX86ATT()
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if parser_x86.is_vector_register(reg):
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if reg['name'][0:3] == i_reg_name:
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return True
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else:
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if i_reg_name == 'gpr':
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return True
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return False
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def _is_AArch64_mem_type(self, i_mem, mem):
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if (
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# check base
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mem['base']['prefix'] == i_mem['base']
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# check offset
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and (
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mem['offset'] == i_mem['offset']
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or (
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mem['offset'] is not None
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and 'identifier' in mem['offset']
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and i_mem['offset'] == 'identifier'
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)
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or (
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mem['offset'] is not None
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and 'value' in mem['offset']
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and i_mem['offset'] == 'imd'
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)
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)
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# check index
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and (
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mem['index'] == i_mem['index']
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or (
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mem['index'] is not None
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and 'prefix' in mem['index']
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and mem['index']['prefix'] == i_mem['index']
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)
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)
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and (mem['scale'] == i_mem['scale'] or (mem['scale'] != 1 and i_mem['scale'] != 1))
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and (('pre_indexed' in mem) == (i_mem['pre-indexed']))
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and (('post_indexed' in mem) == (i_mem['post-indexed']))
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):
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return True
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return False
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def _is_x86_mem_type(self, i_mem, mem):
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if (
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# check base
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self._is_x86_reg_type(i_mem['base'], mem['base'])
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# check offset
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and (
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mem['offset'] == i_mem['offset']
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or (
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mem['offset'] is not None
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and 'identifier' in mem['offset']
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and i_mem['offset'] == 'identifier'
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)
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or (
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mem['offset'] is not None
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and 'value' in mem['offset']
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and (
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i_mem['offset'] == 'imd'
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or (i_mem['offset'] is None and mem['offset']['value'] == '0')
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)
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)
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)
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# check index
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and (
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mem['index'] == i_mem['index']
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or (
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mem['index'] is not None
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and 'name' in mem['index']
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and self._is_x86_reg_type(i_mem['index'], mem['index'])
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)
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)
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and (mem['scale'] == i_mem['scale'] or (mem['scale'] != 1 and i_mem['scale'] != 1))
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):
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return True
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return False
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