mirror of
https://github.com/RRZE-HPC/OSACA.git
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301 lines
11 KiB
Python
Executable File
301 lines
11 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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import os.path
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import sys
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import xml.etree.ElementTree as ET
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from distutils.version import StrictVersion
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from osaca.parser import get_parser
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from osaca.semantics import MachineModel
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intel_archs = [
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'CON',
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'WOL',
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'NHM',
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'WSM',
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'SNB',
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'IVB',
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'HSW',
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'BDW',
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'SKL',
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'SKX',
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'KBL',
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'CFL',
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'CNL',
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'ICL',
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]
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amd_archs = ['ZEN1', 'ZEN+', 'ZEN2']
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def port_pressure_from_tag_attributes(attrib):
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# '1*p015+1*p1+1*p23+1*p4+3*p5' ->
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# [[1, '015'], [1, '1'], [1, '23'], [1, '4'], [3, '5']]
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port_occupation = []
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for p in attrib['ports'].split('+'):
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cycles, ports = p.split('*')
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ports = ports.lstrip('p')
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ports = ports.lstrip('FP')
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port_occupation.append([int(cycles), ports])
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# Also consider div on DIV pipeline
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if 'div_cycles' in attrib:
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port_occupation.append([int(attrib['div_cycles']), ['DIV']])
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return port_occupation
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def extract_paramters(instruction_tag, parser, isa):
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# Extract parameter components
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parameters = [] # used to store string representations
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parameter_tags = sorted(instruction_tag.findall("operand"), key=lambda p: int(p.attrib['idx']))
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for parameter_tag in parameter_tags:
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parameter = {}
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# Ignore parameters with suppressed=1
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if int(parameter_tag.attrib.get('suppressed', '0')):
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continue
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p_type = parameter_tag.attrib['type']
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if p_type == 'imm':
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parameter['class'] = 'immediate'
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parameter['imd'] = 'int'
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parameters.append(parameter)
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elif p_type == 'mem':
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parameter['class'] = 'memory'
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parameter['base'] = "*"
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parameter['offset'] = "*"
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parameter['index'] = "*"
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parameter['scale'] = "*"
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parameters.append(parameter)
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elif p_type == 'reg':
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parameter['class'] = 'register'
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possible_regs = [parser.parse_register('%' + r) for r in parameter_tag.text.split(',')]
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if possible_regs[0] is None:
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raise ValueError(
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'Unknown register type for {} with {}.'.format(
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parameter_tag.attrib, parameter_tag.text
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)
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)
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if isa == 'x86':
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if parser.is_vector_register(possible_regs[0]['register']):
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possible_regs[0]['register']['name'] = possible_regs[0]['register'][
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'name'
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].lower()[:3]
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if 'mask' in possible_regs[0]['register']:
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possible_regs[0]['register']['mask'] = True
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else:
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possible_regs[0]['register']['name'] = 'gpr'
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elif isa == 'aarch64':
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del possible_regs['register']['name']
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for key in possible_regs[0]['register']:
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parameter[key] = possible_regs[0]['register'][key]
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parameters.append(parameter)
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elif p_type == 'relbr':
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parameter['class'] = 'identifier'
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parameters.append(parameter)
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elif p_type == 'agen':
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parameter['class'] = 'memory'
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parameter['base'] = "*"
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parameter['offset'] = "*"
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parameter['index'] = "*"
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parameter['scale'] = "*"
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parameters.append(parameter)
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else:
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raise ValueError("Unknown paramter type {}".format(parameter_tag.attrib))
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return parameters
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def extract_model(tree, arch, skip_mem=True):
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try:
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isa = MachineModel.get_isa_for_arch(arch)
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except Exception:
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print("Skipping...", file=sys.stderr)
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return None
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mm = MachineModel(isa=isa)
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parser = get_parser(isa)
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for instruction_tag in tree.findall('.//instruction'):
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ignore = False
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mnemonic = instruction_tag.attrib['asm']
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iform = instruction_tag.attrib['iform']
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# skip any mnemonic which contain spaces (e.g., "REX CRC32")
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if ' ' in mnemonic:
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continue
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# Extract parameter components
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try:
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parameters = extract_paramters(instruction_tag, parser, isa)
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if isa == 'x86':
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parameters.reverse()
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except ValueError as e:
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print(e, file=sys.stderr)
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# Extract port occupation, throughput and latency
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port_pressure, throughput, latency, uops = [], None, None, None
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arch_tag = instruction_tag.find('architecture[@name="' + arch.upper() + '"]')
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if arch_tag is None:
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continue
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# skip any instructions without port utilization
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if not any(['ports' in x.attrib for x in arch_tag.findall('measurement')]):
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print("Couldn't find port utilization, skip: ", iform, file=sys.stderr)
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continue
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# skip if computed and measured TP don't match
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if not [x.attrib['TP_ports'] == x.attrib['TP'] for x in arch_tag.findall('measurement')][
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0
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]:
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print(
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"Calculated TP from port utilization doesn't match TP, skip: ",
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iform,
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file=sys.stderr,
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)
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continue
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# skip if instruction contains memory operand
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if skip_mem and any(
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[x.attrib['type'] == 'mem' for x in instruction_tag.findall('operand')]
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):
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print("Contains memory operand, skip: ", iform, file=sys.stderr)
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continue
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# We collect all measurement and IACA information and compare them later
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for measurement_tag in arch_tag.iter('measurement'):
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if 'TP_ports' in measurement_tag.attrib:
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throughput = measurement_tag.attrib['TP_ports']
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else:
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throughput = (
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measurement_tag.attrib['TP'] if 'TP' in measurement_tag.attrib else None
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)
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uops = (
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int(measurement_tag.attrib['uops']) if 'uops' in measurement_tag.attrib else None
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)
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if 'ports' in measurement_tag.attrib:
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port_pressure.append(port_pressure_from_tag_attributes(measurement_tag.attrib))
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latencies = [
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int(l_tag.attrib['cycles'])
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for l_tag in measurement_tag.iter('latency')
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if 'cycles' in l_tag.attrib
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]
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if len(latencies) == 0:
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latencies = [
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int(l_tag.attrib['max_cycles'])
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for l_tag in measurement_tag.iter('latency')
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if 'max_cycles' in l_tag.attrib
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]
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if latencies[1:] != latencies[:-1]:
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print(
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"Contradicting latencies found, using smallest:",
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iform,
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latencies,
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file=sys.stderr,
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)
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if latencies:
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latency = min(latencies)
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if ignore:
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continue
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# Ordered by IACA version (newest last)
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for iaca_tag in sorted(
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arch_tag.iter('IACA'), key=lambda i: StrictVersion(i.attrib['version'])
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):
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if 'ports' in iaca_tag.attrib:
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port_pressure.append(port_pressure_from_tag_attributes(iaca_tag.attrib))
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# Check if all are equal
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if port_pressure:
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if port_pressure[1:] != port_pressure[:-1]:
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print("Contradicting port occupancies, using latest IACA:", iform, file=sys.stderr)
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port_pressure = port_pressure[-1]
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else:
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# print("No data available for this architecture:", mnemonic, file=sys.stderr)
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continue
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# Adding Intel's 2D and 3D pipelines on Intel µarchs, without Ice Lake:
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if arch.upper() in intel_archs and not arch.upper() in ['ICL']:
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if any([p['class'] == 'memory' for p in parameters]):
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# We have a memory parameter, if ports 2 & 3 are present, also add 2D & 3D
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# TODO remove port7 on 'hsw' onward and split entries depending on addressing mode
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port_23 = False
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port_4 = False
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for i, pp in enumerate(port_pressure):
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if '2' in pp[1] and '3' in pp[1]:
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port_23 = True
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if '4' in pp[1]:
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port_4 = True
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# Add (X, ['2D', '3D']) if load ports (2 & 3) are used, but not the store port (4)
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# X = 2 on SNB and IVB IFF used in combination with ymm register, otherwise X = 1
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if arch.upper() in ['SNB', 'IVB'] and \
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any([p['class'] == 'register' and p['name'] == 'ymm' for p in parameters]):
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data_port_throughput = 2
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else:
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data_port_throughput = 1
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if port_23 and not port_4:
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port_pressure.append((data_port_throughput, ['2D', '3D']))
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# Add missing ports:
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for ports in [pp[1] for pp in port_pressure]:
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for p in ports:
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mm.add_port(p)
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throughput = max(mm.average_port_pressure(port_pressure))
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mm.set_instruction(mnemonic, parameters, latency, port_pressure, throughput, uops)
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# TODO eliminate entries which could be covered by automatic load / store expansion
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return mm
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def rhs_comment(uncommented_string, comment):
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max_length = max([len(l) for l in uncommented_string.split('\n')])
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commented_string = ""
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for l in uncommented_string.split('\n'):
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commented_string += ("{:<" + str(max_length) + "} # {}\n").format(l, comment)
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return commented_string
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def architectures(tree):
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return set([a.attrib['name'] for a in tree.findall('.//architecture')])
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def main():
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parser = argparse.ArgumentParser()
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parser.add_argument('xml', help='path of instructions.xml from http://uops.info')
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parser.add_argument(
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'arch',
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nargs='?',
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help='architecture to extract, use IACA abbreviations (e.g., SNB). '
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'if not given, all will be extracted and saved to file in CWD.',
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)
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parser.add_argument(
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'--mem',
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dest='skip_mem',
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action='store_false',
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help='add instruction forms including memory addressing operands, which are '
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'skipped by default'
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)
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args = parser.parse_args()
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basename = os.path.basename(__file__)
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tree = ET.parse(args.xml)
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print('# Available architectures:', ', '.join(architectures(tree)))
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if args.arch:
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print('# Chosen architecture: {}'.format(args.arch))
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model = extract_model(tree, args.arch, args.skip_mem)
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if model is not None:
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print(
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rhs_comment(
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model.dump(), "uops.info import"
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)
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)
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else:
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for arch in architectures(tree):
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print(arch, end='')
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model = extract_model(tree, arch.lower(), args.skip_mem)
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if model:
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model_string = rhs_comment(model.dump(), basename + " " + arch)
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with open('{}.yml'.format(arch.lower()), 'w') as f:
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f.write(model_string)
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print('.')
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if __name__ == '__main__':
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main()
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