mirror of
https://github.com/RRZE-HPC/OSACA.git
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604 lines
26 KiB
Python
604 lines
26 KiB
Python
#!/usr/bin/env python3
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import copy
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import time
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from itertools import chain
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from multiprocessing import Manager, Process, cpu_count
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import networkx as nx
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from osaca.semantics import INSTR_FLAGS, ArchSemantics, MachineModel
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from osaca.parser.memory import MemoryOperand
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from osaca.parser.register import RegisterOperand
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from osaca.parser.immediate import ImmediateOperand
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from osaca.parser.flag import FlagOperand
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class KernelDG(nx.DiGraph):
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# threshold for checking dependency graph sequential or in parallel
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INSTRUCTION_THRESHOLD = 50
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def __init__(
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self,
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parsed_kernel,
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parser,
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hw_model: MachineModel,
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semantics: ArchSemantics,
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timeout=10,
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flag_dependencies=False,
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):
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self.timed_out = False
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self.kernel = parsed_kernel
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self.parser = parser
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self.model = hw_model
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self.arch_sem = semantics
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self.dg = self.create_DG(self.kernel, flag_dependencies)
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self.loopcarried_deps = self.check_for_loopcarried_dep(
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self.kernel, timeout, flag_dependencies
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)
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@classmethod
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def _extend_path(cls, dst_list, kernel, dg, offset):
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for instr in kernel:
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generator_path = nx.algorithms.simple_paths.all_simple_paths(
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dg, instr.line_number, instr.line_number + offset
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)
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tmp_list = list(generator_path)
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dst_list.extend(tmp_list)
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# print('Thread [{}-{}] done'.format(kernel[0]['line_number'], kernel[-1]['line_number']))
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def create_DG(self, kernel, flag_dependencies=False):
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"""
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Create directed graph from given kernel
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:param kernel: Parsed asm kernel with assigned semantic information
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:type kerne: list
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:param flag_dependencies: indicating if dependencies of flags should be considered,
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defaults to `False`
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:type flag_dependencies: boolean, optional
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:returns: :class:`~nx.DiGraph` -- directed graph object
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"""
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# 1. go through kernel instruction forms and add them as node attribute
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# 2. find edges (to dependend further instruction)
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# 3. get LT value and set as edge weight
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dg = nx.DiGraph()
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for i, instruction_form in enumerate(kernel):
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dg.add_node(instruction_form.line_number)
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dg.nodes[instruction_form.line_number]["instruction_form"] = instruction_form
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# add load as separate node if existent
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if (
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INSTR_FLAGS.HAS_LD in instruction_form.flags
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and INSTR_FLAGS.LD not in instruction_form.flags
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):
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# add new node
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dg.add_node(instruction_form.line_number + 0.1)
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dg.nodes[instruction_form.line_number + 0.1]["instruction_form"] = instruction_form
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# and set LD latency as edge weight
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dg.add_edge(
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instruction_form.line_number + 0.1,
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instruction_form.line_number,
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latency=instruction_form.latency - instruction_form.latency_wo_load,
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)
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for dep, dep_flags in self.find_depending(
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instruction_form, kernel[i + 1 :], flag_dependencies
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):
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# print(instruction_form.line_number,"\t",dep.line_number,"\n")
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edge_weight = (
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instruction_form.latency
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if "mem_dep" in dep_flags or instruction_form.latency_wo_load is None
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else instruction_form.latency_wo_load
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)
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if "storeload_dep" in dep_flags and self.model is not None:
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edge_weight += self.model.get("store_to_load_forward_latency", 0)
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if "p_indexed" in dep_flags and self.model is not None:
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edge_weight = self.model.get("p_index_latency", 1)
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dg.add_edge(
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instruction_form.line_number,
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dep.line_number,
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latency=edge_weight,
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)
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dg.nodes[dep.line_number]["instruction_form"] = dep
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return dg
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def check_for_loopcarried_dep(self, kernel, timeout=10, flag_dependencies=False):
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"""
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Try to find loop-carried dependencies in given kernel.
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:param kernel: Parsed asm kernel with assigned semantic information
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:type kernel: list
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:param timeout: Timeout in seconds for parallel execution, defaults
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to `10`. Set to `0` for no timeout
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:type timeout: int
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:returns: `dict` -- dependency dictionary with all cyclic LCDs
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"""
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# increase line number for second kernel loop
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offset = max(1000, max([i.line_number for i in kernel]))
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tmp_kernel = [] + kernel
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for orig_iform in kernel:
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temp_iform = copy.copy(orig_iform)
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temp_iform.line_number += offset
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tmp_kernel.append(temp_iform)
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# get dependency graph
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dg = self.create_DG(tmp_kernel, flag_dependencies)
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# build cyclic loop-carried dependencies
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loopcarried_deps = []
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all_paths = []
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klen = len(kernel)
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if klen >= self.INSTRUCTION_THRESHOLD:
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# parallel execution with static scheduling
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num_cores = cpu_count()
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workload = int((klen - 1) / num_cores) + 1
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starts = [tid * workload for tid in range(num_cores)]
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ends = [min((tid + 1) * workload, klen) for tid in range(num_cores)]
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instrs = [kernel[s:e] for s, e in zip(starts, ends)]
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with Manager() as manager:
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all_paths = manager.list()
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processes = [
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Process(
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target=KernelDG._extend_path,
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args=(all_paths, instr_section, dg, offset),
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)
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for instr_section in instrs
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]
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for p in processes:
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p.start()
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if timeout == -1:
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# no timeout
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for p in processes:
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p.join()
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else:
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start_time = time.time()
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while time.time() - start_time <= timeout:
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if any(p.is_alive() for p in processes):
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time.sleep(0.2)
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else:
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# all procs done
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for p in processes:
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p.join()
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break
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else:
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self.timed_out = True
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# terminate running processes
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for p in processes:
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if p.is_alive():
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p.kill()
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p.join()
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all_paths = list(all_paths)
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else:
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# sequential execution to avoid overhead when analyzing smaller kernels
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for instr in kernel:
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all_paths.extend(
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nx.algorithms.simple_paths.all_simple_paths(
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dg, instr.line_number, instr.line_number + offset
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)
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)
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paths_set = set()
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for path in all_paths:
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lat_sum = 0.0
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# extend path by edge bound latencies (e.g., store-to-load latency)
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lat_path = []
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for s, d in nx.utils.pairwise(path):
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edge_lat = dg.edges[s, d]["latency"]
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# map source node back to original line numbers
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if s > offset:
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s -= offset
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lat_path.append((s, edge_lat))
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lat_sum += edge_lat
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if d > offset:
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d -= offset
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lat_path.sort()
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# Ignore duplicate paths which differ only in the root node
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if tuple(lat_path) in paths_set:
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continue
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paths_set.add(tuple(lat_path))
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loopcarried_deps.append((lat_sum, lat_path))
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loopcarried_deps.sort(reverse=True)
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# map lcd back to nodes
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loopcarried_deps_dict = {}
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for lat_sum, involved_lines in loopcarried_deps:
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dict_key = "-".join([str(il[0]) for il in involved_lines])
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loopcarried_deps_dict[dict_key] = {
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"root": self._get_node_by_lineno(involved_lines[0][0]),
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"dependencies": [
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(self._get_node_by_lineno(ln), lat) for ln, lat in involved_lines
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],
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"latency": lat_sum,
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}
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return loopcarried_deps_dict
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def _get_node_by_lineno(self, lineno, kernel=None, all=False):
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"""Return instruction form with line number ``lineno`` from kernel"""
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if kernel is None:
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kernel = self.kernel
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result = [instr for instr in kernel if instr.line_number == lineno]
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if not all:
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return result[0]
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else:
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return result
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def get_critical_path(self):
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"""Find and return critical path after the creation of a directed graph."""
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max_latency_instr = max(self.kernel, key=lambda k: k.latency)
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if nx.algorithms.dag.is_directed_acyclic_graph(self.dg):
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longest_path = nx.algorithms.dag.dag_longest_path(self.dg, weight="latency")
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# TODO verify that we can remove the next two lince due to earlier initialization
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for line_number in longest_path:
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self._get_node_by_lineno(int(line_number)).latency_cp = 0
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# set cp latency to instruction
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path_latency = 0.0
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for s, d in nx.utils.pairwise(longest_path):
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node = self._get_node_by_lineno(int(s))
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node.latency_cp = self.dg.edges[(s, d)]["latency"]
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path_latency += node.latency_cp
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# add latency for last instruction
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node = self._get_node_by_lineno(int(longest_path[-1]))
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node.latency_cp = node.latency
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if max_latency_instr.latency > path_latency:
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max_latency_instr.latency_cp = float(max_latency_instr.latency)
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return [max_latency_instr]
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else:
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return [x for x in self.kernel if x.line_number in longest_path]
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else:
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# split to DAG
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raise NotImplementedError("Kernel is cyclic.")
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def get_loopcarried_dependencies(self):
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"""
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Return all LCDs from kernel (after :func:`~KernelDG.check_for_loopcarried_dep` was run)
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"""
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if nx.algorithms.dag.is_directed_acyclic_graph(self.dg):
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return self.loopcarried_deps
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else:
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# split to DAG
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raise NotImplementedError("Kernel is cyclic.")
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def find_depending(self, instruction_form, instructions, flag_dependencies=False):
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"""
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Find instructions in `instructions` depending on a given instruction form's results.
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:param dict instruction_form: instruction form to check for dependencies
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:param list instructions: instructions to check
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:param flag_dependencies: indicating if dependencies of flags should be considered,
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defaults to `False`
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:type flag_dependencies: boolean, optional
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:returns: iterator if all directly dependent instruction forms and according flags
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"""
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if instruction_form.semantic_operands is None:
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return
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for dst in chain(
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instruction_form.semantic_operands["destination"],
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instruction_form.semantic_operands["src_dst"],
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):
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# TODO instructions before must be considered as well, if they update registers
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# not used by insruction_form. E.g., validation/build/A64FX/gcc/O1/gs-2d-5pt.marked.s
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register_changes = self._update_reg_changes(instruction_form)
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# print("FROM", instruction_form.line, register_changes)
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for i, instr_form in enumerate(instructions):
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self._update_reg_changes(instr_form, register_changes)
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# print(" TO", instr_form.line, register_changes)
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if isinstance(dst, RegisterOperand):
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# read of register
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if self.is_read(dst, instr_form):
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if (
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dst.pre_indexed
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or dst.post_indexed
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or (isinstance(dst.post_indexed, dict))
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):
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yield instr_form, ["p_indexed"]
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else:
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yield instr_form, []
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# write to register -> abort
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if self.is_written(dst, instr_form):
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break
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if isinstance(dst, FlagOperand) and flag_dependencies:
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# read of flag
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if self.is_read(dst, instr_form):
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yield instr_form, []
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# write to flag -> abort
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if self.is_written(dst, instr_form):
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break
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if isinstance(dst, MemoryOperand):
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# base register is altered during memory access
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if dst.pre_indexed:
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if self.is_written(dst.base, instr_form):
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break
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# if dst.memory.base:
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# if self.is_read(dst.memory.base, instr_form):
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# yield instr_form, []
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# if dst.memory.index:
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# if self.is_read(dst.memory.index, instr_form):
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# yield instr_form, []
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if dst.post_indexed:
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# Check for read of base register until overwrite
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if self.is_written(dst.base, instr_form):
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break
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# TODO record register changes
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# (e.g., mov, leaadd, sub, inc, dec) in instructions[:i]
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# and pass to is_memload and is_memstore to consider relevance.
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# load from same location (presumed)
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if self.is_memload(dst, instr_form, register_changes):
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yield instr_form, ["storeload_dep"]
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# store to same location (presumed)
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if self.is_memstore(dst, instr_form, register_changes):
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break
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self._update_reg_changes(instr_form, register_changes, only_postindexed=True)
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def _update_reg_changes(self, iform, reg_state=None, only_postindexed=False):
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if self.arch_sem is None:
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# This analysis requires semenatics to be available
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return {}
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if reg_state is None:
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reg_state = {}
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for reg, change in self.arch_sem.get_reg_changes(iform, only_postindexed).items():
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if change is None or reg_state.get(reg, {}) is None:
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reg_state[reg] = None
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else:
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reg_state.setdefault(reg, {"name": reg, "value": 0})
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if change["name"] != reg:
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# renaming occured, ovrwrite value with up-to-now change of source register
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reg_state[reg]["name"] = change["name"]
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src_reg_state = reg_state.get(change["name"], {"value": 0})
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if src_reg_state is None:
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# original register's state was changed beyond reconstruction
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reg_state[reg] = None
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continue
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reg_state[reg]["value"] = src_reg_state["value"]
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reg_state[reg]["value"] += change["value"]
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return reg_state
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def get_dependent_instruction_forms(self, instr_form=None, line_number=None):
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"""
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Returns iterator
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"""
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if not instr_form and not line_number:
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raise ValueError("Either instruction form or line_number required.")
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line_number = line_number if line_number else instr_form["line_number"]
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if self.dg.has_node(line_number):
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return self.dg.successors(line_number)
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return iter([])
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def is_read(self, register, instruction_form):
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"""Check if instruction form reads from given register"""
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is_read = False
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if instruction_form.semantic_operands is None:
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return is_read
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for src in chain(
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instruction_form.semantic_operands["source"],
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instruction_form.semantic_operands["src_dst"],
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):
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if isinstance(src, RegisterOperand):
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is_read = self.parser.is_reg_dependend_of(register, src) or is_read
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if isinstance(src, FlagOperand):
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is_read = self.parser.is_flag_dependend_of(register, src) or is_read
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if isinstance(src, MemoryOperand):
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if src.base is not None:
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is_read = self.parser.is_reg_dependend_of(register, src.base) or is_read
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if src.index is not None and isinstance(src.index, RegisterOperand):
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is_read = self.parser.is_reg_dependend_of(register, src.index) or is_read
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# Check also if read in destination memory address
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for dst in chain(
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instruction_form.semantic_operands["destination"],
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instruction_form.semantic_operands["src_dst"],
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):
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if isinstance(dst, MemoryOperand):
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if dst.base is not None:
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is_read = self.parser.is_reg_dependend_of(register, dst.base) or is_read
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if dst.index is not None:
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is_read = self.parser.is_reg_dependend_of(register, dst.index) or is_read
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return is_read
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def is_memload(self, mem, instruction_form, register_changes={}):
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"""Check if instruction form loads from given location, assuming register_changes"""
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if instruction_form.semantic_operands is None:
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return False
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for src in chain(
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instruction_form.semantic_operands["source"],
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instruction_form.semantic_operands["src_dst"],
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):
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# Here we check for mem dependecies only
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if not isinstance(src, MemoryOperand):
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continue
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# src = src.memory
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# determine absolute address change
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addr_change = 0
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if isinstance(src.offset, ImmediateOperand) and src.offset.value is not None:
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addr_change += src.offset.value
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if isinstance(mem.offset, ImmediateOperand) and mem.offset.value is not None:
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addr_change -= mem.offset.value
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if mem.base and src.base:
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base_change = register_changes.get(
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(src.base.prefix if src.base.prefix is not None else "") + src.base.name,
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{
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"name": (src.base.prefix if src.base.prefix is not None else "")
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+ src.base.name,
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"value": 0,
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},
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)
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if base_change is None:
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# Unknown change occurred
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continue
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if (
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mem.base.prefix
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if mem.base.prefix is not None
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else "" + mem.base.name != base_change["name"]
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):
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# base registers do not match
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continue
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addr_change += base_change["value"]
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elif mem.base or src.base:
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# base registers do not match
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continue
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if mem.index and src.index:
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index_change = register_changes.get(
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(src.index.prefix if src.index.prefix is not None else "") + src.index.name,
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{
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"name": (src.index.prefix if src.index.prefix is not None else "")
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+ src.index.name,
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"value": 0,
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},
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)
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if index_change is None:
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# Unknown change occurred
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continue
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if mem.scale != src.scale:
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# scale factors do not match
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continue
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if (
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mem.index.prefix
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if mem.index.prefix is not None
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else "" + mem.index.name != index_change["name"]
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):
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# index registers do not match
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continue
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addr_change += index_change["value"] * src.scale
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elif mem.index or src.index:
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# index registers do not match
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continue
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# if instruction_form.line_number == 3:
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if addr_change == 0:
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return True
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return False
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def is_written(self, register, instruction_form):
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"""Check if instruction form writes in given register"""
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is_written = False
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if instruction_form.semantic_operands is None:
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return is_written
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for dst in chain(
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instruction_form.semantic_operands["destination"],
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instruction_form.semantic_operands["src_dst"],
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):
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if isinstance(dst, RegisterOperand):
|
|
is_written = self.parser.is_reg_dependend_of(register, dst) or is_written
|
|
if isinstance(dst, FlagOperand):
|
|
is_written = self.parser.is_flag_dependend_of(register, dst) or is_written
|
|
if isinstance(dst, MemoryOperand):
|
|
if dst.pre_indexed or dst.post_indexed:
|
|
is_written = self.parser.is_reg_dependend_of(register, dst.base) or is_written
|
|
# Check also for possible pre- or post-indexing in memory addresses
|
|
for src in chain(
|
|
instruction_form.semantic_operands["source"],
|
|
instruction_form.semantic_operands["src_dst"],
|
|
):
|
|
if isinstance(src, MemoryOperand):
|
|
if src.pre_indexed or src.post_indexed:
|
|
is_written = self.parser.is_reg_dependend_of(register, src.base) or is_written
|
|
return is_written
|
|
|
|
def is_memstore(self, mem, instruction_form, register_changes={}):
|
|
"""Check if instruction form stores to given location, assuming unchanged registers"""
|
|
is_store = False
|
|
if instruction_form.semantic_operands is None:
|
|
return is_store
|
|
for dst in chain(
|
|
instruction_form.semantic_operands["destination"],
|
|
instruction_form.semantic_operands["src_dst"],
|
|
):
|
|
if isinstance(dst, MemoryOperand):
|
|
is_store = mem == dst or is_store
|
|
return is_store
|
|
|
|
def export_graph(self, filepath=None):
|
|
"""
|
|
Export graph with highlighted CP and LCDs as DOT file. Writes it to 'osaca_dg.dot'
|
|
if no other path is given.
|
|
|
|
:param filepath: path to write DOT file, defaults to None.
|
|
:type filepath: str, optional
|
|
"""
|
|
graph = copy.deepcopy(self.dg)
|
|
cp = self.get_critical_path()
|
|
cp_line_numbers = [x.line_number for x in cp]
|
|
lcd = self.get_loopcarried_dependencies()
|
|
lcd_line_numbers = {}
|
|
for dep in lcd:
|
|
lcd_line_numbers[dep] = [x.line_number for x, lat in lcd[dep]["dependencies"]]
|
|
# add color scheme
|
|
graph.graph["node"] = {"colorscheme": "set312"}
|
|
graph.graph["edge"] = {"colorscheme": "set312"}
|
|
|
|
# create LCD edges
|
|
for dep in lcd_line_numbers:
|
|
min_line_number = min(lcd_line_numbers[dep])
|
|
max_line_number = max(lcd_line_numbers[dep])
|
|
graph.add_edge(max_line_number, min_line_number)
|
|
graph.edges[max_line_number, min_line_number]["latency"] = [
|
|
lat for x, lat in lcd[dep]["dependencies"] if x.line_number == max_line_number
|
|
]
|
|
|
|
# add label to edges
|
|
for e in graph.edges:
|
|
graph.edges[e]["label"] = graph.edges[e]["latency"]
|
|
|
|
# add CP values to graph
|
|
for n in cp:
|
|
graph.nodes[n.line_number]["instruction_form"].latency_cp = n.latency_cp
|
|
|
|
# color CP and LCD
|
|
for n in graph.nodes:
|
|
if n in cp_line_numbers:
|
|
# graph.nodes[n]['color'] = 1
|
|
graph.nodes[n]["style"] = "bold"
|
|
graph.nodes[n]["penwidth"] = 4
|
|
for col, dep in enumerate(lcd):
|
|
if n in lcd_line_numbers[dep]:
|
|
if "style" not in graph.nodes[n]:
|
|
graph.nodes[n]["style"] = "filled"
|
|
else:
|
|
graph.nodes[n]["style"] += ",filled"
|
|
graph.nodes[n]["fillcolor"] = 2 + col % 11
|
|
|
|
# color edges
|
|
for e in graph.edges:
|
|
if (
|
|
graph.nodes[e[0]]["instruction_form"].line_number in cp_line_numbers
|
|
and graph.nodes[e[1]]["instruction_form"].line_number in cp_line_numbers
|
|
and e[0] < e[1]
|
|
):
|
|
bold_edge = True
|
|
for i in range(e[0] + 1, e[1]):
|
|
if i in cp_line_numbers:
|
|
bold_edge = False
|
|
if bold_edge:
|
|
graph.edges[e]["style"] = "bold"
|
|
graph.edges[e]["penwidth"] = 3
|
|
for dep in lcd_line_numbers:
|
|
if (
|
|
graph.nodes[e[0]]["instruction_form"].line_number in lcd_line_numbers[dep]
|
|
and graph.nodes[e[1]]["instruction_form"].line_number in lcd_line_numbers[dep]
|
|
):
|
|
graph.edges[e]["color"] = graph.nodes[e[1]]["fillcolor"]
|
|
|
|
# rename node from [idx] to [idx mnemonic] and add shape
|
|
mapping = {}
|
|
for n in graph.nodes:
|
|
if int(n) != n:
|
|
mapping[n] = "{}: LOAD".format(int(n))
|
|
graph.nodes[n]["fontname"] = "italic"
|
|
graph.nodes[n]["fontsize"] = 11.0
|
|
else:
|
|
node = graph.nodes[n]["instruction_form"]
|
|
if node.mnemonic is not None:
|
|
mapping[n] = "{}: {}".format(n, node.mnemonic)
|
|
else:
|
|
label = "label" if node.label is not None else None
|
|
label = "directive" if node.directive is not None else label
|
|
label = "comment" if node.comment is not None and label is None else label
|
|
mapping[n] = "{}: {}".format(n, label)
|
|
graph.nodes[n]["fontname"] = "italic"
|
|
graph.nodes[n]["fontsize"] = 11.0
|
|
graph.nodes[n]["shape"] = "rectangle"
|
|
|
|
nx.relabel.relabel_nodes(graph, mapping, copy=False)
|
|
if filepath:
|
|
nx.drawing.nx_agraph.write_dot(graph, filepath)
|
|
else:
|
|
nx.drawing.nx_agraph.write_dot(graph, "osaca_dg.dot")
|