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OSACA/osaca/data/isa/riscv.yml
2025-03-13 09:54:06 +01:00

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---
osaca_version: 0.6.1
isa: riscv
# Contains all operand-irregular instruction forms OSACA supports for RISC-V.
# Operand-regular for a RISC-V instruction form with N operands in the shape of
# mnemonic op1 ... opN
# means that op1 is the only destination operand and op2 to op(N) are source operands.
# For vector instructions with suffixes (.v, .vv, .vf), the operand behavior follows
# the base instruction pattern.
instruction_forms:
- name: addi
operands:
- class: register
prefix: x
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
- class: immediate
imd: 'int'
source: true
destination: false
operation: "op1['value'] = op2['value'] + op3['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "Z"
source: false
destination: true
- class: flag
name: "N"
source: false
destination: true
- name: add
operands:
- class: register
prefix: x
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
- class: register
prefix: x
source: true
destination: false
operation: "op1['value'] = op2['value'] + op3['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "Z"
source: false
destination: true
- class: flag
name: "N"
source: false
destination: true
- name: sub
operands:
- class: register
prefix: x
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
- class: register
prefix: x
source: true
destination: false
operation: "op1['value'] = op2['value'] - op3['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "Z"
source: false
destination: true
- class: flag
name: "N"
source: false
destination: true
- name: mul
operands:
- class: register
prefix: x
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
- class: register
prefix: x
source: true
destination: false
operation: "op1['value'] = op2['value'] * op3['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "Z"
source: false
destination: true
- class: flag
name: "N"
source: false
destination: true
- name: div
operands:
- class: register
prefix: x
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
- class: register
prefix: x
source: true
destination: false
operation: "op1['value'] = op2['value'] / op3['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "Z"
source: false
destination: true
- class: flag
name: "N"
source: false
destination: true
- name: and
operands:
- class: register
prefix: x
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
- class: register
prefix: x
source: true
destination: false
operation: "op1['value'] = op2['value'] & op3['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "Z"
source: false
destination: true
- class: flag
name: "N"
source: false
destination: true
- name: or
operands:
- class: register
prefix: x
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
- class: register
prefix: x
source: true
destination: false
operation: "op1['value'] = op2['value'] | op3['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "Z"
source: false
destination: true
- class: flag
name: "N"
source: false
destination: true
- name: xor
operands:
- class: register
prefix: x
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
- class: register
prefix: x
source: true
destination: false
operation: "op1['value'] = op2['value'] ^ op3['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "Z"
source: false
destination: true
- class: flag
name: "N"
source: false
destination: true
- name: sll
operands:
- class: register
prefix: x
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
- class: register
prefix: x
source: true
destination: false
operation: "op1['value'] = op2['value'] << op3['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "Z"
source: false
destination: true
- class: flag
name: "N"
source: false
destination: true
- name: srl
operands:
- class: register
prefix: x
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
- class: register
prefix: x
source: true
destination: false
operation: "op1['value'] = op2['value'] >> op3['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "Z"
source: false
destination: true
- class: flag
name: "N"
source: false
destination: true
- name: sra
operands:
- class: register
prefix: x
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
- class: register
prefix: x
source: true
destination: false
operation: "op1['value'] = op2['value'] >> op3['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "Z"
source: false
destination: true
- class: flag
name: "N"
source: false
destination: true
- name: lw
operands:
- class: register
prefix: x
source: false
destination: true
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
pre_indexed: "*"
post_indexed: "*"
source: true
destination: false
operation: "op1['value'] = memory[op2['value']]; op1['name'] = op2['name']"
- name: sw
operands:
- class: register
prefix: x
source: true
destination: false
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
pre_indexed: "*"
post_indexed: "*"
source: false
destination: true
operation: "memory[op2['value']] = op1['value']"
- name: lb
operands:
- class: register
prefix: x
source: false
destination: true
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
pre_indexed: "*"
post_indexed: "*"
source: true
destination: false
operation: "op1['value'] = memory[op2['value']]; op1['name'] = op2['name']"
- name: sb
operands:
- class: register
prefix: x
source: true
destination: false
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
pre_indexed: "*"
post_indexed: "*"
source: false
destination: true
operation: "memory[op2['value']] = op1['value']"
- name: lh
operands:
- class: register
prefix: x
source: false
destination: true
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
pre_indexed: "*"
post_indexed: "*"
source: true
destination: false
operation: "op1['value'] = memory[op2['value']]; op1['name'] = op2['name']"
- name: sh
operands:
- class: register
prefix: x
source: true
destination: false
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
pre_indexed: "*"
post_indexed: "*"
source: false
destination: true
operation: "memory[op2['value']] = op1['value']"
- name: beq
operands:
- class: register
prefix: x
source: true
destination: false
- class: register
prefix: x
source: true
destination: false
- class: identifier
source: true
destination: false
hidden_operands:
- class: flag
name: "Z"
source: true
destination: false
- name: bne
operands:
- class: register
prefix: x
source: true
destination: false
- class: register
prefix: x
source: true
destination: false
- class: identifier
source: true
destination: false
hidden_operands:
- class: flag
name: "Z"
source: true
destination: false
- name: blt
operands:
- class: register
prefix: x
source: true
destination: false
- class: register
prefix: x
source: true
destination: false
- class: identifier
source: true
destination: false
hidden_operands:
- class: flag
name: "N"
source: true
destination: false
- name: bge
operands:
- class: register
prefix: x
source: true
destination: false
- class: register
prefix: x
source: true
destination: false
- class: identifier
source: true
destination: false
hidden_operands:
- class: flag
name: "N"
source: true
destination: false
- name: jal
operands:
- class: register
prefix: x
source: false
destination: true
- class: identifier
source: true
destination: false
operation: "op1['value'] = pc + 4; pc = op2['value']"
- name: jalr
operands:
- class: register
prefix: x
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
- class: immediate
imd: 'int'
source: true
destination: false
operation: "op1['value'] = pc + 4; pc = op2['value'] + op3['value']"
- name: lui
operands:
- class: register
prefix: x
source: false
destination: true
- class: immediate
imd: 'int'
source: true
destination: false
operation: "op1['value'] = op2['value'] << 12"
- name: auipc
operands:
- class: register
prefix: x
source: false
destination: true
- class: immediate
imd: 'int'
source: true
destination: false
operation: "op1['value'] = pc + (op2['value'] << 12)"
- name: li
operands:
- class: register
prefix: x
source: false
destination: true
- class: immediate
imd: 'int'
source: true
destination: false
operation: "op1['value'] = op2['value']"
- name: mv
operands:
- class: register
prefix: x
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
operation: "op1['value'] = op2['value']"
- name: ret
operands:
- class: register
prefix: x
name: "1" # x1 is the return address register (ra)
source: true
destination: false
operation: "pc = op1['value']"
- name: j
operands:
- class: identifier
source: true
destination: false
operation: "pc = op1['value']"
- name: jr
operands:
- class: register
prefix: x
source: true
destination: false
operation: "pc = op1['value']"
# Floating-point instructions
- name: flw
operands:
- class: register
prefix: f
source: false
destination: true
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
pre_indexed: "*"
post_indexed: "*"
source: true
destination: false
operation: "op1['value'] = memory[op2['value']]; op1['name'] = op2['name']"
- name: fsw
operands:
- class: register
prefix: f
source: true
destination: false
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
pre_indexed: "*"
post_indexed: "*"
source: false
destination: true
operation: "memory[op2['value']] = op1['value']"
- name: fadd
operands:
- class: register
prefix: f
source: false
destination: true
- class: register
prefix: f
source: true
destination: false
- class: register
prefix: f
source: true
destination: false
operation: "op1['value'] = op2['value'] + op3['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "FSR"
source: true
destination: true
- name: fsub
operands:
- class: register
prefix: f
source: false
destination: true
- class: register
prefix: f
source: true
destination: false
- class: register
prefix: f
source: true
destination: false
operation: "op1['value'] = op2['value'] - op3['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "FSR"
source: true
destination: true
- name: fmul
operands:
- class: register
prefix: f
source: false
destination: true
- class: register
prefix: f
source: true
destination: false
- class: register
prefix: f
source: true
destination: false
operation: "op1['value'] = op2['value'] * op3['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "FSR"
source: true
destination: true
- name: fdiv
operands:
- class: register
prefix: f
source: false
destination: true
- class: register
prefix: f
source: true
destination: false
- class: register
prefix: f
source: true
destination: false
operation: "op1['value'] = op2['value'] / op3['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "FSR"
source: true
destination: true
- name: fmv.x.w
operands:
- class: register
prefix: x
source: false
destination: true
- class: register
prefix: f
source: true
destination: false
operation: "op1['value'] = op2['value']"
- name: fmv.w.x
operands:
- class: register
prefix: f
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
operation: "op1['value'] = op2['value']"
# Vector instructions
- name: vsetvli
operands:
- class: register
prefix: x
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
- class: identifier
source: true
destination: false
- class: identifier
source: true
destination: false
- class: identifier
source: true
destination: false
- class: identifier
source: true
destination: false
operation: "op1['value'] = min(op2['value'], op3['value']); vtype = op4['value']; vsew = op5['value']; vlmul = op6['value']"
hidden_operands:
- class: flag
name: "VSR"
source: true
destination: true
- name: vsetivli
operands:
- class: register
prefix: x
source: false
destination: true
- class: immediate
imd: 'int'
source: true
destination: false
- class: identifier
source: true
destination: false
- class: identifier
source: true
destination: false
- class: identifier
source: true
destination: false
- class: identifier
source: true
destination: false
operation: "op1['value'] = min(op2['value'], op3['value']); vtype = op4['value']; vsew = op5['value']; vlmul = op6['value']"
hidden_operands:
- class: flag
name: "VSR"
source: true
destination: true
- name: vle32.v
operands:
- class: register
prefix: v
source: false
destination: true
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
pre_indexed: "*"
post_indexed: "*"
source: true
destination: false
operation: "op1['value'] = memory[op2['value']]; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "VSR"
source: true
destination: true
- name: vse32.v
operands:
- class: register
prefix: v
source: true
destination: false
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
pre_indexed: "*"
post_indexed: "*"
source: false
destination: true
operation: "memory[op2['value']] = op1['value']"
hidden_operands:
- class: flag
name: "VSR"
source: true
destination: true
- name: vadd.vv
operands:
- class: register
prefix: v
source: false
destination: true
- class: register
prefix: v
source: true
destination: false
- class: register
prefix: v
source: true
destination: false
operation: "op1['value'] = op2['value'] + op3['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "VSR"
source: true
destination: true
- name: vfmv.v.f
operands:
- class: register
prefix: v
source: false
destination: true
- class: register
prefix: f
source: true
destination: false
operation: "op1['value'] = op2['value']"
hidden_operands:
- class: flag
name: "VSR"
source: true
destination: true
- name: vfmadd.vv
operands:
- class: register
prefix: v
source: false
destination: true
- class: register
prefix: v
source: true
destination: false
- class: register
prefix: v
source: true
destination: false
operation: "op1['value'] = op2['value'] * op3['value'] + op1['value']; op1['name'] = op2['name']"
hidden_operands:
- class: flag
name: "VSR"
source: true
destination: true
- name: vfmacc.vf
operands:
- class: register
prefix: v
source: true
destination: true
- class: register
prefix: f
source: true
destination: false
- class: register
prefix: v
source: true
destination: false
operation: "op1['value'] = op2['value'] * op3['value'] + op1['value']"
hidden_operands:
- class: flag
name: "VSR"
source: true
destination: true
# CSR instructions
- name: csrr
operands:
- class: register
prefix: x
source: false
destination: true
- class: identifier
source: true
destination: false
operation: "op1['value'] = csr[op2['value']]"
hidden_operands:
- class: flag
name: "CSR"
source: true
destination: true
- name: csrw
operands:
- class: identifier
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
operation: "csr[op1['value']] = op2['value']"
hidden_operands:
- class: flag
name: "CSR"
source: true
destination: true
- name: csrs
operands:
- class: identifier
source: true
destination: true
- class: register
prefix: x
source: true
destination: false
operation: "csr[op1['value']] |= op2['value']"
hidden_operands:
- class: flag
name: "CSR"
source: true
destination: true
- name: csrc
operands:
- class: identifier
source: true
destination: true
- class: register
prefix: x
source: true
destination: false
operation: "csr[op1['value']] &= ~op2['value']"
hidden_operands:
- class: flag
name: "CSR"
source: true
destination: true
# Atomic instructions
- name: lr.w
operands:
- class: register
prefix: x
source: false
destination: true
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
pre_indexed: "*"
post_indexed: "*"
source: true
destination: false
operation: "op1['value'] = memory[op2['value']]; memory[op2['value']] = reserved"
hidden_operands:
- class: flag
name: "CSR"
source: true
destination: true
- name: sc.w
operands:
- class: register
prefix: x
source: false
destination: true
- class: register
prefix: x
source: true
destination: false
- class: memory
base: "*"
offset: "*"
index: "*"
scale: "*"
pre_indexed: "*"
post_indexed: "*"
source: true
destination: true
operation: "if (memory[op3['value']] == reserved) { memory[op3['value']] = op2['value']; op1['value'] = 0; } else { op1['value'] = 1; }"
hidden_operands:
- class: flag
name: "CSR"
source: true
destination: true