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https://github.com/RRZE-HPC/OSACA.git
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114 lines
5.2 KiB
Python
Executable File
114 lines
5.2 KiB
Python
Executable File
#!/usr/bin/env python3
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import networkx as nx
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from .hw_model import MachineModel
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class KernelDG(nx.DiGraph):
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def __init__(self, parsed_kernel, parser, hw_model: MachineModel):
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self.kernel = parsed_kernel
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self.parser = parser
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self.model = hw_model
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self.dg = self.create_DG()
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def check_for_loop(self, kernel):
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raise NotImplementedError
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def create_DG(self):
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# 1. go through kernel instruction forms (as vertices)
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# 2. find edges (to dependend further instruction)
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# 3. get LT value and set as edge weight
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# 4. add instr forms as node attribute
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dg = nx.DiGraph()
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for i, instruction_form in enumerate(self.kernel):
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for dep in self.find_depending(instruction_form, self.kernel[i + 1:]):
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dg.add_edge(
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instruction_form['line_number'],
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dep['line_number'],
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latency=instruction_form['latency'],
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)
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dg.nodes[instruction_form['line_number']]['instruction_form'] = instruction_form
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dg.nodes[dep['line_number']]['instruction_form'] = dep
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return dg
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def find_depending(self, instruction_form, kernel):
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if instruction_form.operands is None:
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return
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for dst in instruction_form.operands.destination + instruction_form.operands.src_dst:
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if 'register' in dst:
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# Check for read of register until overwrite
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for instr_form in kernel:
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if self.is_read(dst.register, instr_form):
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yield instr_form
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if self.is_written(dst.register, instr_form):
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# operand in src_dst list
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break
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elif self.is_written(dst.register, instr_form):
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break
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elif 'memory' in dst:
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# Check if base register is altered during memory access
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if 'pre_indexed' in dst.memory or 'post_indexed' in dst.memory:
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# Check for read of base register until overwrite
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for instr_form in kernel:
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if self.is_read(dst.memory.base, instr_form):
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yield instr_form
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if self.is_written(dst.memory.base, instr_form):
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# operand in src_dst list
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break
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elif self.is_written(dst.memory.base, instr_form):
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break
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def get_dependent_instruction_forms(self, instr_form=None, line_number=None):
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"""
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Returns iterator
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"""
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if not instr_form and not line_number:
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raise ValueError('Either instruction form or line_number required.')
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line_number = line_number if line_number else instr_form['line_number']
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if self.dg.has_node(line_number):
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return self.dg.successors(line_number)
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return iter([])
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def is_read(self, register, instruction_form):
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is_read = False
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for src in instruction_form.operands.source + instruction_form.operands.src_dst:
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if 'register' in src:
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is_read = self.parser.is_reg_dependend_of(register, src.register) or is_read
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if 'memory' in src:
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if src.memory.base is not None:
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is_read = self.parser.is_reg_dependend_of(register, src.memory.base) or is_read
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if src.memory.index is not None:
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is_read = (
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self.parser.is_reg_dependend_of(register, src.memory.index) or is_read
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)
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# Check also if read in destination memory address
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for dst in instruction_form.operands.destination + instruction_form.operands.src_dst:
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if 'memory' in dst:
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if dst.memory.base is not None:
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is_read = self.parser.is_reg_dependend_of(register, dst.memory.base) or is_read
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if dst.memory.index is not None:
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is_read = (
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self.parser.is_reg_dependend_of(register, dst.memory.index) or is_read
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)
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return is_read
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def is_written(self, register, instruction_form):
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is_written = False
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for dst in instruction_form.operands.destination + instruction_form.operands.src_dst:
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if 'register' in dst:
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is_written = self.parser.is_reg_dependend_of(register, dst.register) or is_written
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if 'memory' in dst:
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if 'pre_indexed' in dst.memory or 'post_indexed' in dst.memory:
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is_written = (
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self.parser.is_reg_dependend_of(register, dst.memory.base) or is_written
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)
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# Check also for possible pre- or post-indexing in memory addresses
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for src in instruction_form.operands.source + instruction_form.operands.src_dst:
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if 'memory' in src:
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if 'pre_indexed' in src.memory or 'post_indexed' in src.memory:
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is_written = (
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self.parser.is_reg_dependend_of(register, src.memory.base) or is_written
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)
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return is_written
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