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https://github.com/RRZE-HPC/OSACA.git
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119 lines
4.6 KiB
Python
Executable File
119 lines
4.6 KiB
Python
Executable File
#!/usr/bin/env python3
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from itertools import chain
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from osaca import utils
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from osaca.parser import AttrDict, ParserAArch64v81, ParserX86ATT
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from .hw_model import MachineModel
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class INSTR_FLAGS:
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"""
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Flags used for unknown or special instructions
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"""
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LD = 'is_load_instruction'
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TP_UNKWN = 'tp_unknown'
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LT_UNKWN = 'lt_unknown'
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NOT_BOUND = 'not_bound'
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HIDDEN_LD = 'hidden_load'
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HAS_LD = 'performs_load'
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HAS_ST = 'performs_store'
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class ISASemantics(object):
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def __init__(self, isa, path_to_yaml=None):
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self._isa = isa.lower()
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path = utils.find_file('isa/' + self._isa + '.yml') if not path_to_yaml else path_to_yaml
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self._isa_model = MachineModel(path_to_yaml=path)
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if self._isa == 'x86':
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self._parser = ParserX86ATT()
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elif self._isa == 'aarch64':
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self._parser = ParserAArch64v81()
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def process(self, instruction_forms):
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"""Process a list of instruction forms."""
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for i in instruction_forms:
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self.assign_src_dst(i)
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# get ;parser result and assign operands to
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# - source
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# - destination
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# - source/destination
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def assign_src_dst(self, instruction_form):
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"""Update instruction form dictionary with source, destination and flag information."""
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# if the instruction form doesn't have operands, there's nothing to do
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if instruction_form['operands'] is None:
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instruction_form['semantic_operands'] = AttrDict(
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{'source': [], 'destination': [], 'src_dst': []})
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return
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# check if instruction form is in ISA yaml, otherwise apply standard operand assignment
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# (one dest, others source)
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isa_data = self._isa_model.get_instruction(
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instruction_form['instruction'], instruction_form['operands']
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)
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operands = instruction_form['operands']
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op_dict = {}
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if isa_data is None:
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# no irregular operand structure, apply default
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op_dict['source'] = self._get_regular_source_operands(instruction_form)
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op_dict['destination'] = self._get_regular_destination_operands(instruction_form)
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op_dict['src_dst'] = []
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else:
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# load src/dst structure from isa_data
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op_dict['source'] = []
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op_dict['destination'] = []
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op_dict['src_dst'] = []
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for i, op in enumerate(isa_data['operands']):
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if op['source'] and op['destination']:
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op_dict['src_dst'].append(operands[i])
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continue
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if op['source']:
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op_dict['source'].append(operands[i])
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continue
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if op['destination']:
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op_dict['destination'].append(operands[i])
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continue
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# store operand list in dict and reassign operand key/value pair
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instruction_form['semantic_operands'] = AttrDict.convert_dict(op_dict)
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# assign LD/ST flags
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instruction_form['flags'] = (
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instruction_form['flags'] if 'flags' in instruction_form else []
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)
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if self._has_load(instruction_form):
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instruction_form['flags'] += [INSTR_FLAGS.HAS_LD]
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if self._has_store(instruction_form):
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instruction_form['flags'] += [INSTR_FLAGS.HAS_ST]
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def _has_load(self, instruction_form):
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for operand in chain(instruction_form['semantic_operands']['source'],
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instruction_form['semantic_operands']['src_dst']):
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if 'memory' in operand:
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return True
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return False
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def _has_store(self, instruction_form):
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for operand in chain(instruction_form['semantic_operands']['destination'],
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instruction_form['semantic_operands']['src_dst']):
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if 'memory' in operand:
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return True
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return False
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def _get_regular_source_operands(self, instruction_form):
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if self._isa == 'x86':
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# return all but last operand
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return [op for op in instruction_form['operands'][0:-1]]
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elif self._isa == 'aarch64':
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return [op for op in instruction_form['operands'][1:]]
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else:
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raise ValueError("Unsupported ISA {}.".format(self._isa))
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def _get_regular_destination_operands(self, instruction_form):
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if self._isa == 'x86':
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# return last operand
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return instruction_form['operands'][-1:]
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if self._isa == 'aarch64':
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# return first operand
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return instruction_form['operands'][:1]
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else:
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raise ValueError("Unsupported ISA {}.".format(self._isa))
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