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OSACA/osaca/data/m1.yml
JanLJL dc250bcedc initial commit of M1 model (not complete)
2023-09-28 10:04:15 +02:00

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osaca_version: 0.5.2
micro_architecture: Apple M1 Firestorm
arch_code: m1
isa: AArch64
ROB_size: 623 #https://dougallj.github.io/applecpu/firestorm.html
retired_uOps_per_cycle: 8
scheduler_size: 326 #https://dougallj.github.io/applecpu/firestorm.html
hidden_loads: false
load_latency: {w: 3.0, x: 3.0, b: 3.0, h: 3.0, s: 3.0, d: 3.0, q: 3.0, v: 3.0}
p_index_latency: 1
load_throughput:
- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, '467']]}
- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '467'], [1, ['8', '9', '10', '12', '13']]]}
- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '467'], [1, ['8', '9', '10', '12', '13']]]}
load_throughput_default: [[1, '467']]
store_throughput:
- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: false, port_pressure: [[1, '45']]}
- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: false, post-indexed: true, port_pressure: [[1, '45'], [1, ['8', '9', '10', '12', '13']]]}
- {base: '*', index: '*', offset: '*', scale: '*', pre-indexed: true, post-indexed: false, port_pressure: [[1, '45'], [1, ['8', '9', '10', '12', '13']]]}
store_throughput_default: [[1, '45']]
ports: ['0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '10', '11', '12', '13']
port_model_scheme: |
+------+ +------+ +------+ +-------------+ +-----------------------------+ +------+ +------+ +------+ +------+ +-------------+ +------+
| 36 | | 36 | | 36 | | 36 | | 48 | | 24 | | 26 | | 16 | | 12 | | 28 | | 28 |
+------+ +------+ +------+ +-------------+ +-----------------------------+ +------+ +------+ +------+ +------+ +-------------+ +------+
0 |FP0 1 |FP1 2 |FP2 3 |FP3 4 |D0 5 |D1 6 |D2 7 |D3 8 |INT0 9 |INT1 10 |INT2 11 |INT3 12 |INT4 13 |INT5
\/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/
+------+ +------+ +------+ +------+ +----+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+
| ALU | | ALU | | ALU | | ALU | | DV | | LD | | ST | | LD | | LD | | ALU | | ALU | | ALU | | ALU | | ALU | | DV | | ALU |
+------+ +------+ +------+ +------+ +----+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +----+ +------+
+------+ +------+ +------+ +------+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +------+
| MUL | | MUL | | MUL | | MUL | | ST | | AGU | | AGU | | AGU | | SHIFT| | SHIFT| | SHIFT| | SHIFT| | SHIFT| | SHIFT|
+------+ +------+ +------+ +------+ +-----+ +-----+ +-----+ +-----+ +------+ +------+ +------+ +------+ +------+ +------+
+------+ +------+ +------+ +------+ +-----+ +------+ +------+ +------+ +------+ +------+ +------+
| FMA | | FMA | | FMA | | FMA | | AGU | | BR | | BR | | FLAGS| |MOV FP| | MUL | | MUL |
+------+ +------+ +------+ +------+ +-----+ +------+ +------+ +------+ +------+ +------+ +------+
+------+ +------+ +------+ +------+ +------+ +------+
| FCSEL| | FCSEL| | FLAGS| | FLAGS| |MOV FP| silly | FMA |
+------+ +------+ +------+ +------+ +------+ +------+
+------+ +------+
| 2INT | | 2INT |
+------+ +------+
+------+
| RCP |
+------+
+------+
| SHA |
+------+
instruction_forms:
- name: [adc, adcs]
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
- class: register
prefix: '*'
throughput: 0.33333333
latency: 1.0 # 1*p89,10
port_pressure: [[1, ['8', '9', '10']]]
- name: add
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: register
prefix: x
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: add
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: immediate
imd: int
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: add
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: add
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: immediate
imd: int
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: adds
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
- class: register
prefix: '*'
throughput: 0.33333333
latency: 1.0 # 1*p89,10
port_pressure: [[1, ['8', '9', '10']]]
- name: adds
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
- class: immediate
imd: int
throughput: 0.33333333
latency: 1.0 # 1*p89,10
port_pressure: [[1, ['8', '9', '10']]]
- name: adr
operands:
- class: register
prefix: '*'
- class: identifier
throughput: 0.5
latency: ~ # 1*p89
port_pressure: [[1, '89']]
- name: and
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: register
prefix: x
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: asr
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: immediate
imd: int
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: and
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: asr
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: immediate
imd: int
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: [asr, asrv]
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
- class: register
prefix: '*'
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: asr
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
- class: immediate
imd: int
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: [b, bl, bcc, bcs, bgt, bhi, b.lo, b.ne, b.any, b.none, bal, b.al, b.lt, b.eq, b.hs, b.gt, b.hi, bne, beq]
operands:
- class: identifier
throughput: 0.5
latency: 0.0
port_pressure: [[1, '89']]
- name: [bfi, bfm]
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
- class: immediate
imd: int
- class: immediate
imd: int
throughput: 1.0
latency: 1.0 # 1*p13
port_pressure: [[1, ['13']]]
- name: bic
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: register
prefix: x
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: bics
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: register
prefix: x
throughput: 0.33333333
latency: 1.0 # 1*p89,10
port_pressure: [[1, ['8', '9', '10']]]
- name: bic
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: bics
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.33333333
latency: 1.0 # 1*p89,10
port_pressure: [[1, ['8', '9', '10']]]
- name: [cls, clz]
operands:
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: [cls, clz]
operands:
- class: register
prefix: x
- class: register
prefix: x
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: cmp
operands:
- class: register
prefix: '*'
- class: immediate
imd: int
throughput: 0.33333333
latency: 1.0 # 1*p89,10
port_pressure: [[1, ['8', '9', '10']]]
- name: cmp
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
throughput: 0.3333333
latency: 1.0 # 1*p89,10
port_pressure: [[1, ['8', '9', '10']]]
- name: [eon, eor]
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: register
prefix: x
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: eor
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: immediate
imd: int
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: [eon, eor]
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: eor
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: immediate
imd: int
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: [ldr, ldur]
operands:
- class: register
prefix: "*"
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: false
throughput: 0.3333333
latency: 3.0 # 1*p467
port_pressure: [[1, '467']]
- name: [ldr, ldur]
operands:
- class: register
prefix: "*"
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: false
throughput: 0.3333333
latency: 4.0 # 1*p467
port_pressure: [[1, '467']]
- name: [ldr, ldur]
operands:
- class: register
prefix: "*"
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: true
pre-indexed: false
throughput: 0.3333333
latency: 3.0 # 1*p467
port_pressure: [[1, '467'], [1, ['8', '9', '10']]]
- name: [ldr, ldur]
operands:
- class: register
prefix: "*"
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: true
pre-indexed: false
throughput: 0.3333333
latency: 4.0 # 1*p467
port_pressure: [[1, '467'], [1, ['8', '9', '10']]]
- name: [ldr, ldur]
operands:
- class: register
prefix: "*"
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: true
throughput: 0.3333333
latency: 3.0 # 1*p467
port_pressure: [[1, '467'], [1, ['8', '9', '10']]]
- name: [ldr, ldur]
operands:
- class: register
prefix: "*"
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: true
throughput: 0.3333333
latency: 4.0 # 1*p467
port_pressure: [[1, '467'], [1, ['8', '9', '10']]]
- name: ldp
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: false
throughput: 0.3333333
latency: 3.0 # 1*p467
port_pressure: [[1, '467']]
- name: ldp
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: false
throughput: 0.3333333
latency: 4.0 # 1*p467
port_pressure: [[1, '467']]
- name: ldp
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: true
pre-indexed: false
throughput: 0.3333333
latency: 3.0 # 1*p467
port_pressure: [[1, '467'], [1, ['8', '9', '10']]]
- name: ldp
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: true
pre-indexed: false
throughput: 0.3333333
latency: 4.0 # 1*p467
port_pressure: [[1, '467'], [1, ['8', '9', '10']]]
- name: ldp
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: true
throughput: 0.3333333
latency: 3.0 # 1*p467
port_pressure: [[1, '467'], [1, ['8', '9', '10']]]
- name: ldp
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: true
throughput: 0.3333333
latency: 4.0 # 1*p467
port_pressure: [[1, '467'], [1, ['8', '9', '10']]]
- name: ldp
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: false
throughput: 0.3333333
latency: 3.0 # 1*p467
port_pressure: [[1, '467']]
- name: ldp
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: false
throughput: 0.3333333
latency: 4.0 # 1*p467
port_pressure: [[1, '467']]
- name: ldp
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: true
pre-indexed: false
throughput: 0.3333333
latency: 3.0 # 1*p467
port_pressure: [[1, '467'], [1, ['8', '9', '10']]]
- name: ldp
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: true
pre-indexed: false
throughput: 0.3333333
latency: 4.0 # 1*p467
port_pressure: [[1, '467'], [1, ['8', '9', '10']]]
- name: ldp
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: true
throughput: 0.3333333
latency: 3.0 # 1*p467
port_pressure: [[1, '467'], [1, ['8', '9', '10']]]
- name: ldp
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: true
throughput: 0.3333333
latency: 4.0 # 1*p467
port_pressure: [[1, '467'], [1, ['8', '9', '10']]]
- name: ldp
operands:
- class: register
prefix: d
- class: register
prefix: d
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: false
throughput: 0.3333333
latency: 3.0 # 1*p467
port_pressure: [[1, '467']]
- name: ldp
operands:
- class: register
prefix: d
- class: register
prefix: d
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: false
throughput: 0.3333333
latency: 4.0 # 1*p467
port_pressure: [[1, '467']]
- name: ldp
operands:
- class: register
prefix: d
- class: register
prefix: d
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: true
pre-indexed: false
throughput: 0.3333333
latency: 3.0 # 1*p467
port_pressure: [[1, '467'], [1, ['8', '9', '10']]]
- name: ldp
operands:
- class: register
prefix: d
- class: register
prefix: d
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: true
pre-indexed: false
throughput: 0.3333333
latency: 4.0 # 1*p467
port_pressure: [[1, '467'], [1, ['8', '9', '10']]]
- name: ldp
operands:
- class: register
prefix: d
- class: register
prefix: d
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: true
throughput: 0.3333333
latency: 3.0 # 1*p467
port_pressure: [[1, '467'], [1, ['8', '9', '10']]]
- name: ldp
operands:
- class: register
prefix: d
- class: register
prefix: d
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: true
throughput: 0.3333333
latency: 4.0 # 1*p467
port_pressure: [[1, '467'], [1, ['8', '9', '10']]]
- name: ldp
operands:
- class: register
prefix: q
- class: register
prefix: q
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: false
throughput: 0.3333333
latency: 3.0 # 2*p467
port_pressure: [[2, '467']]
- name: ldp
operands:
- class: register
prefix: q
- class: register
prefix: q
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: false
throughput: 0.3333333
latency: 4.0 # 2*p467
port_pressure: [[2, '467']]
- name: ldp
operands:
- class: register
prefix: q
- class: register
prefix: q
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: true
pre-indexed: false
throughput: 0.3333333
latency: 3.0 # 2*p467
port_pressure: [[2, '467'], [1, ['8', '9', '10']]]
- name: ldp
operands:
- class: register
prefix: q
- class: register
prefix: q
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: true
pre-indexed: false
throughput: 0.3333333
latency: 4.0 # 2*p467
port_pressure: [[2, '467'], [1, ['8', '9', '10']]]
- name: ldp
operands:
- class: register
prefix: q
- class: register
prefix: q
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: true
throughput: 0.3333333
latency: 3.0 # 2*p467
port_pressure: [[2, '467'], [1, ['8', '9', '10']]]
- name: ldp
operands:
- class: register
prefix: q
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: true
throughput: 0.3333333
latency: 4.0 # 2*p467
port_pressure: [[2, '467'], [1, ['8', '9', '10']]]
- name: [lsl, lslv, lsr, lsrv]
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
- class: register
prefix: '*'
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: [lsl, lslv, lsr, lsrv]
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
- class: immediate
imd: int
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: madd # NOTE: if the dependency is via the addend (fourth operand), the latency is only 1cy !!!
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
- class: register
prefix: '*'
- class: register
prefix: '*'
throughput: 1.0
latency: 3.0 # 1*,13 NOTE: if the dependency is via the addend (fourth operand), the latency is only 1cy !!!
port_pressure: [[1, ['13']]]
- name: [msub, mneg]
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
- class: register
prefix: '*'
throughput: 0.5
latency: 3.0 # 1*p12,13
port_pressure: [[1, ['12', '13']]]
- name: [mov, movk, movn, movz]
operands:
- class: register
prefix: x
- class: immediate
imd: int
throughput: 0.16666666
latency: 0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: [mov, movk, movn, movz]
operands:
- class: register
prefix: w
- class: immediate
imd: int
throughput: 0.16666666
latency: 0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: [mov, movk, movn, movz]
operands:
- class: register
prefix: x
- class: register
prefix: x
throughput: 0.16666666
latency: 0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: [mov, movk, movn, movz]
operands:
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.16666666
latency: 0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: mul
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.5
latency: 3.0 # 1*p12,13
port_pressure: [[1, ['12', '13']]]
- name: mul
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: register
prefix: x
throughput: 0.5
latency: 3.0 # 1*p12,13
port_pressure: [[1, ['12', '13']]]
- name: neg
operands:
- class: register
prefix: x
- class: register
prefix: x
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: neg
operands:
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: [negs, ngc, ngcs]
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
throughput: 0.33333333
latency: 1.0 # 1*p89,10
port_pressure: [[1, ['8', '9', '10']]]
- name: [orn, orr]
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: register
prefix: x
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: [orn, orr]
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: immediate
imd: int
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: [orn, orr]
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: [orn, orr]
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: immediate
imd: int
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: [rbit, rev, rev16, rev32]
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: register
prefix: x
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: [rbit, rev, rev16, rev32]
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: ror
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
- class: immediate
imd: int
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: [ror, rorv]
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: [sbc, sbcs]
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
- class: register
prefix: '*'
throughput: 0.33333333
latency: 1.0 # 1*p89,10
port_pressure: [[1, ['8', '9', '10']]]
- name: [sbfiz, sbfm, sbfx]
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
- class: immediate
imd: int
- class: immediate
imd: int
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: sdiv
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
- class: register
prefix: '*'
throughput: 7.0
latency: 2.0 # 2*p12DV
port_pressure: [[2, ['12']]]
- name: [smaddl, smsubl, umaddl, umsubl]
operands:
- class: register
prefix: x
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: x
throughput: 1.0
latency: 3.0 # 1*p13
port_pressure: [[1, ['13']]]
- name: [smnegl, umnegl]
operands:
- class: register
prefix: x
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.5
latency: 3.0 # 1*p12,13
port_pressure: [[1, ['12', '13']]]
- name: [smull, smulh, umulh, umull]
operands:
- class: register
prefix: x
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.5
latency: 3.0 # 1*p12,13
port_pressure: [[1, ['12', '13']]]
- name: [str, stur]
operands:
- class: register
prefix: "*"
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45']]
- name: [str, stur]
operands:
- class: register
prefix: "*"
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45']]
- name: [str, stur]
operands:
- class: register
prefix: "*"
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: true
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45'], [1, ['8', '9', '10']]]
- name: [str, stur]
operands:
- class: register
prefix: "*"
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: true
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45'], [1, ['8', '9', '10']]]
- name: [str, stur]
operands:
- class: register
prefix: "*"
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45'], [1, ['8', '9', '10']]]
- name: [str, stur]
operands:
- class: register
prefix: "*"
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45'], [1, ['8', '9', '10']]]
- name: stp
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45']]
- name: stp
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45']]
- name: stp
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: true
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45'], [1, ['8', '9', '10']]]
- name: stp
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: true
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45'], [1, ['8', '9', '10']]]
- name: stp
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45'], [1, ['8', '9', '10']]]
- name: stp
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45'], [1, ['8', '9', '10']]]
- name: stp
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45']]
- name: stp
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45']]
- name: stp
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: true
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45'], [1, ['8', '9', '10']]]
- name: stp
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: true
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45'], [1, ['8', '9', '10']]]
- name: stp
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45'], [1, ['8', '9', '10']]]
- name: stp
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45'], [1, ['8', '9', '10']]]
- name: stp
operands:
- class: register
prefix: d
- class: register
prefix: d
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45']]
- name: stp
operands:
- class: register
prefix: d
- class: register
prefix: d
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45']]
- name: stp
operands:
- class: register
prefix: d
- class: register
prefix: d
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: true
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45'], [1, ['8', '9', '10']]]
- name: stp
operands:
- class: register
prefix: d
- class: register
prefix: d
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: true
pre-indexed: false
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45'], [1, ['8', '9', '10']]]
- name: stp
operands:
- class: register
prefix: d
- class: register
prefix: d
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45'], [1, ['8', '9', '10']]]
- name: stp
operands:
- class: register
prefix: d
- class: register
prefix: d
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: true
throughput: 0.5
latency: 0.0 # 1*p45
port_pressure: [[1, '45'], [1, ['8', '9', '10']]]
- name: stp
operands:
- class: register
prefix: q
- class: register
prefix: q
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: false
throughput: 0.5
latency: 0.0 # 2*p45
port_pressure: [[2, '45']]
- name: stp
operands:
- class: register
prefix: q
- class: register
prefix: q
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: false
throughput: 0.5
latency: 0.0 # 2*p45
port_pressure: [[2, '45']]
- name: stp
operands:
- class: register
prefix: q
- class: register
prefix: q
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: true
pre-indexed: false
throughput: 0.5
latency: 0.0 # 2*p45
port_pressure: [[2, '45'], [1, ['8', '9', '10']]]
- name: stp
operands:
- class: register
prefix: q
- class: register
prefix: q
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: true
pre-indexed: false
throughput: 0.5
latency: 0.0 # 2*p45
port_pressure: [[2, '45'], [1, ['8', '9', '10']]]
- name: stp
operands:
- class: register
prefix: q
- class: register
prefix: q
- class: memory
base: x
offset: '*'
index: ~
scale: ~
post-indexed: false
pre-indexed: true
throughput: 0.5
latency: 0.0 # 2*p45
port_pressure: [[2, '45'], [1, ['8', '9', '10']]]
- name: stp
operands:
- class: register
prefix: q
- class: register
prefix: q
- class: memory
base: x
offset: '*'
index: '*'
scale: '*'
post-indexed: false
pre-indexed: true
throughput: 0.5
latency: 4.0 # 2*p467
port_pressure: [[2, '467'], [1, ['8', '9', '10']]]
- name: sub
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: immediate
imd: int
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: sub
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: immediate
imd: int
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: sub
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: sub
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: register
prefix: x
throughput: 0.2
latency: 1.0 # 1*p89,10,12,13
port_pressure: [[1, ['8', '9', '10', '12', '13']]]
- name: subs
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: immediate
imd: int
throughput: 0.33333333
latency: 1.0 # 1*p89,10
port_pressure: [[1, ['8', '9', '10']]]
- name: subs
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: immediate
imd: int
throughput: 0.33333333
latency: 1.0 # 1*p89,10
port_pressure: [[1, ['8', '9', '10']]]
- name: subs
operands:
- class: register
prefix: w
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.33333333
latency: 1.0 # 1*p89,10
port_pressure: [[1, ['8', '9', '10']]]
- name: subs
operands:
- class: register
prefix: x
- class: register
prefix: x
- class: register
prefix: x
throughput: 0.33333333
latency: 1.0 # 1*p89,10
port_pressure: [[1, ['8', '9', '10']]]
- name: sxtb
operands:
- class: register
prefix: x
- class: register
prefix: w
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name: [uxtb, uxth]
operands:
- class: register
prefix: w
- class: register
prefix: w
throughput: 0.16666666
latency: 1.0 # 1*p89,10,11,12,13
port_pressure: [[1, ['8', '9', '10', '11', '12', '13']]]
- name:
operands:
- class: register
prefix: v
shape: '*'
width: '*'
- class: immediate
imd: int
throughput: 0.
latency: 1.0 # 1*p0123
port_pressure: [[1, '0123']]
- name: fadd
operands:
- class: register
prefix: v
shape: '*'
width: '*'
- class: register
prefix: v
shape: '*'
width: '*'
- class: register
prefix: v
shape: '*'
width: '*'
throughput: 0.25
latency: 3.0 # 1*p0123
port_pressure: [[1, '0123']]
- name: fadd
operands:
- class: register
prefix: '*'
- class: register
prefix: '*'
- class: register
prefix: '*'
throughput: 0.25
latency: 3.0 # 1*p0123
port_pressure: [[1, '0123']]
- name: fdiv
operands:
- class: register
prefix: v
shape: d
width: '*'
- class: register
prefix: v
shape: d
width: '*'
- class: register
prefix: v
shape: d
width: '*'
throughput: 1.0
latency: 10.0 # 1*p3
port_pressure: [[1, '3']]
- name: fdiv
operands:
- class: register
prefix: d
- class: register
prefix: d
- class: register
prefix: d
throughput: 1.0
latency: 10.0 # 1*p3
port_pressure: [[1, '3']]
- name: fdiv
operands:
- class: register
prefix: v
shape: s
width: '*'
- class: register
prefix: v
shape: s
width: '*'
- class: register
prefix: v
shape: s
width: '*'
throughput: 1.0
latency: 8.0 # 1*p3
port_pressure: [[1, '3']]
- name: fdiv
operands:
- class: register
prefix: s
- class: register
prefix: s
- class: register
prefix: s
throughput: 1.0
latency: 8.0 # 1*p3
port_pressure: [[1, '3']]
- name: fmla
operands:
- class: register
prefix: v
shape: s
width: '*'
- class: register
prefix: v
shape: s
width: '*'
- class: register
prefix: v
shape: s
width: '*'
throughput: 0.5
latency: 2.0 # 1*p45
port_pressure: [[1, '45']]
- name: fmla
operands:
- class: register
prefix: v
shape: d
width: '*'
- class: register
prefix: v
shape: d
width: '*'
- class: register
prefix: v
shape: d
width: '*'
throughput: 0.5
latency: 2.0 # 1*p45
port_pressure: [[1, '45']]
- name: fmov
operands:
- {class: register, prefix: s}
- {class: immediate, imd: double}
latency: ~ # 1*p45
port_pressure: [[1, '45']]
throughput: 0.5
- name: fmul
operands:
- class: register
prefix: v
shape: s
width: '*'
- class: register
prefix: v
shape: s
width: '*'
- class: register
prefix: v
shape: s
width: '*'
throughput: 0.5
latency: 3.0 # 1*p45
port_pressure: [[1, '45']]
- name: fmul
operands:
- class: register
prefix: v
shape: d
width: '*'
- class: register
prefix: v
shape: d
width: '*'
- class: register
prefix: v
shape: d
width: '*'
throughput: 0.5
latency: 3.0 # 1*p45
port_pressure: [[1, '45']]
- name: fmul
operands:
- class: register
prefix: d
- class: register
prefix: d
- class: register
prefix: d
throughput: 0.5
latency: 3.0 # 1*p45
port_pressure: [[1, '45']]
- name: frecpe
operands:
- class: register
prefix: v
shape: s
width: '*'
- class: register
prefix: v
shape: s
width: '*'
- class: register
prefix: v
shape: s
width: '*'
throughput: 2.0
latency: 4.0 # 1*p4
port_pressure: [[2, '4']]
- name: frecpe
operands:
- class: register
prefix: v
shape: d
width: '*'
- class: register
prefix: v
shape: d
width: '*'
- class: register
prefix: v
shape: d
width: '*'
throughput: 1.0
latency: 3.0 # 1*p4
port_pressure: [[1, '4']]
- name: fsub
operands:
- class: register
prefix: v
shape: s
width: '*'
- class: register
prefix: v
shape: s
width: '*'
- class: register
prefix: v
shape: s
width: '*'
throughput: 0.5
latency: 2.0 # 1*p45
port_pressure: [[1, '45']]
- name: fsub
operands:
- class: register
prefix: v
shape: d
width: '*'
- class: register
prefix: v
shape: d
width: '*'
- class: register
prefix: v
shape: d
width: '*'
throughput: 0.5
latency: 2.0 # 1*p45
port_pressure: [[1, '45']]
- name: mov
operands:
- class: register
prefix: v
shape: b
width: '*'
- class: register
prefix: v
shape: b
width: '*'
throughput: 0.5
latency: 2.0 # 1*p45
port_pressure: [[1, '45']]
- name: dup
operands:
- class: register
prefix: d
- class: register
prefix: v
shape: d
width: '*'
throughput: 0.5
latency: 2.0 # 1*p45
port_pressure: [[1, '45']]
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