mirror of
https://github.com/RRZE-HPC/OSACA.git
synced 2025-12-15 16:40:05 +01:00
ebf76caa18
- Enhanced ImmediateOperand with reloc_type and symbol attributes for better RISC-V support - Updated RISC-V parser with relocation type support (%hi, %lo, %pcrel_hi, etc.) - Renamed example files from rv6 to rv64 for consistency - Updated related configuration and test files - All 115 tests pass successfully
44 lines
681 B
ArmAsm
44 lines
681 B
ArmAsm
j2d_riscv:
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.L5:
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vsetvli a5,a7,e64,m1,ta,ma
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vle64.v v4,0(t1)
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vle64.v v1,0(a0)
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vle64.v v3,0(t3)
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vle64.v v2,0(a6)
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slli a4,a5,3
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sub a7,a7,a5
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add t1,t1,a4
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vfadd.vv v1,v1,v4
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add a0,a0,a4
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add t3,t3,a4
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add a6,a6,a4
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vfadd.vv v1,v1,v3
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vfadd.vv v1,v1,v2
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vfmul.vf v1,v1,fa4
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vse64.v v1,0(a2)
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add a2,a2,a4
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bne a7,zero,.L5
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addi t5,t5,1
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addi a1,a1,8
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addi t4,t4,8
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bne t5,t0,.L4
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.L7:
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fld fa5,0(a0)
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fld fa1,-16(a5)
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fld fa2,0(a5)
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fld fa3,0(a6)
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fadd.d fa5,fa5,fa1
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addi a5,a5,8
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addi a0,a0,8
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addi a6,a6,8
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addi a2,a2,8
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fadd.d fa5,fa5,fa2
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fadd.d fa5,fa5,fa3
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fmul.d fa5,fa5,fa4
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fsd fa5,-8(a2)
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bne a5,t1,.L7
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addi t5,t5,1
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addi a1,a1,8
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addi t4,t4,8
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bne t5,t0,.L4
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j .L17 |