Metehan Dundar 480c0dcac0 Merge branch 'master' into dev/risc-v

2025-05-08 12:23:22 +02:00

..

aarch64.yml

Merge remote-tracking branch 'origin/master' into InstrucForm

2023-12-16 12:14:36 +01:00

riscv.yml

Add RISC-V vector add and triad benchmarks with corresponding Makefiles and assembly files

2025-05-08 11:57:06 +02:00

x86.yml

Fix the x86 ISA description to indicate that the register of SAR and SAL is read/write.

2025-03-27 22:47:32 +01:00