From 023a49c55ed5f3ebabab8969013533dfbdfdff33 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Tue, 11 Nov 2025 13:54:20 +1100 Subject: [PATCH] mimxrt/boards/PHYBOARD_RT1170: Add PHYBOARD-RT1170 board support. Adds board support for PHYTEC phyBOARD-RT1170 Development Kit featuring MIMXRT1176 dual-core (Cortex-M7/M4), 64MB SDRAM, 16MB QSPI Flash, dual Gigabit Ethernet (DP83867 RGMII + KSZ8081 RMII), USB 2.0, MIPI-DSI/CSI, audio codec, CAN FD, RS-232, microSD, and M.2 Key E connector. Signed-off-by: Andrew Leech --- .../mimxrt/boards/PHYBOARD_RT1170/board.json | 28 ++ .../mimxrt/boards/PHYBOARD_RT1170/manifest.py | 3 + .../boards/PHYBOARD_RT1170/mpconfigboard.h | 308 ++++++++++++++++++ .../boards/PHYBOARD_RT1170/mpconfigboard.mk | 31 ++ ports/mimxrt/boards/PHYBOARD_RT1170/pins.csv | 127 ++++++++ pyproject.toml | 2 +- 6 files changed, 498 insertions(+), 1 deletion(-) create mode 100644 ports/mimxrt/boards/PHYBOARD_RT1170/board.json create mode 100644 ports/mimxrt/boards/PHYBOARD_RT1170/manifest.py create mode 100644 ports/mimxrt/boards/PHYBOARD_RT1170/mpconfigboard.h create mode 100644 ports/mimxrt/boards/PHYBOARD_RT1170/mpconfigboard.mk create mode 100644 ports/mimxrt/boards/PHYBOARD_RT1170/pins.csv diff --git a/ports/mimxrt/boards/PHYBOARD_RT1170/board.json b/ports/mimxrt/boards/PHYBOARD_RT1170/board.json new file mode 100644 index 0000000000..6eaafe1f48 --- /dev/null +++ b/ports/mimxrt/boards/PHYBOARD_RT1170/board.json @@ -0,0 +1,28 @@ +{ + "deploy": [ + "../deploy_mimxrt.md" + ], + "docs": "", + "features": [ + "Audio Codec", + "CAN", + "Camera", + "Display", + "Dual-core", + "Ethernet", + "External Flash", + "External RAM", + "IMU", + "RGB LED", + "USB", + "microSD" + ], + "images": [ + "phyBOARD-RT1170_front.png" + ], + "mcu": "mimxrt", + "product": "phyBOARD-RT1170 Development Kit", + "thumbnail": "", + "url": "https://www.phytec.com/product/phyboard-rt1170-development-kit/", + "vendor": "PHYTEC" +} diff --git a/ports/mimxrt/boards/PHYBOARD_RT1170/manifest.py b/ports/mimxrt/boards/PHYBOARD_RT1170/manifest.py new file mode 100644 index 0000000000..5986677220 --- /dev/null +++ b/ports/mimxrt/boards/PHYBOARD_RT1170/manifest.py @@ -0,0 +1,3 @@ +include("../manifest.py") +require("bundle-networking") +include("$(MPY_DIR)/extmod/asyncio/manifest.py") diff --git a/ports/mimxrt/boards/PHYBOARD_RT1170/mpconfigboard.h b/ports/mimxrt/boards/PHYBOARD_RT1170/mpconfigboard.h new file mode 100644 index 0000000000..3cb49ab2cc --- /dev/null +++ b/ports/mimxrt/boards/PHYBOARD_RT1170/mpconfigboard.h @@ -0,0 +1,308 @@ +#define MICROPY_HW_BOARD_NAME "phyBOARD-RT1170 Development Kit" +#define MICROPY_HW_MCU_NAME "MIMXRT1176DVMAA" + +#define MICROPY_PY_NETWORK_HOSTNAME_DEFAULT "mpy-phyboard" + +#define MICROPY_EVENT_POLL_HOOK \ + do { \ + extern void mp_handle_pending(bool); \ + mp_handle_pending(true); \ + } while (0); + +// phyBOARD-RT1170 SoM onboard LEDs (red and green from phyCORE SoM) +// Carrier board provides additional RGB LEDs via GPIO +#define MICROPY_HW_LED1_PIN (pin_GPIO_LPSR_07) // SoM Red LED +#define MICROPY_HW_LED2_PIN (pin_GPIO_LPSR_08) // SoM Green LED +#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin)) // LEDs are active low +#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin)) + +// phyBOARD carrier board RGB LEDs +#define MICROPY_HW_LED3_PIN (pin_GPIO_AD_14) // Carrier Red LED +#define MICROPY_HW_LED4_PIN (pin_GPIO_LPSR_13) // Carrier Green LED + +#define MICROPY_HW_NUM_PIN_IRQS (6 * 32) + +// Define mapping hardware UART # to logical UART # +// phyBOARD-RT1170 UART interfaces +// LPUART1 -> 0 (GPIO_AD_24/25) - Primary debug/console (SoM) +// LPUART2 -> 1 (GPIO_DISP_B2_10/11/12/13) - Carrier board +// LPUART3 -> 2 (GPIO_AD_30/31) - General purpose (SoM) +// LPUART5 -> 3 (GPIO_AD_28/29) - Expansion (SoM) +// LPUART6 -> 4 (GPIO_EMC_B1_40/41) - Console UART (FT2232H - Carrier) +// LPUART7 -> 5 (GPIO_DISP_B2_06/07) - General purpose (SoM) +// LPUART8 -> 6 (GPIO_AD_02/03/04/05) - RS-232 (Carrier) + +#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0]) +#define MICROPY_HW_UART_INDEX { 1, 2, 3, 5, 6, 7, 8 } + +#define IOMUX_TABLE_UART \ + { IOMUXC_GPIO_AD_24_LPUART1_TXD }, { IOMUXC_GPIO_AD_25_LPUART1_RXD }, \ + { IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD }, { IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD }, \ + { IOMUXC_GPIO_AD_30_LPUART3_TXD }, { IOMUXC_GPIO_AD_31_LPUART3_RXD }, \ + { 0 }, { 0 }, \ + { IOMUXC_GPIO_AD_28_LPUART5_TXD }, { IOMUXC_GPIO_AD_29_LPUART5_RXD }, \ + { IOMUXC_GPIO_EMC_B1_40_LPUART6_TXD }, { IOMUXC_GPIO_EMC_B1_41_LPUART6_RXD }, \ + { IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD }, { IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD }, \ + { IOMUXC_GPIO_AD_02_LPUART8_TXD }, { IOMUXC_GPIO_AD_03_LPUART8_RXD }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, + +#define IOMUX_TABLE_UART_CTS_RTS \ + { 0 }, { 0 }, \ + { IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B }, { IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { IOMUXC_GPIO_AD_04_LPUART8_CTS_B }, { IOMUXC_GPIO_AD_05_LPUART8_RTS_B }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, + +// Define the mapping hardware SPI # to logical SPI # +// phyCORE SoM basic SPI interfaces available on connector +// LPSPI1 -> 0 (GPIO_AD_28/29/30/31) +// LPSPI2 -> 1 (GPIO_AD_24/25/26/27) + +#define MICROPY_HW_SPI_INDEX { 1, 2 } + +#define IOMUX_TABLE_SPI \ + { IOMUXC_GPIO_AD_28_LPSPI1_SCK }, { IOMUXC_GPIO_AD_29_LPSPI1_PCS0 }, \ + { IOMUXC_GPIO_AD_30_LPSPI1_SOUT }, { IOMUXC_GPIO_AD_31_LPSPI1_SIN }, \ + { IOMUXC_GPIO_AD_24_LPSPI2_SCK }, { IOMUXC_GPIO_AD_25_LPSPI2_PCS0 }, \ + { IOMUXC_GPIO_AD_26_LPSPI2_SOUT }, { IOMUXC_GPIO_AD_27_LPSPI2_SIN }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, + + +#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx, \ + kDmaRequestMuxLPSPI3Rx, kDmaRequestMuxLPSPI4Rx } + +#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx, \ + kDmaRequestMuxLPSPI3Tx, kDmaRequestMuxLPSPI4Tx } + +// Define the mapping hardware I2C # to logical I2C # +// phyBOARD-RT1170 I2C interfaces +// LPI2C1 -> 0 (GPIO_AD_32/33) - EEPROM (SoM) +// LPI2C2 -> 1 (GPIO_AD_18/19) - EEPROM + Accelerometer (Carrier) +// LPI2C3 -> 2 (GPIO_DISP_B2_10/11) - Reserved (SoM) +// LPI2C5 -> 3 (GPIO_LPSR_08/09, GPIO_AD_26/27) - Audio Codec + Accelerometer (Carrier) + +#define MICROPY_HW_I2C_INDEX { 1, 2, 3, 5 } + +#define IOMUX_TABLE_I2C \ + { IOMUXC_GPIO_AD_32_LPI2C1_SCL }, { IOMUXC_GPIO_AD_33_LPI2C1_SDA }, \ + { IOMUXC_GPIO_AD_18_LPI2C2_SCL }, { IOMUXC_GPIO_AD_19_LPI2C2_SDA }, \ + { IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL }, { IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA }, \ + { 0 }, { 0 }, \ + { IOMUXC_GPIO_LPSR_08_LPI2C5_SDA }, { IOMUXC_GPIO_LPSR_09_LPI2C5_SCL }, \ + { 0 }, { 0 }, + +#define MICROPY_PY_MACHINE_I2S (1) +#define MICROPY_HW_I2S_NUM (1) +#define I2S_CLOCK_MUX { 0, kCLOCK_Root_Sai1, kCLOCK_Root_Sai2, kCLOCK_Root_Sai3, kCLOCK_Root_Sai4 } +#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx, kDmaRequestMuxSai3Rx, kDmaRequestMuxSai4Rx } +#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx, kDmaRequestMuxSai3Tx, kDmaRequestMuxSai4Tx } +#define I2S_WM8960_RX_MODE (1) +#define I2S_AUDIO_PLL_CLOCK (4U) +#define DMAMUX DMAMUX0 + +#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \ + { \ + .hw_id = _hwid, \ + .fn = _fn, \ + .mode = _mode, \ + .name = MP_QSTR_##_pin, \ + .iomux = {_iomux}, \ + } + +#define I2S_GPIO_MAP \ + { \ + I2S_GPIO(1, MCK, TX, GPIO_AD_17, IOMUXC_GPIO_AD_17_SAI1_MCLK), \ + I2S_GPIO(1, SCK, RX, GPIO_AD_19, IOMUXC_GPIO_AD_19_SAI1_RX_BCLK), \ + I2S_GPIO(1, WS, RX, GPIO_AD_18, IOMUXC_GPIO_AD_18_SAI1_RX_SYNC), \ + I2S_GPIO(1, SD, RX, GPIO_AD_20, IOMUXC_GPIO_AD_20_SAI1_RX_DATA00), \ + I2S_GPIO(1, SCK, TX, GPIO_AD_22, IOMUXC_GPIO_AD_22_SAI1_TX_BCLK), \ + I2S_GPIO(1, WS, TX, GPIO_AD_23, IOMUXC_GPIO_AD_23_SAI1_TX_SYNC), \ + I2S_GPIO(1, SD, TX, GPIO_AD_21, IOMUXC_GPIO_AD_21_SAI1_TX_DATA00), \ + } + +// USDHC1 (SDCARD) +#define MICROPY_PY_MACHINE_SDCARD 0 +#if MICROPY_PY_MACHINE_SDCARD +#define USDHC_DUMMY_PIN NULL, 0 +#define MICROPY_USDHC1 \ + { \ + .cmd = {GPIO_SD_B1_00_USDHC1_CMD}, \ + .clk = { GPIO_SD_B1_01_USDHC1_CLK }, \ + .cd_b = { USDHC_DUMMY_PIN }, \ + .data0 = { GPIO_SD_B1_02_USDHC1_DATA0 }, \ + .data1 = { GPIO_SD_B1_03_USDHC1_DATA1 }, \ + .data2 = { GPIO_SD_B1_04_USDHC1_DATA2 }, \ + .data3 = { GPIO_SD_B1_05_USDHC1_DATA3 }, \ + } +#define USDHC_DATA3_PULL_DOWN_ON_BOARD (1) +#endif + +// Network definitions + +// phyBOARD-RT1170 Dual Ethernet configuration +// Port 0: KSZ8081 100Mbps RMII PHY on carrier board (PBA-C-26) +// Port 1: DP83867 1Gbps RGMII PHY on phyCORE SoM + +// Primary Ethernet (100M RMII) - KSZ8081 on carrier board +#define ENET_PHY_ADDRESS (1) // KSZ8081 PHY address 001b +#define ENET_PHY KSZ8081 +#define ENET_PHY_OPS phyksz8081_ops + +// ENET RMII pin configuration - connected to carrier board KSZ8081 +#define IOMUX_TABLE_ENET \ + { IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, 0, 0x06u }, \ + { IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, 0, 0x06u }, \ + { IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, 0, 0x06u }, \ + { IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, 0, 0x02u }, \ + { IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, 0, 0x02u }, \ + { IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, 0, 0x06u }, \ + { IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK, 1, 0x03u }, \ + { IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER, 0, 0x06u }, \ + { IOMUXC_GPIO_AD_33_ENET_MDIO, 0, 0x06u }, \ + { IOMUXC_GPIO_AD_32_ENET_MDC, 0, 0x06u }, + +// Secondary Ethernet (1G RGMII) - DP83867 on phyCORE SoM +#define ENET_1_PHY_ADDRESS (0) +#define ENET_1_PHY DP83867 +#define ENET_1_PHY_OPS phydp83867_ops + +// ENET_1G RGMII pin configuration - full RGMII pins for Gigabit operation +#define IOMUX_TABLE_ENET_1 \ + { IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN, 0, 0x08U }, \ + { IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK, 0, 0x08U }, \ + { IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00, 0, 0x08U }, \ + { IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01, 0, 0x08U }, \ + { IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02, 0, 0x08U }, \ + { IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03, 0, 0x08U }, \ + { IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03, 0, 0x0CU }, \ + { IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02, 0, 0x0CU }, \ + { IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01, 0, 0x0CU }, \ + { IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00, 0, 0x0CU }, \ + { IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN, 0, 0x0CU }, \ + { IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO, 0, 0x0CU }, \ + { IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO, 0, 0x06u }, \ + { IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC, 0, 0x06u }, + + +// --- SEMC --- // +#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 +#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 +#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 +#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 +#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 +#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 +#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 +#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 +#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 +#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 +#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 +#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 +#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 +#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 +#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 +#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 + +#define MIMXRT_IOMUXC_SEMC_ADDR00 IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 +#define MIMXRT_IOMUXC_SEMC_ADDR01 IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 +#define MIMXRT_IOMUXC_SEMC_ADDR02 IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 +#define MIMXRT_IOMUXC_SEMC_ADDR03 IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 +#define MIMXRT_IOMUXC_SEMC_ADDR04 IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 +#define MIMXRT_IOMUXC_SEMC_ADDR05 IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 +#define MIMXRT_IOMUXC_SEMC_ADDR06 IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 +#define MIMXRT_IOMUXC_SEMC_ADDR07 IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 +#define MIMXRT_IOMUXC_SEMC_ADDR08 IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 +#define MIMXRT_IOMUXC_SEMC_ADDR09 IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 +#define MIMXRT_IOMUXC_SEMC_ADDR10 IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 +#define MIMXRT_IOMUXC_SEMC_ADDR11 IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 +#define MIMXRT_IOMUXC_SEMC_ADDR12 IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 + +#define MIMXRT_IOMUXC_SEMC_BA0 IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 +#define MIMXRT_IOMUXC_SEMC_BA1 IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 +#define MIMXRT_IOMUXC_SEMC_CAS IOMUXC_GPIO_EMC_B1_24_SEMC_CAS +#define MIMXRT_IOMUXC_SEMC_RAS IOMUXC_GPIO_EMC_B1_25_SEMC_RAS +#define MIMXRT_IOMUXC_SEMC_CLK IOMUXC_GPIO_EMC_B1_26_SEMC_CLK +#define MIMXRT_IOMUXC_SEMC_CKE IOMUXC_GPIO_EMC_B1_27_SEMC_CKE +#define MIMXRT_IOMUXC_SEMC_WE IOMUXC_GPIO_EMC_B1_28_SEMC_WE +#define MIMXRT_IOMUXC_SEMC_DM00 IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 +#define MIMXRT_IOMUXC_SEMC_DM01 IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 +#define MIMXRT_IOMUXC_SEMC_DQS IOMUXC_GPIO_EMC_B1_39_SEMC_DQS + +#define MIMXRT_IOMUXC_SEMC_CS0 IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 + +#define MIMXRT_IOMUXC_SEMC_DATA16 IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 +#define MIMXRT_IOMUXC_SEMC_DATA17 IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 +#define MIMXRT_IOMUXC_SEMC_DATA18 IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 +#define MIMXRT_IOMUXC_SEMC_DATA19 IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 +#define MIMXRT_IOMUXC_SEMC_DATA20 IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 +#define MIMXRT_IOMUXC_SEMC_DATA21 IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 +#define MIMXRT_IOMUXC_SEMC_DATA22 IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 +#define MIMXRT_IOMUXC_SEMC_DATA23 IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 +#define MIMXRT_IOMUXC_SEMC_DM02 IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 + +#define MIMXRT_IOMUXC_SEMC_DATA24 IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 +#define MIMXRT_IOMUXC_SEMC_DATA25 IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 +#define MIMXRT_IOMUXC_SEMC_DATA26 IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 +#define MIMXRT_IOMUXC_SEMC_DATA27 IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 +#define MIMXRT_IOMUXC_SEMC_DATA28 IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 +#define MIMXRT_IOMUXC_SEMC_DATA29 IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 +#define MIMXRT_IOMUXC_SEMC_DATA30 IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 +#define MIMXRT_IOMUXC_SEMC_DATA31 IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 +#define MIMXRT_IOMUXC_SEMC_DM03 IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 +#define MIMXRT_IOMUXC_SEMC_DQS4 IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 + +#if MICROPY_PY_MACHINE_I2S +#define MICROPY_BOARD_ROOT_POINTERS \ + struct _machine_i2s_obj_t *machine_i2s_obj[MICROPY_HW_I2S_NUM]; +#endif + +// AUTOGENERATED by update.py from copier +#define MICROPY_HW_USB_CDC_NUM (2) +#define MICROPY_HW_USB_MSC (0) +#define MICROPY_HW_USB_HID (0) + +#define MICROPY_HW_USB_MANUFACTURER_STRING "PHYTEC" +#define MICROPY_HW_USB_PRODUCT_HS_STRING "phyBOARD-RT1170 Development Kit" +#define MICROPY_HW_USB_PRODUCT_FS_STRING "phyBOARD-RT1170 Development Kit" +#define MICROPY_HW_USB_CONFIGURATION_HS_STRING "phyBOARD Config" +#define MICROPY_HW_USB_INTERFACE_HS_STRING "phyBOARD Interface" +#define MICROPY_HW_USB_CONFIGURATION_FS_STRING "phyBOARD Config" +#define MICROPY_HW_USB_INTERFACE_FS_STRING "phyBOARD Interface" + +#define MBOOT_USBD_MANUFACTURER_STRING "PHYTEC" +#define MBOOT_USBD_PRODUCT_STRING "phyBOARD Boot" + +// phyBOARD-RT1170 Development Kit hardware features + +// Onboard EEPROM (M24C32 - 32Kbit) +#define MICROPY_HW_EEPROM_I2C_BUS (0) // On LPI2C1 (SoM) +#define MICROPY_HW_EEPROM_ADDR (0x50) + +// Carrier board peripherals +// Audio Codec: TLV320AIC3110 on LPI2C5 (I2C address: 0x18) +// Accelerometer: ICM-40627 on LPI2C2 (I2C address: 0x6B) +// CAN Interface: CAN3 (GPIO_LPSR_00/01) +// RS-232 Serial: LPUART8 (GPIO_AD_02/03/04/05) +// User Button: GPIO_AD_35 +// RGB LEDs: GPIO_AD_14 (red), GPIO_LPSR_13 (green) +// microSD Card Slot: USDHC1 +// M.2 Connector (Key E): WiFi/Bluetooth modules + +// Basic ADC channels available on connector +#define MICROPY_HW_ADC_NUM_CHANNELS (16) // GPIO_AD domain pins diff --git a/ports/mimxrt/boards/PHYBOARD_RT1170/mpconfigboard.mk b/ports/mimxrt/boards/PHYBOARD_RT1170/mpconfigboard.mk new file mode 100644 index 0000000000..9cca7a54ab --- /dev/null +++ b/ports/mimxrt/boards/PHYBOARD_RT1170/mpconfigboard.mk @@ -0,0 +1,31 @@ +MCU_SERIES = MIMXRT1176 +MCU_VARIANT = MIMXRT1176DVMAA +MCU_CORE = _cm7 + +MICROPY_FLOAT_IMPL = double +MICROPY_HW_FLASH_TYPE ?= qspi_nor_flash +MICROPY_HW_FLASH_SIZE ?= 0x1000000 # 16MB +MICROPY_HW_FLASH_RESERVED ?= 0x100000 # 1MB CM4 Code address space +MICROPY_HW_FLASH_CLK = kFlexSpiSerialClk_100MHz +MICROPY_HW_FLASH_QE_CMD = 0x31 +MICROPY_HW_FLASH_QE_ARG = 0x02 +# phyCORE SoM flash timing - use loopback from DQS pad for better signal integrity +MICROPY_HW_FLASH_DQS = kFlexSPIReadSampleClk_LoopbackFromDqsPad + +MICROPY_HW_SDRAM_AVAIL = 1 +MICROPY_HW_SDRAM_SIZE = 0x4000000 # 64MB + +MICROPY_PY_LWIP = 1 +MICROPY_PY_SSL = 1 +MICROPY_SSL_MBEDTLS = 1 +MICROPY_PY_OPENAMP = 1 +MICROPY_PY_OPENAMP_REMOTEPROC = 1 + +FROZEN_MANIFEST ?= $(BOARD_DIR)/manifest.py + +CFLAGS += -DCPU_MIMXRT1176DVMAA_cm7 \ + -DMIMXRT117x_SERIES \ + -DENET_ENHANCEDBUFFERDESCRIPTOR_MODE=1 \ + -DCPU_HEADER_H='<$(MCU_SERIES)$(MCU_CORE).h>' \ + -DUSB1_BASE=USB_OTG1_BASE \ + -DUSB2_BASE=USB_OTG2_BASE diff --git a/ports/mimxrt/boards/PHYBOARD_RT1170/pins.csv b/ports/mimxrt/boards/PHYBOARD_RT1170/pins.csv new file mode 100644 index 0000000000..c0222d9b25 --- /dev/null +++ b/ports/mimxrt/boards/PHYBOARD_RT1170/pins.csv @@ -0,0 +1,127 @@ +# phyBOARD-RT1170 Development Kit Pin Mapping +# phyCORE-i.MX RT1170 SoM + PBA-C-26 Carrier Board + +# LEDs - phyCORE SoM onboard (active low) +LED_SOM_RED,GPIO_LPSR_07 +LED_SOM_GREEN,GPIO_LPSR_08 + +# LEDs - Carrier board RGB LEDs (active low) +LED_CARRIER_RED,GPIO_AD_14 +LED_CARRIER_GREEN,GPIO_LPSR_13 + +# Buttons +USER_BUTTON,GPIO_AD_35 +POWER_BUTTON,GPIO_LPSR_04 +WAKE_BUTTON,GPIO_LPSR_03 +RESET_BUTTON,GPIO_LPSR_02 + +# Primary UART interfaces +UART1_TX,GPIO_AD_24 +UART1_RX,GPIO_AD_25 + +# Additional UART interfaces (Carrier board) +UART2_TX,GPIO_DISP_B2_10 +UART2_RX,GPIO_DISP_B2_11 +UART2_CTS,GPIO_DISP_B2_13 +UART2_RTS,GPIO_DISP_B2_12 + +UART5_TX,GPIO_AD_28 +UART5_RX,GPIO_AD_29 + +UART6_TX,GPIO_EMC_B1_40 +UART6_RX,GPIO_EMC_B1_41 + +UART7_TX,GPIO_DISP_B2_06 +UART7_RX,GPIO_DISP_B2_07 + +UART8_TX_RS232,GPIO_AD_02 +UART8_RX_RS232,GPIO_AD_03 +UART8_CTS,GPIO_AD_04 +UART8_RTS,GPIO_AD_05 + +# I2C interfaces +I2C1_SCL,GPIO_AD_32 +I2C1_SDA,GPIO_AD_33 + +I2C2_SCL,GPIO_AD_18 +I2C2_SDA,GPIO_AD_19 + +I2C3_SCL,GPIO_DISP_B2_10 +I2C3_SDA,GPIO_DISP_B2_11 + +I2C5_SCL,GPIO_LPSR_09 +I2C5_SDA,GPIO_LPSR_08 + +# SPI interface +SPI1_SCK,GPIO_AD_28 +SPI1_CS,GPIO_AD_29 + +# Display interface (MIPI-DSI) +MIPI_DSI_DP0,GPIO_DISP_B1_02 +MIPI_DSI_DN0,GPIO_DISP_B1_03 +MIPI_DSI_DP1,GPIO_DISP_B1_00 +MIPI_DSI_DN1,GPIO_DISP_B1_01 +MIPI_DSI_CKP,GPIO_DISP_B1_05 +MIPI_DSI_CKN,GPIO_DISP_B1_04 + +# Display control pins +LCD_RST_B,GPIO_DISP_B2_14 +LCD_PWR_EN,GPIO_AD_26 +LCD_BACKLIGHT_CTL,GPIO_AD_27 +CTP_INT,GPIO_AD_26 +CTP_RST_B,GPIO_DISP_B2_15 + +# Camera interface (MIPI-CSI) - on SoM connector (via pin definitions) +# Note: MIPI-CSI differential pairs are on SoM - reference schematic for pin assignments + +# Accelerometer (ICM-40627 on LPI2C2) +ACCEL_INT1,GPIO_AD_26 +ACCEL_INT2,GPIO_AD_27 + +# Audio codec (TLV320AIC3110 on LPI2C5 and SAI1) +SAI1_TX_BCLK,GPIO_AD_22 +SAI1_TX_SYNC,GPIO_AD_23 +SAI1_TX_DATA,GPIO_AD_21 +SAI1_RX_DATA,GPIO_AD_20 +SAI1_MCLK,GPIO_AD_17 + +# CAN interface (CAN3) +CAN3_TX,GPIO_LPSR_00 +CAN3_RX,GPIO_LPSR_01 + +# SD Card interface (USDHC1) +SD1_CLK,GPIO_SD_B1_01 +SD1_CMD,GPIO_SD_B1_00 +SD1_DATA0,GPIO_SD_B1_02 +SD1_DATA1,GPIO_SD_B1_03 +SD1_DATA2,GPIO_SD_B1_04 +SD1_DATA3,GPIO_SD_B1_05 + +# Basic ADC channels +ADC1_CH0,GPIO_AD_00 +ADC1_CH1,GPIO_AD_01 +ADC1_CH2,GPIO_AD_02 +ADC1_CH3,GPIO_AD_03 + +# GPIO expansion connector +GPIO_CONN_16,GPIO_AD_16 +GPIO_CONN_17,GPIO_AD_17 +GPIO_CONN_18,GPIO_AD_18 +GPIO_CONN_19,GPIO_AD_19 +GPIO_CONN_20,GPIO_AD_20 +GPIO_CONN_21,GPIO_AD_21 +GPIO_CONN_22,GPIO_AD_22 +GPIO_CONN_23,GPIO_AD_23 +GPIO_CONN_26,GPIO_AD_26 +GPIO_CONN_27,GPIO_AD_27 +GPIO_CONN_LPSR_09,GPIO_LPSR_09 +GPIO_CONN_LPSR_10,GPIO_LPSR_10 +GPIO_CONN_LPSR_11,GPIO_LPSR_11 +GPIO_CONN_LPSR_12,GPIO_LPSR_12 + +# JTAG interface +JTAG_TCK,GPIO_LPSR_14 +JTAG_TMS,GPIO_LPSR_15 +JTAG_TDI,GPIO_LPSR_12 +JTAG_TDO,GPIO_LPSR_11 +JTAG_nTRST,GPIO_LPSR_10 diff --git a/pyproject.toml b/pyproject.toml index 1cf57166e1..2f71058f60 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -1,7 +1,7 @@ [tool.codespell] count = "" ignore-regex = '\b[A-Z]{3}\b' -ignore-words-list = "ans,asend,deques,dout,emac,extint,hsi,iput,mis,notin,numer,ser,shft,synopsys,technic,ure,curren" +ignore-words-list = "ans,asend,deques,dout,emac,extint,hsi,iput,mis,notin,numer,ser,shft,som,synopsys,technic,ure,curren" quiet-level = 3 skip = """ */build*,\