Lerking/micropython
1
0
Fork 0
mirror of https://github.com/micropython/micropython.git synced 2025-12-16 09:50:15 +01:00
Code Issues Actions 27 Packages Projects Releases Wiki Activity

py/emitnative: Ensure load_subscr does not clobber existing REG_ARG_2.

Browse Source 
Follow up from a similar fix in 426785a19e

Fixes issue #6314.

Signed-off-by: Damien George <damien@micropython.org>
This commit is contained in:
Damien George
2022-11-11 12:25:32 +11:00
parent 451ded8d7b
commit 0698dd72ea
3 changed files with 17 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
py/emitnative.c
View File

@@ -1527,6 +1527,7 @@ STATIC void emit_native_load_subscr(emit_t *emit) {
break;
}
#endif
need_reg_single(emit, reg_index, 0);
ASM_MOV_REG_IMM(emit->as, reg_index, index_value);
ASM_ADD_REG_REG(emit->as, reg_index, reg_base); // add index to base
reg_base = reg_index;
@@ -1544,6 +1545,7 @@ STATIC void emit_native_load_subscr(emit_t *emit) {
break;
}
#endif
need_reg_single(emit, reg_index, 0);
ASM_MOV_REG_IMM(emit->as, reg_index, index_value << 1);
ASM_ADD_REG_REG(emit->as, reg_index, reg_base); // add 2*index to base
reg_base = reg_index;
@@ -1561,6 +1563,7 @@ STATIC void emit_native_load_subscr(emit_t *emit) {
break;
}
#endif
need_reg_single(emit, reg_index, 0);
ASM_MOV_REG_IMM(emit->as, reg_index, index_value << 2);
ASM_ADD_REG_REG(emit->as, reg_index, reg_base); // add 4*index to base
reg_base = reg_index;