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py/asmxtensa: Implement the full set of Viper load/store operations.

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This commit expands the implementation of Viper load/store operations
that are optimised for the Xtensa platform.

Now both load and store emitters should generate the shortest possible
sequence in all cases.  Redundant specialised operation emitters have
been aliased to the general case implementation - this was the case of
integer-indexed load/store operations with a fixed offset of zero.

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit is contained in:
Alessandro Gatti
2025-06-10 19:54:28 +02:00
committed by Damien George
parent cd1b921bf2
commit 12f36cc13c
3 changed files with 60 additions and 44 deletions
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18
py/emitnative.c
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@@ -1534,12 +1534,6 @@ static void emit_native_load_subscr(emit_t *emit) {
#ifdef ASM_LOAD8_REG_REG_OFFSET
ASM_LOAD8_REG_REG_OFFSET(emit->as, REG_RET, reg_base, index_value);
#else
#if N_XTENSA || N_XTENSAWIN
if (index_value >= 0 && index_value < 256) {
asm_xtensa_op_l8ui(emit->as, REG_RET, reg_base, index_value);
break;
}
#endif
if (index_value != 0) {
// index is non-zero
need_reg_single(emit, reg_index, 0);
@@ -1776,12 +1770,6 @@ static void emit_native_store_subscr(emit_t *emit) {
#ifdef ASM_STORE8_REG_REG_OFFSET
ASM_STORE8_REG_REG_OFFSET(emit->as, reg_value, reg_base, index_value);
#else
#if N_XTENSA || N_XTENSAWIN
if (index_value >= 0 && index_value < 256) {
asm_xtensa_op_s8i(emit->as, reg_value, reg_base, index_value);
break;
}
#endif
if (index_value != 0) {
// index is non-zero
ASM_MOV_REG_IMM(emit->as, reg_index, index_value);
@@ -1797,12 +1785,6 @@ static void emit_native_store_subscr(emit_t *emit) {
#ifdef ASM_STORE16_REG_REG_OFFSET
ASM_STORE16_REG_REG_OFFSET(emit->as, reg_value, reg_base, index_value);
#else
#if N_XTENSA || N_XTENSAWIN
if (index_value >= 0 && index_value < 256) {
asm_xtensa_op_s16i(emit->as, reg_value, reg_base, index_value);
break;
}
#endif
if (index_value != 0) {
// index is a non-zero immediate
ASM_MOV_REG_IMM(emit->as, reg_index, index_value << 1);