From 2c44f044dea3313718366c43379f0788abbb1c98 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 13 May 2026 12:16:13 +1000 Subject: [PATCH] samd/machine_uart: Only fire the TXIDLE event once. The UART DRE flag is always set if the DATA register is empty. That would lead to a TXIDLE event each time the IRQ handler was run. To fix that, only fire the TXIDLE event if the DRE interrupt flag is enabled. Partially fixes the `tests/extmod/machine_uart_irq_txidle.py` test on `ADAFRUIT_ITSYBITSY_M0_EXPRESS`. Signed-off-by: Damien George --- ports/samd/machine_uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ports/samd/machine_uart.c b/ports/samd/machine_uart.c index ac0c1be581..c39dd8d613 100644 --- a/ports/samd/machine_uart.c +++ b/ports/samd/machine_uart.c @@ -167,7 +167,7 @@ void common_uart_irq_handler(int uart_id) { uart->USART.DATA.bit.DATA = ringbuf_get(&self->write_buffer) | (ringbuf_get(&self->write_buffer) << 8); } - } else { + } else if (uart->USART.INTENCLR.bit.DRE != 0) { #if MICROPY_PY_MACHINE_UART_IRQ // Set the TXIDLE flag mp_irq_flags |= SERCOM_USART_INTFLAG_TXC;