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qemu-riscv: Add new QEMU RV32 port.

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This adds a QEMU-based bare metal RISC-V 32 bits port.  For the time being
only QEMU's "virt" 32 bits board is supported, using the ilp32 ABI and the
RV32IMC architecture.

The top-level README and the run-tests.py files are updated for this new
port.

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
This commit is contained in:
Alessandro Gatti
2023-10-31 21:55:07 +01:00
committed by Damien George
parent d7d77d91be
commit 2d69aab7b3
16 changed files with 1052 additions and 1 deletions
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9
tests/run-tests.py
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@@ -678,6 +678,8 @@ def run_tests(pyb, tests, args, result_dir, num_threads=1):
) # RA fsp rtc function doesn't support nano sec info
elif args.target == "qemu-arm":
skip_tests.add("misc/print_exception.py") # requires sys stdfiles
elif args.target == "qemu-riscv":
skip_tests.add("misc/print_exception.py") # requires sys stdfiles
elif args.target == "webassembly":
skip_tests.add("basics/string_format_modulo.py") # can't print nulls to stdout
skip_tests.add("basics/string_strip.py") # can't print nulls to stdout
@@ -1048,6 +1050,7 @@ the last matching regex is used:
LOCAL_TARGETS = (
"unix",
"qemu-arm",
"qemu-riscv",
"webassembly",
)
EXTERNAL_TARGETS = (
@@ -1151,6 +1154,12 @@ the last matching regex is used:
"inlineasm",
"ports/qemu-arm",
)
elif args.target == "qemu-riscv":
if not args.write_exp:
raise ValueError("--target=qemu-riscv must be used with --write-exp")
# Generate expected output files for qemu run.
# This list should match the test_dirs tuple in tinytest-codegen.py.
test_dirs += ("float",)
elif args.target == "webassembly":
test_dirs += ("float", "ports/webassembly")
else: