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stm32/powerctrl: Add sleep RCC semaphore management for WB55 MCUs.

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Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
This commit is contained in:
Andrew Leech
2022-03-23 17:44:10 +11:00
committed by Damien George
parent 2ec101e609
commit 2eca86e8fa
4 changed files with 123 additions and 8 deletions
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18
ports/stm32/powerctrlboot.c
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@@ -298,21 +298,20 @@ void SystemClock_Config(void) {
}
#elif defined(STM32WB)
#include "stm32wbxx_ll_hsem.h"
// This semaphore protected access to the CLK48 configuration.
// CPU1 should hold this semaphore while the USB peripheral is in use.
// See AN5289 and https://github.com/micropython/micropython/issues/6316.
#define CLK48_SEMID (5)
void SystemClock_Config(void) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
// Enable the 32MHz external oscillator
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY)) {
}
// Prevent CPU2 from disabling CLK48.
while (LL_HSEM_1StepLock(HSEM, CLK48_SEMID)) {
// This semaphore protected access to the CLK48 configuration.
// CPU1 should hold this semaphore while the USB peripheral is in use.
// See AN5289 and https://github.com/micropython/micropython/issues/6316.
while (LL_HSEM_1StepLock(HSEM, CFG_HW_CLK48_CONFIG_SEMID)) {
}
// Use HSE and the PLL to get a 64MHz SYSCLK
@@ -349,6 +348,9 @@ void SystemClock_Config(void) {
SystemCoreClockUpdate();
powerctrl_config_systick();
// Release RCC semaphore
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
}
#elif defined(STM32WL)