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stm32/eth: Add support for gigabit RGMII peripheral interface.

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Signed-off-by: Damien George <damien@micropython.org>
This commit is contained in:
Damien George
2025-10-27 14:49:15 +11:00
parent d1e993f872
commit 45956a9516
2 changed files with 42 additions and 10 deletions
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20
ports/stm32/boards/stm32n657_af.csv
View File

@@ -39,19 +39,25 @@ PortE,PE12, , , ,
PortE,PE13, , , , ,I2C4_SCL , , , , , , , , , , , ,
PortE,PE14, , , , ,I2C4_SDA , , , , , , , , , , , ,
PortE,PE15, , , , , ,SPI5_SCK , , , , , , , , , , ,
PortF,PF0 , , , , , , , , , , , , ,ETH1_RGMII_GTX_CLK , , , ,
PortF,PF2 , , , , , , , , , , , ,ETH1_RGMII_CLK125 , , , , ,
PortF,PF3 , , , , , , , ,USART2_RTS , , , , , , , , ,ADC1_INP16
PortF,PF4 , , , , , , , , , , , ,ETH1_MDIO , , , , ,
PortF,PF6 , , , , , , , ,USART2_RX , , , , , , , , ,
PortF,PF7 , , , , , , , , , , , ,ETH1_RMII_REF_CLK , , , , ,
PortF,PF10, , , , , , , , , , , ,ETH1_RMII_CRS_DV , , , , ,
PortF,PF11, , , , , , , , , , , ,ETH1_RMII_TX_EN , , , , ,
PortF,PF12, , , , , , , , , , , ,ETH1_RMII_TXD0 , , , , ,
PortF,PF13, , , , , , , , , , , ,ETH1_RMII_TXD1 , , , , ,
PortF,PF14, , , , , , , , , , , ,ETH1_RMII_RXD0 , , , , ,
PortF,PF15, , , , , , , , , , , ,ETH1_RMII_RXD1 , , , , ,
PortF,PF7 , , , , , , , , , , , ,ETH1_RMII_REF_CLK/ETH1_RGMII_RX_CLK , , , , ,
PortF,PF8 , , , , , , , , , , , ,ETH1_RGMII_RXD2 , , , , ,
PortF,PF9 , , , , , , , , , , , ,ETH1_RGMII_RXD3 , , , , ,
PortF,PF10, , , , , , , , , , , ,ETH1_RMII_CRS_DV/ETH1_RGMII_RX_CTL , , , , ,
PortF,PF11, , , , , , , , , , , ,ETH1_RMII_TX_EN/ETH1_RGMII_TX_CTL , , , , ,
PortF,PF12, , , , , , , , , , , ,ETH1_RMII_TXD0/ETH1_RGMII_TXD0 , , , , ,
PortF,PF13, , , , , , , , , , , ,ETH1_RMII_TXD1/ETH1_RGMII_TXD1 , , , , ,
PortF,PF14, , , , , , , , , , , ,ETH1_RMII_RXD0/ETH1_RGMII_RXD0 , , , , ,
PortF,PF15, , , , , , , , , , , ,ETH1_RMII_RXD1/ETH1_RGMII_RXD1 , , , , ,
PortG,PG0 , , ,TIM12_CH1 , , , , , , , , , , , , , ,
PortG,PG1 , , , , , ,SPI5_MISO , , , , , , , , , , ,
PortG,PG2 , , , , , ,SPI5_MOSI , , , , , , , , , , ,
PortG,PG3 , , , , , , , , , , , ,ETH1_RGMII_TXD2 , , , , ,
PortG,PG4 , , , , , , , , , , , ,ETH1_RGMII_TXD3 , , , , ,
PortG,PG5 , , , , , , , ,USART2_CTS , , , , , , , , ,
PortG,PG8 , , , , , , , , , , , ,SDMMC2_D1 , , , , ,
PortG,PG11, , , , , , , , , , , ,ETH1_MDC , , , , ,
1 Port Pin AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 ADC
39 PortE PE13 I2C4_SCL
40 PortE PE14 I2C4_SDA
41 PortE PE15 SPI5_SCK
42 PortF PF0 ETH1_RGMII_GTX_CLK
43 PortF PF2 ETH1_RGMII_CLK125
44 PortF PF3 USART2_RTS ADC1_INP16
45 PortF PF4 ETH1_MDIO
46 PortF PF6 USART2_RX
47 PortF PF7 ETH1_RMII_REF_CLK ETH1_RMII_REF_CLK/ETH1_RGMII_RX_CLK
48 PortF PF10 PF8 ETH1_RMII_CRS_DV ETH1_RGMII_RXD2
49 PortF PF11 PF9 ETH1_RMII_TX_EN ETH1_RGMII_RXD3
50 PortF PF12 PF10 ETH1_RMII_TXD0 ETH1_RMII_CRS_DV/ETH1_RGMII_RX_CTL
51 PortF PF13 PF11 ETH1_RMII_TXD1 ETH1_RMII_TX_EN/ETH1_RGMII_TX_CTL
52 PortF PF14 PF12 ETH1_RMII_RXD0 ETH1_RMII_TXD0/ETH1_RGMII_TXD0
53 PortF PF15 PF13 ETH1_RMII_RXD1 ETH1_RMII_TXD1/ETH1_RGMII_TXD1
54 PortF PF14 ETH1_RMII_RXD0/ETH1_RGMII_RXD0
55 PortF PF15 ETH1_RMII_RXD1/ETH1_RGMII_RXD1
56 PortG PG0 TIM12_CH1
57 PortG PG1 SPI5_MISO
58 PortG PG2 SPI5_MOSI
59 PortG PG3 ETH1_RGMII_TXD2
60 PortG PG4 ETH1_RGMII_TXD3
61 PortG PG5 USART2_CTS
62 PortG PG8 SDMMC2_D1
63 PortG PG11 ETH1_MDC

32
ports/stm32/eth.c
View File

@@ -225,9 +225,12 @@ int eth_init(eth_t *self, int mac_idx, uint32_t phy_addr, int phy_type) {
return -1;
}
// Configure GPIO
// Configure GPIO for management data.
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_MDC, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(MDC));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_MDIO, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(MDIO));
#if defined(MICROPY_HW_ETH_RMII_REF_CLK)
// Configure GPIO for RMII interface.
mp_hal_pin_config_alt_static_speed(MICROPY_HW_ETH_RMII_REF_CLK, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_MEDIUM, STATIC_AF_ETH(RMII_REF_CLK));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RMII_CRS_DV, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RMII_CRS_DV));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RMII_RXD0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RMII_RXD0));
@@ -235,6 +238,22 @@ int eth_init(eth_t *self, int mac_idx, uint32_t phy_addr, int phy_type) {
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RMII_TX_EN, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RMII_TX_EN));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RMII_TXD0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RMII_TXD0));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RMII_TXD1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RMII_TXD1));
#else
// Configure GPIO for RGMII interface.
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RGMII_CLK125, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RGMII_CLK125));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RGMII_GTX_CLK, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RGMII_GTX_CLK));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RGMII_TXD0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RGMII_TXD0));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RGMII_TXD1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RGMII_TXD1));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RGMII_TXD2, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RGMII_TXD2));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RGMII_TXD3, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RGMII_TXD3));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RGMII_TX_CTL, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RGMII_TX_CTL));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RGMII_RX_CLK, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RGMII_RX_CLK));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RGMII_RXD0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RGMII_RXD0));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RGMII_RXD1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RGMII_RXD1));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RGMII_RXD2, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RGMII_RXD2));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RGMII_RXD3, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RGMII_RXD3));
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_RGMII_RX_CTL, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH(RGMII_RX_CTL));
#endif
// Enable peripheral clock
#if defined(STM32H5)
@@ -290,14 +309,18 @@ static int eth_mac_init(eth_t *self) {
LL_RCC_SetETHPTPClockSource(LL_RCC_ETH1PTP_CLKSOURCE_HCLK); // max 200MHz
#endif
// Select RMII interface
// Select RMII or RGMII interface
#if defined(STM32H5)
__HAL_RCC_SBS_CLK_ENABLE();
SBS->PMCR = (SBS->PMCR & ~SBS_PMCR_ETH_SEL_PHY_Msk) | SBS_PMCR_ETH_SEL_PHY_2;
#elif defined(STM32H7)
SYSCFG->PMCR = (SYSCFG->PMCR & ~SYSCFG_PMCR_EPIS_SEL_Msk) | SYSCFG_PMCR_EPIS_SEL_2;
#elif defined(STM32N6)
#if defined(MICROPY_HW_ETH_RGMII_CLK125)
LL_RCC_SetETHPHYInterface(LL_RCC_ETH1PHY_IF_RGMII);
#else
LL_RCC_SetETHPHYInterface(LL_RCC_ETH1PHY_IF_RMII);
#endif
#else
__HAL_RCC_SYSCFG_CLK_ENABLE();
SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
@@ -602,11 +625,14 @@ static int eth_mac_init(eth_t *self) {
#if defined(STM32N6)
if (!(phy_scsr & PHY_SPEED_1000HALF)) {
maccr |= ETH_MACCR_PS;
}
maccr |=
ETH_MACCR_IPG_96BIT
| ETH_MACCR_SARC_REPADDR0
| ETH_MACCR_IPC
| ETH_MACCR_PS
| ETH_MACCR_BL_10
| ETH_MACCR_PRELEN_7;