diff --git a/ports/stm32/eth_phy.c b/ports/stm32/eth_phy.c index 56cddba9c5..2435cc3e03 100644 --- a/ports/stm32/eth_phy.c +++ b/ports/stm32/eth_phy.c @@ -31,8 +31,9 @@ #if defined(MICROPY_HW_ETH_MDC) #define PHY_SCSR_LAN87XX (0x001f) -#define PHY_SCSR_LAN87XX_SPEED_Pos (2) -#define PHY_SCSR_LAN87XX_SPEED_Msk (7) +#define PHY_SCSR_LAN87XX_10M_Msk (0x0004) +#define PHY_SCSR_LAN87XX_100M_Msk (0x0008) +#define PHY_SCSR_LAN87XX_DUPLEX_Msk (0x0010) #define PHY_SCSR_DP838XX (0x0010) #define PHY_RECR_DP838XX (0x0015) @@ -41,8 +42,18 @@ int16_t eth_phy_lan87xx_get_link_status(uint32_t phy_addr) { // Get the link mode & speed - int16_t scsr = eth_phy_read(phy_addr, PHY_SCSR_LAN87XX); - return (scsr >> PHY_SCSR_LAN87XX_SPEED_Pos) & PHY_SCSR_LAN87XX_SPEED_Msk; + uint16_t scsr = eth_phy_read(phy_addr, PHY_SCSR_LAN87XX); + int16_t status = 0; + if (scsr & PHY_SCSR_LAN87XX_10M_Msk) { + status |= PHY_SPEED_10HALF; + } + if (scsr & PHY_SCSR_LAN87XX_100M_Msk) { + status |= PHY_SPEED_100HALF; + } + if (scsr & PHY_SCSR_LAN87XX_DUPLEX_Msk) { + status |= PHY_DUPLEX; + } + return status; } int16_t eth_phy_dp838xx_get_link_status(uint32_t phy_addr) { diff --git a/ports/stm32/eth_phy.h b/ports/stm32/eth_phy.h index dccfb7951a..1f2045082d 100644 --- a/ports/stm32/eth_phy.h +++ b/ports/stm32/eth_phy.h @@ -50,11 +50,13 @@ #define PHY_ANAR_SPEED_100FULL (0x0100) #define PHY_ANAR_IEEE802_3 (0x0001) -#define PHY_SPEED_10HALF (1) -#define PHY_SPEED_10FULL (5) -#define PHY_SPEED_100HALF (2) -#define PHY_SPEED_100FULL (6) -#define PHY_DUPLEX (4) +#define PHY_SPEED_10HALF (0x01) +#define PHY_SPEED_100HALF (0x02) +#define PHY_SPEED_1000HALF (0x04) +#define PHY_DUPLEX (0x08) +#define PHY_SPEED_10FULL (PHY_DUPLEX | PHY_SPEED_10HALF) +#define PHY_SPEED_100FULL (PHY_DUPLEX | PHY_SPEED_100HALF) +#define PHY_SPEED_1000FULL (PHY_DUPLEX | PHY_SPEED_1000HALF) uint32_t eth_phy_read(uint32_t phy_addr, uint32_t reg); void eth_phy_write(uint32_t phy_addr, uint32_t reg, uint32_t val);