diff --git a/tests/extmod/machine_uart_tx.py b/tests/extmod/machine_uart_tx.py
index 70d57be464..1ff9af64bd 100644
--- a/tests/extmod/machine_uart_tx.py
+++ b/tests/extmod/machine_uart_tx.py
@@ -19,6 +19,8 @@ if "alif" in sys.platform:
     bit_margin = 1
 elif "esp32" in sys.platform:
     timing_margin_us = 400
+elif "esp8266" in sys.platform:
+    timing_margin_us = 4100
 elif "mimxrt" in sys.platform:
     initial_delay_ms = 20  # UART sends idle frame after init, so wait for that
     bit_margin = 1
diff --git a/tests/target_wiring/esp8266.py b/tests/target_wiring/esp8266.py
new file mode 100644
index 0000000000..336deb3dda
--- /dev/null
+++ b/tests/target_wiring/esp8266.py
@@ -0,0 +1,7 @@
+# Target wiring for general esp8266 board.
+#
+# Connect:
+# - GPIO4 to GPIO5
+
+uart_loopback_args = (1,)
+uart_loopback_kwargs = {}