From a4a098ff8210a086d947b53771ed747a8998cef0 Mon Sep 17 00:00:00 2001
From: Damien George <damien@micropython.org>
Date: Thu, 26 Jun 2025 00:29:22 +1000
Subject: [PATCH] tests/extmod_hardware/machine_uart_irq_rxidle.py: Ignore
 inital IRQ.

On stm32, the hardware generates an RXIDLE IRQ after enabling the UART,
because the RX line is technically idle.

Signed-off-by: Damien George <damien@micropython.org>
---
 tests/extmod_hardware/machine_uart_irq_rxidle.py | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/tests/extmod_hardware/machine_uart_irq_rxidle.py b/tests/extmod_hardware/machine_uart_irq_rxidle.py
index 634369150c..ced24dca64 100644
--- a/tests/extmod_hardware/machine_uart_irq_rxidle.py
+++ b/tests/extmod_hardware/machine_uart_irq_rxidle.py
@@ -13,6 +13,9 @@ except (ImportError, AttributeError):
 
 import time, sys
 
+# Target tuning options.
+tune_wait_initial_rxidle = False
+
 # Configure pins based on the target.
 if "alif" in sys.platform:
     uart_id = 1
@@ -26,6 +29,7 @@ elif "mimxrt" in sys.platform:
     uart_id = 1
     tx_pin = None
 elif "pyboard" in sys.platform:
+    tune_wait_initial_rxidle = True
     if "STM32WB" in sys.implementation._machine:
         # LPUART(1) is on PA2/PA3
         uart_id = "LP1"
@@ -69,8 +73,15 @@ for bits_per_s in (2400, 9600, 115200):
     else:
         uart = UART(uart_id, bits_per_s, tx=tx_pin, rx=rx_pin)
 
+    # Ignore a possible initial RXIDLE condition after creating UART.
+    if tune_wait_initial_rxidle:
+        uart.irq(lambda _: None, uart.IRQ_RXIDLE)
+        time.sleep_ms(10)
+
+    # Configure desired IRQ.
     uart.irq(irq, uart.IRQ_RXIDLE)
 
+    # Write data and wait for IRQ.
     print("write", bits_per_s)
     uart.write(text)
     uart.flush()